[linux-2.6-block.git] / arch / powerpc / platforms / cell / spufs / hw_ops.c

/* hw_ops.c - query/set operations on active SPU context.
 *
 * Copyright (C) IBM 2005
 * Author: Mark Nutter <mnutter@us.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/poll.h>
#include <linux/smp.h>
#include <linux/stddef.h>
#include <linux/unistd.h>

#include <asm/io.h>
#include <asm/spu.h>
#include <asm/spu_priv1.h>
#include <asm/spu_csa.h>
#include <asm/mmu_context.h>
#include "spufs.h"

static int spu_hw_mbox_read(struct spu_context *ctx, u32 * data)
{
	struct spu *spu = ctx->spu;
	struct spu_problem __iomem *prob = spu->problem;
	u32 mbox_stat;
	int ret = 0;

	spin_lock_irq(&spu->register_lock);
	mbox_stat = in_be32(&prob->mb_stat_R);
	if (mbox_stat & 0x0000ff) {
		*data = in_be32(&prob->pu_mb_R);
		ret = 4;
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static u32 spu_hw_mbox_stat_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->mb_stat_R);
}

static __poll_t spu_hw_mbox_stat_poll(struct spu_context *ctx, __poll_t events)
{
	struct spu *spu = ctx->spu;
	__poll_t ret = 0;
	u32 stat;

	spin_lock_irq(&spu->register_lock);
	stat = in_be32(&spu->problem->mb_stat_R);

	/* if the requested event is there, return the poll
	   mask, otherwise enable the interrupt to get notified,
	   but first mark any pending interrupts as done so
	   we don't get woken up unnecessarily */

	if (events & (EPOLLIN | EPOLLRDNORM)) {
		if (stat & 0xff0000)
			ret |= EPOLLIN | EPOLLRDNORM;
		else {
			spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);
			spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
		}
	}
	if (events & (EPOLLOUT | EPOLLWRNORM)) {
		if (stat & 0x00ff00)
			ret = EPOLLOUT | EPOLLWRNORM;
		else {
			spu_int_stat_clear(spu, 2,
					CLASS2_MAILBOX_THRESHOLD_INTR);
			spu_int_mask_or(spu, 2,
					CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
		}
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data)
{
	struct spu *spu = ctx->spu;
	struct spu_problem __iomem *prob = spu->problem;
	struct spu_priv2 __iomem *priv2 = spu->priv2;
	int ret;

	spin_lock_irq(&spu->register_lock);
	if (in_be32(&prob->mb_stat_R) & 0xff0000) {
		/* read the first available word */
		*data = in_be64(&priv2->puint_mb_R);
		ret = 4;
	} else {
		/* make sure we get woken up by the interrupt */
		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
		ret = 0;
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
{
	struct spu *spu = ctx->spu;
	struct spu_problem __iomem *prob = spu->problem;
	int ret;

	spin_lock_irq(&spu->register_lock);
	if (in_be32(&prob->mb_stat_R) & 0x00ff00) {
		/* we have space to write wbox_data to */
		out_be32(&prob->spu_mb_W, data);
		ret = 4;
	} else {
		/* make sure we get woken up by the interrupt when space
		   becomes available */
		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
		ret = 0;
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
{
	out_be32(&ctx->spu->problem->signal_notify1, data);
}

static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
{
	out_be32(&ctx->spu->problem->signal_notify2, data);
}

static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val)
{
	struct spu *spu = ctx->spu;
	struct spu_priv2 __iomem *priv2 = spu->priv2;
	u64 tmp;

	spin_lock_irq(&spu->register_lock);
	tmp = in_be64(&priv2->spu_cfg_RW);
	if (val)
		tmp |= 1;
	else
		tmp &= ~1;
	out_be64(&priv2->spu_cfg_RW, tmp);
	spin_unlock_irq(&spu->register_lock);
}

static u64 spu_hw_signal1_type_get(struct spu_context *ctx)
{
	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
}

static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val)
{
	struct spu *spu = ctx->spu;
	struct spu_priv2 __iomem *priv2 = spu->priv2;
	u64 tmp;

	spin_lock_irq(&spu->register_lock);
	tmp = in_be64(&priv2->spu_cfg_RW);
	if (val)
		tmp |= 2;
	else
		tmp &= ~2;
	out_be64(&priv2->spu_cfg_RW, tmp);
	spin_unlock_irq(&spu->register_lock);
}

static u64 spu_hw_signal2_type_get(struct spu_context *ctx)
{
	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
}

static u32 spu_hw_npc_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->spu_npc_RW);
}

static void spu_hw_npc_write(struct spu_context *ctx, u32 val)
{
	out_be32(&ctx->spu->problem->spu_npc_RW, val);
}

static u32 spu_hw_status_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->spu_status_R);
}

static char *spu_hw_get_ls(struct spu_context *ctx)
{
	return ctx->spu->local_store;
}

static void spu_hw_privcntl_write(struct spu_context *ctx, u64 val)
{
	out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
}

static u32 spu_hw_runcntl_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->spu_runcntl_RW);
}

static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
{
	spin_lock_irq(&ctx->spu->register_lock);
	if (val & SPU_RUNCNTL_ISOLATE)
		spu_hw_privcntl_write(ctx,
			SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK);
	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
	spin_unlock_irq(&ctx->spu->register_lock);
}

static void spu_hw_runcntl_stop(struct spu_context *ctx)
{
	spin_lock_irq(&ctx->spu->register_lock);
	out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
	while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
		cpu_relax();
	spin_unlock_irq(&ctx->spu->register_lock);
}

static void spu_hw_master_start(struct spu_context *ctx)
{
	struct spu *spu = ctx->spu;
	u64 sr1;

	spin_lock_irq(&spu->register_lock);
	sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
	spu_mfc_sr1_set(spu, sr1);
	spin_unlock_irq(&spu->register_lock);
}

static void spu_hw_master_stop(struct spu_context *ctx)
{
	struct spu *spu = ctx->spu;
	u64 sr1;

	spin_lock_irq(&spu->register_lock);
	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
	spu_mfc_sr1_set(spu, sr1);
	spin_unlock_irq(&spu->register_lock);
}

static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
{
	struct spu_problem __iomem *prob = ctx->spu->problem;
	int ret;

	spin_lock_irq(&ctx->spu->register_lock);
	ret = -EAGAIN;
	if (in_be32(&prob->dma_querytype_RW))
		goto out;
	ret = 0;
	out_be32(&prob->dma_querymask_RW, mask);
	out_be32(&prob->dma_querytype_RW, mode);
out:
	spin_unlock_irq(&ctx->spu->register_lock);
	return ret;
}

static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
{
	return in_be32(&ctx->spu->problem->dma_tagstatus_R);
}

static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->dma_qstatus_R);
}

static int spu_hw_send_mfc_command(struct spu_context *ctx,
					struct mfc_dma_command *cmd)
{
	u32 status;
	struct spu_problem __iomem *prob = ctx->spu->problem;

	spin_lock_irq(&ctx->spu->register_lock);
	out_be32(&prob->mfc_lsa_W, cmd->lsa);
	out_be64(&prob->mfc_ea_W, cmd->ea);
	out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
				cmd->size << 16 | cmd->tag);
	out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
				cmd->class << 16 | cmd->cmd);
	status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
	spin_unlock_irq(&ctx->spu->register_lock);

	switch (status & 0xffff) {
	case 0:
		return 0;
	case 2:
		return -EAGAIN;
	default:
		return -EINVAL;
	}
}

static void spu_hw_restart_dma(struct spu_context *ctx)
{
	struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;

	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))
		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
}

struct spu_context_ops spu_hw_ops = {
	.mbox_read = spu_hw_mbox_read,
	.mbox_stat_read = spu_hw_mbox_stat_read,
	.mbox_stat_poll = spu_hw_mbox_stat_poll,
	.ibox_read = spu_hw_ibox_read,
	.wbox_write = spu_hw_wbox_write,
	.signal1_write = spu_hw_signal1_write,
	.signal2_write = spu_hw_signal2_write,
	.signal1_type_set = spu_hw_signal1_type_set,
	.signal1_type_get = spu_hw_signal1_type_get,
	.signal2_type_set = spu_hw_signal2_type_set,
	.signal2_type_get = spu_hw_signal2_type_get,
	.npc_read = spu_hw_npc_read,
	.npc_write = spu_hw_npc_write,
	.status_read = spu_hw_status_read,
	.get_ls = spu_hw_get_ls,
	.privcntl_write = spu_hw_privcntl_write,
	.runcntl_read = spu_hw_runcntl_read,
	.runcntl_write = spu_hw_runcntl_write,
	.runcntl_stop = spu_hw_runcntl_stop,
	.master_start = spu_hw_master_start,
	.master_stop = spu_hw_master_stop,
	.set_mfc_query = spu_hw_set_mfc_query,
	.read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
	.get_mfc_free_elements = spu_hw_get_mfc_free_elements,
	.send_mfc_command = spu_hw_send_mfc_command,
	.restart_dma = spu_hw_restart_dma,
};
Commit	Line	Data
8b3d6663 AB	1	/* hw_ops.c - query/set operations on active SPU context.
	2	*
	3	* Copyright (C) IBM 2005
	4	* Author: Mark Nutter <mnutter@us.ibm.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2, or (at your option)
	9	* any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
8b3d6663 AB	21	#include <linux/errno.h>
	22	#include <linux/sched.h>
	23	#include <linux/kernel.h>
	24	#include <linux/mm.h>
3a843d7c	25	#include <linux/poll.h>
8b3d6663	26	#include <linux/smp.h>
8b3d6663 AB	27	#include <linux/stddef.h>
	28	#include <linux/unistd.h>
	29
	30	#include <asm/io.h>
	31	#include <asm/spu.h>
540270d8	32	#include <asm/spu_priv1.h>
8b3d6663 AB	33	#include <asm/spu_csa.h>
	34	#include <asm/mmu_context.h>
	35	#include "spufs.h"
	36
	37	static int spu_hw_mbox_read(struct spu_context ctx, u32 data)
	38	{
	39	struct spu *spu = ctx->spu;
	40	struct spu_problem __iomem *prob = spu->problem;
	41	u32 mbox_stat;
	42	int ret = 0;
	43
	44	spin_lock_irq(&spu->register_lock);
	45	mbox_stat = in_be32(&prob->mb_stat_R);
	46	if (mbox_stat & 0x0000ff) {
	47	*data = in_be32(&prob->pu_mb_R);
	48	ret = 4;
	49	}
	50	spin_unlock_irq(&spu->register_lock);
	51	return ret;
	52	}
	53
	54	static u32 spu_hw_mbox_stat_read(struct spu_context *ctx)
	55	{
	56	return in_be32(&ctx->spu->problem->mb_stat_R);
	57	}
	58
8153a5ea	59	static __poll_t spu_hw_mbox_stat_poll(struct spu_context *ctx, __poll_t events)
3a843d7c AB	60	{
3a843d7c AB	61	struct spu *spu = ctx->spu;
8153a5ea	62	__poll_t ret = 0;
3a843d7c AB	63	u32 stat;
	64
	65	spin_lock_irq(&spu->register_lock);
	66	stat = in_be32(&spu->problem->mb_stat_R);
	67
	68	/* if the requested event is there, return the poll
	69	mask, otherwise enable the interrupt to get notified,
	70	but first mark any pending interrupts as done so
	71	we don't get woken up unnecessarily */
	72
a9a08845	73	if (events & (EPOLLIN \| EPOLLRDNORM)) {
3a843d7c	74	if (stat & 0xff0000)
a9a08845	75	ret \|= EPOLLIN \| EPOLLRDNORM;
3a843d7c	76	else {
8af30675 JK	77	spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);
8af30675 JK	78	spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
3a843d7c AB	79	}
3a843d7c AB	80	}
a9a08845	81	if (events & (EPOLLOUT \| EPOLLWRNORM)) {
3a843d7c	82	if (stat & 0x00ff00)
a9a08845	83	ret = EPOLLOUT \| EPOLLWRNORM;
3a843d7c	84	else {
8af30675 JK	85	spu_int_stat_clear(spu, 2,
	86	CLASS2_MAILBOX_THRESHOLD_INTR);
	87	spu_int_mask_or(spu, 2,
	88	CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
3a843d7c AB	89	}
	90	}
	91	spin_unlock_irq(&spu->register_lock);
	92	return ret;
	93	}
	94
8b3d6663 AB	95	static int spu_hw_ibox_read(struct spu_context ctx, u32 data)
	96	{
	97	struct spu *spu = ctx->spu;
	98	struct spu_problem __iomem *prob = spu->problem;
8b3d6663 AB	99	struct spu_priv2 __iomem *priv2 = spu->priv2;
	100	int ret;
	101
	102	spin_lock_irq(&spu->register_lock);
	103	if (in_be32(&prob->mb_stat_R) & 0xff0000) {
	104	/* read the first available word */
	105	*data = in_be64(&priv2->puint_mb_R);
	106	ret = 4;
	107	} else {
	108	/* make sure we get woken up by the interrupt */
8af30675	109	spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
8b3d6663 AB	110	ret = 0;
	111	}
	112	spin_unlock_irq(&spu->register_lock);
	113	return ret;
	114	}
	115
	116	static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
	117	{
	118	struct spu *spu = ctx->spu;
	119	struct spu_problem __iomem *prob = spu->problem;
8b3d6663 AB	120	int ret;
	121
	122	spin_lock_irq(&spu->register_lock);
	123	if (in_be32(&prob->mb_stat_R) & 0x00ff00) {
	124	/* we have space to write wbox_data to */
	125	out_be32(&prob->spu_mb_W, data);
	126	ret = 4;
	127	} else {
	128	/* make sure we get woken up by the interrupt when space
	129	becomes available */
8af30675	130	spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
8b3d6663 AB	131	ret = 0;
	132	}
	133	spin_unlock_irq(&spu->register_lock);
	134	return ret;
	135	}
	136
8b3d6663 AB	137	static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
	138	{
	139	out_be32(&ctx->spu->problem->signal_notify1, data);
	140	}
	141
8b3d6663 AB	142	static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
	143	{
	144	out_be32(&ctx->spu->problem->signal_notify2, data);
	145	}
	146
	147	static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val)
	148	{
	149	struct spu *spu = ctx->spu;
	150	struct spu_priv2 __iomem *priv2 = spu->priv2;
	151	u64 tmp;
	152
	153	spin_lock_irq(&spu->register_lock);
	154	tmp = in_be64(&priv2->spu_cfg_RW);
	155	if (val)
	156	tmp \|= 1;
	157	else
	158	tmp &= ~1;
	159	out_be64(&priv2->spu_cfg_RW, tmp);
	160	spin_unlock_irq(&spu->register_lock);
	161	}
	162
	163	static u64 spu_hw_signal1_type_get(struct spu_context *ctx)
	164	{
	165	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
	166	}
	167
	168	static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val)
	169	{
	170	struct spu *spu = ctx->spu;
	171	struct spu_priv2 __iomem *priv2 = spu->priv2;
	172	u64 tmp;
	173
	174	spin_lock_irq(&spu->register_lock);
	175	tmp = in_be64(&priv2->spu_cfg_RW);
	176	if (val)
	177	tmp \|= 2;
	178	else
	179	tmp &= ~2;
	180	out_be64(&priv2->spu_cfg_RW, tmp);
	181	spin_unlock_irq(&spu->register_lock);
	182	}
	183
	184	static u64 spu_hw_signal2_type_get(struct spu_context *ctx)
	185	{
	186	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
	187	}
	188
	189	static u32 spu_hw_npc_read(struct spu_context *ctx)
	190	{
	191	return in_be32(&ctx->spu->problem->spu_npc_RW);
	192	}
	193
	194	static void spu_hw_npc_write(struct spu_context *ctx, u32 val)
	195	{
	196	out_be32(&ctx->spu->problem->spu_npc_RW, val);
	197	}
	198
	199	static u32 spu_hw_status_read(struct spu_context *ctx)
	200	{
	201	return in_be32(&ctx->spu->problem->spu_status_R);
	202	}
	203
	204	static char spu_hw_get_ls(struct spu_context ctx)
	205	{
206	return ctx->spu->local_store;
207	}
208
cc210b3e LB	209	static void spu_hw_privcntl_write(struct spu_context *ctx, u64 val)
	210	{
	211	out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
	212	}
	213
3960c260 JK	214	static u32 spu_hw_runcntl_read(struct spu_context *ctx)
	215	{
	216	return in_be32(&ctx->spu->problem->spu_runcntl_RW);
	217	}
	218
5110459f AB	219	static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
5110459f AB	220	{
5737edd1 MN	221	spin_lock_irq(&ctx->spu->register_lock);
5737edd1 MN	222	if (val & SPU_RUNCNTL_ISOLATE)
cc210b3e LB	223	spu_hw_privcntl_write(ctx,
cc210b3e LB	224	SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK);
5110459f	225	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
5737edd1	226	spin_unlock_irq(&ctx->spu->register_lock);
5110459f AB	227	}
5110459f AB	228
c25620d7 MN	229	static void spu_hw_runcntl_stop(struct spu_context *ctx)
	230	{
	231	spin_lock_irq(&ctx->spu->register_lock);
	232	out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
	233	while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
	234	cpu_relax();
	235	spin_unlock_irq(&ctx->spu->register_lock);
	236	}
	237
ee2d7340	238	static void spu_hw_master_start(struct spu_context *ctx)
5110459f	239	{
ee2d7340 AB	240	struct spu *spu = ctx->spu;
	241	u64 sr1;
	242
	243	spin_lock_irq(&spu->register_lock);
	244	sr1 = spu_mfc_sr1_get(spu) \| MFC_STATE1_MASTER_RUN_CONTROL_MASK;
	245	spu_mfc_sr1_set(spu, sr1);
	246	spin_unlock_irq(&spu->register_lock);
	247	}
	248
	249	static void spu_hw_master_stop(struct spu_context *ctx)
	250	{
	251	struct spu *spu = ctx->spu;
	252	u64 sr1;
	253
	254	spin_lock_irq(&spu->register_lock);
	255	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
	256	spu_mfc_sr1_set(spu, sr1);
	257	spin_unlock_irq(&spu->register_lock);
5110459f AB	258	}
5110459f AB	259
a33a7d73 AB	260	static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
a33a7d73 AB	261	{
ed2bfcd2	262	struct spu_problem __iomem *prob = ctx->spu->problem;
a33a7d73 AB	263	int ret;
	264
	265	spin_lock_irq(&ctx->spu->register_lock);
	266	ret = -EAGAIN;
	267	if (in_be32(&prob->dma_querytype_RW))
	268	goto out;
	269	ret = 0;
	270	out_be32(&prob->dma_querymask_RW, mask);
	271	out_be32(&prob->dma_querytype_RW, mode);
	272	out:
	273	spin_unlock_irq(&ctx->spu->register_lock);
	274	return ret;
	275	}
	276
	277	static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
	278	{
	279	return in_be32(&ctx->spu->problem->dma_tagstatus_R);
	280	}
	281
	282	static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
	283	{
	284	return in_be32(&ctx->spu->problem->dma_qstatus_R);
	285	}
	286
	287	static int spu_hw_send_mfc_command(struct spu_context *ctx,
	288	struct mfc_dma_command *cmd)
	289	{
	290	u32 status;
ed2bfcd2	291	struct spu_problem __iomem *prob = ctx->spu->problem;
a33a7d73 AB	292
	293	spin_lock_irq(&ctx->spu->register_lock);
	294	out_be32(&prob->mfc_lsa_W, cmd->lsa);
	295	out_be64(&prob->mfc_ea_W, cmd->ea);
	296	out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
	297	cmd->size << 16 \| cmd->tag);
	298	out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
	299	cmd->class << 16 \| cmd->cmd);
	300	status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
	301	spin_unlock_irq(&ctx->spu->register_lock);
	302
	303	switch (status & 0xffff) {
	304	case 0:
	305	return 0;
	306	case 2:
	307	return -EAGAIN;
	308	default:
	309	return -EINVAL;
	310	}
	311	}
	312
57dace23 AB	313	static void spu_hw_restart_dma(struct spu_context *ctx)
	314	{
	315	struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;
	316
	317	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))
	318	out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
	319	}
	320
8b3d6663 AB	321	struct spu_context_ops spu_hw_ops = {
	322	.mbox_read = spu_hw_mbox_read,
	323	.mbox_stat_read = spu_hw_mbox_stat_read,
3a843d7c	324	.mbox_stat_poll = spu_hw_mbox_stat_poll,
8b3d6663 AB	325	.ibox_read = spu_hw_ibox_read,
8b3d6663 AB	326	.wbox_write = spu_hw_wbox_write,
8b3d6663	327	.signal1_write = spu_hw_signal1_write,
8b3d6663 AB	328	.signal2_write = spu_hw_signal2_write,
	329	.signal1_type_set = spu_hw_signal1_type_set,
	330	.signal1_type_get = spu_hw_signal1_type_get,
	331	.signal2_type_set = spu_hw_signal2_type_set,
	332	.signal2_type_get = spu_hw_signal2_type_get,
	333	.npc_read = spu_hw_npc_read,
	334	.npc_write = spu_hw_npc_write,
	335	.status_read = spu_hw_status_read,
	336	.get_ls = spu_hw_get_ls,
cc210b3e	337	.privcntl_write = spu_hw_privcntl_write,
3960c260	338	.runcntl_read = spu_hw_runcntl_read,
5110459f	339	.runcntl_write = spu_hw_runcntl_write,
c25620d7	340	.runcntl_stop = spu_hw_runcntl_stop,
ee2d7340 AB	341	.master_start = spu_hw_master_start,
ee2d7340 AB	342	.master_stop = spu_hw_master_stop,
a33a7d73 AB	343	.set_mfc_query = spu_hw_set_mfc_query,
	344	.read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
	345	.get_mfc_free_elements = spu_hw_get_mfc_free_elements,
	346	.send_mfc_command = spu_hw_send_mfc_command,
57dace23	347	.restart_dma = spu_hw_restart_dma,
8b3d6663	348	};