Commit | Line | Data |
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f0831acc | 1 | /* |
540270d8 GL |
2 | * spu hypervisor abstraction for direct hardware access. |
3 | * | |
4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
5 | * Copyright 2006 Sony Corp. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
f0831acc | 19 | */ |
540270d8 | 20 | |
e28b0031 GL |
21 | #include <linux/interrupt.h> |
22 | #include <linux/list.h> | |
f0831acc | 23 | #include <linux/module.h> |
e28b0031 | 24 | #include <linux/ptrace.h> |
e28b0031 GL |
25 | #include <linux/wait.h> |
26 | #include <linux/mm.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/mutex.h> | |
29 | #include <linux/device.h> | |
7a214200 | 30 | #include <linux/sched.h> |
f0831acc | 31 | |
f0831acc | 32 | #include <asm/spu.h> |
540270d8 | 33 | #include <asm/spu_priv1.h> |
e28b0031 GL |
34 | #include <asm/firmware.h> |
35 | #include <asm/prom.h> | |
f0831acc | 36 | |
a91942ae | 37 | #include "interrupt.h" |
e28b0031 GL |
38 | #include "spu_priv1_mmio.h" |
39 | ||
540270d8 | 40 | static void int_mask_and(struct spu *spu, int class, u64 mask) |
f0831acc AB |
41 | { |
42 | u64 old_mask; | |
43 | ||
c9868fe0 IK |
44 | old_mask = in_be64(&spu->priv1->int_mask_RW[class]); |
45 | out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); | |
f0831acc | 46 | } |
f0831acc | 47 | |
540270d8 | 48 | static void int_mask_or(struct spu *spu, int class, u64 mask) |
f0831acc AB |
49 | { |
50 | u64 old_mask; | |
51 | ||
c9868fe0 IK |
52 | old_mask = in_be64(&spu->priv1->int_mask_RW[class]); |
53 | out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); | |
f0831acc | 54 | } |
f0831acc | 55 | |
540270d8 | 56 | static void int_mask_set(struct spu *spu, int class, u64 mask) |
f0831acc | 57 | { |
c9868fe0 | 58 | out_be64(&spu->priv1->int_mask_RW[class], mask); |
f0831acc | 59 | } |
f0831acc | 60 | |
540270d8 | 61 | static u64 int_mask_get(struct spu *spu, int class) |
f0831acc | 62 | { |
c9868fe0 | 63 | return in_be64(&spu->priv1->int_mask_RW[class]); |
f0831acc | 64 | } |
f0831acc | 65 | |
540270d8 | 66 | static void int_stat_clear(struct spu *spu, int class, u64 stat) |
f0831acc | 67 | { |
c9868fe0 | 68 | out_be64(&spu->priv1->int_stat_RW[class], stat); |
f0831acc | 69 | } |
f0831acc | 70 | |
540270d8 | 71 | static u64 int_stat_get(struct spu *spu, int class) |
f0831acc | 72 | { |
c9868fe0 | 73 | return in_be64(&spu->priv1->int_stat_RW[class]); |
f0831acc | 74 | } |
f0831acc | 75 | |
a91942ae | 76 | static void cpu_affinity_set(struct spu *spu, int cpu) |
f0831acc | 77 | { |
7a214200 LB |
78 | u64 target; |
79 | u64 route; | |
80 | ||
81 | if (nr_cpus_node(spu->node)) { | |
86c6f274 RR |
82 | const struct cpumask *spumask = cpumask_of_node(spu->node), |
83 | *cpumask = cpumask_of_node(cpu_to_node(cpu)); | |
7a214200 | 84 | |
86c6f274 | 85 | if (!cpumask_intersects(spumask, cpumask)) |
7a214200 LB |
86 | return; |
87 | } | |
88 | ||
89 | target = iic_get_target_id(cpu); | |
90 | route = target << 48 | target << 32 | target << 16; | |
c9868fe0 | 91 | out_be64(&spu->priv1->int_route_RW, route); |
f0831acc | 92 | } |
f0831acc | 93 | |
540270d8 | 94 | static u64 mfc_dar_get(struct spu *spu) |
f0831acc | 95 | { |
c9868fe0 | 96 | return in_be64(&spu->priv1->mfc_dar_RW); |
f0831acc | 97 | } |
f0831acc | 98 | |
540270d8 | 99 | static u64 mfc_dsisr_get(struct spu *spu) |
f0831acc | 100 | { |
c9868fe0 | 101 | return in_be64(&spu->priv1->mfc_dsisr_RW); |
f0831acc | 102 | } |
f0831acc | 103 | |
540270d8 | 104 | static void mfc_dsisr_set(struct spu *spu, u64 dsisr) |
f0831acc | 105 | { |
c9868fe0 | 106 | out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); |
f0831acc | 107 | } |
f0831acc | 108 | |
24f43b33 | 109 | static void mfc_sdr_setup(struct spu *spu) |
f0831acc | 110 | { |
c9868fe0 | 111 | out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1)); |
f0831acc | 112 | } |
f0831acc | 113 | |
540270d8 | 114 | static void mfc_sr1_set(struct spu *spu, u64 sr1) |
f0831acc | 115 | { |
c9868fe0 | 116 | out_be64(&spu->priv1->mfc_sr1_RW, sr1); |
f0831acc | 117 | } |
f0831acc | 118 | |
540270d8 | 119 | static u64 mfc_sr1_get(struct spu *spu) |
f0831acc | 120 | { |
c9868fe0 | 121 | return in_be64(&spu->priv1->mfc_sr1_RW); |
f0831acc | 122 | } |
f0831acc | 123 | |
540270d8 | 124 | static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id) |
f0831acc | 125 | { |
c9868fe0 | 126 | out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); |
f0831acc | 127 | } |
f0831acc | 128 | |
540270d8 | 129 | static u64 mfc_tclass_id_get(struct spu *spu) |
f0831acc | 130 | { |
c9868fe0 | 131 | return in_be64(&spu->priv1->mfc_tclass_id_RW); |
f0831acc | 132 | } |
f0831acc | 133 | |
540270d8 | 134 | static void tlb_invalidate(struct spu *spu) |
f0831acc | 135 | { |
c9868fe0 | 136 | out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); |
f0831acc | 137 | } |
f0831acc | 138 | |
540270d8 | 139 | static void resource_allocation_groupID_set(struct spu *spu, u64 id) |
f0831acc | 140 | { |
c9868fe0 | 141 | out_be64(&spu->priv1->resource_allocation_groupID_RW, id); |
f0831acc | 142 | } |
f0831acc | 143 | |
540270d8 | 144 | static u64 resource_allocation_groupID_get(struct spu *spu) |
f0831acc | 145 | { |
c9868fe0 | 146 | return in_be64(&spu->priv1->resource_allocation_groupID_RW); |
f0831acc | 147 | } |
f0831acc | 148 | |
540270d8 | 149 | static void resource_allocation_enable_set(struct spu *spu, u64 enable) |
f0831acc | 150 | { |
c9868fe0 | 151 | out_be64(&spu->priv1->resource_allocation_enable_RW, enable); |
f0831acc | 152 | } |
f0831acc | 153 | |
540270d8 | 154 | static u64 resource_allocation_enable_get(struct spu *spu) |
f0831acc | 155 | { |
c9868fe0 | 156 | return in_be64(&spu->priv1->resource_allocation_enable_RW); |
f0831acc | 157 | } |
540270d8 GL |
158 | |
159 | const struct spu_priv1_ops spu_priv1_mmio_ops = | |
160 | { | |
161 | .int_mask_and = int_mask_and, | |
162 | .int_mask_or = int_mask_or, | |
163 | .int_mask_set = int_mask_set, | |
164 | .int_mask_get = int_mask_get, | |
165 | .int_stat_clear = int_stat_clear, | |
166 | .int_stat_get = int_stat_get, | |
a91942ae | 167 | .cpu_affinity_set = cpu_affinity_set, |
540270d8 GL |
168 | .mfc_dar_get = mfc_dar_get, |
169 | .mfc_dsisr_get = mfc_dsisr_get, | |
170 | .mfc_dsisr_set = mfc_dsisr_set, | |
24f43b33 | 171 | .mfc_sdr_setup = mfc_sdr_setup, |
540270d8 GL |
172 | .mfc_sr1_set = mfc_sr1_set, |
173 | .mfc_sr1_get = mfc_sr1_get, | |
174 | .mfc_tclass_id_set = mfc_tclass_id_set, | |
175 | .mfc_tclass_id_get = mfc_tclass_id_get, | |
176 | .tlb_invalidate = tlb_invalidate, | |
177 | .resource_allocation_groupID_set = resource_allocation_groupID_set, | |
178 | .resource_allocation_groupID_get = resource_allocation_groupID_get, | |
179 | .resource_allocation_enable_set = resource_allocation_enable_set, | |
180 | .resource_allocation_enable_get = resource_allocation_enable_get, | |
181 | }; |