Commit | Line | Data |
---|---|---|
de6cc651 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
67207b96 AB |
2 | /* |
3 | * Low-level SPU handling | |
4 | * | |
5 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
6 | * | |
7 | * Author: Arnd Bergmann <arndb@de.ibm.com> | |
67207b96 AB |
8 | */ |
9 | ||
3b3d22cb | 10 | #undef DEBUG |
67207b96 AB |
11 | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/list.h> | |
8038665f | 14 | #include <linux/init.h> |
67207b96 AB |
15 | #include <linux/ptrace.h> |
16 | #include <linux/slab.h> | |
17 | #include <linux/wait.h> | |
e28b0031 GL |
18 | #include <linux/mm.h> |
19 | #include <linux/io.h> | |
14cc3e2b | 20 | #include <linux/mutex.h> |
bce94513 | 21 | #include <linux/linux_logo.h> |
f5a592f7 | 22 | #include <linux/syscore_ops.h> |
67207b96 | 23 | #include <asm/spu.h> |
540270d8 | 24 | #include <asm/spu_priv1.h> |
58bd403c | 25 | #include <asm/spu_csa.h> |
ff8a8f25 | 26 | #include <asm/xmon.h> |
158d5b5e | 27 | #include <asm/kexec.h> |
67207b96 | 28 | |
e28b0031 | 29 | const struct spu_management_ops *spu_management_ops; |
ccf17e9d JK |
30 | EXPORT_SYMBOL_GPL(spu_management_ops); |
31 | ||
540270d8 | 32 | const struct spu_priv1_ops *spu_priv1_ops; |
24140594 | 33 | EXPORT_SYMBOL_GPL(spu_priv1_ops); |
540270d8 | 34 | |
24140594 CH |
35 | struct cbe_spu_info cbe_spu_info[MAX_NUMNODES]; |
36 | EXPORT_SYMBOL_GPL(cbe_spu_info); | |
94b2a439 | 37 | |
3ce2f62b | 38 | /* |
f383d8b4 | 39 | * The spufs fault-handling code needs to call force_sig_fault to raise signals |
3ce2f62b JK |
40 | * on DMA errors. Export it here to avoid general kernel-wide access to this |
41 | * function | |
42 | */ | |
f383d8b4 | 43 | EXPORT_SYMBOL_GPL(force_sig_fault); |
3ce2f62b | 44 | |
24140594 CH |
45 | /* |
46 | * Protects cbe_spu_info and spu->number. | |
47 | */ | |
48 | static DEFINE_SPINLOCK(spu_lock); | |
49 | ||
50 | /* | |
51 | * List of all spus in the system. | |
52 | * | |
53 | * This list is iterated by callers from irq context and callers that | |
54 | * want to sleep. Thus modifications need to be done with both | |
55 | * spu_full_list_lock and spu_full_list_mutex held, while iterating | |
56 | * through it requires either of these locks. | |
57 | * | |
027dfac6 | 58 | * In addition spu_full_list_lock protects all assignments to |
24140594 CH |
59 | * spu->mm. |
60 | */ | |
61 | static LIST_HEAD(spu_full_list); | |
62 | static DEFINE_SPINLOCK(spu_full_list_lock); | |
63 | static DEFINE_MUTEX(spu_full_list_mutex); | |
540270d8 | 64 | |
94b2a439 BH |
65 | void spu_invalidate_slbs(struct spu *spu) |
66 | { | |
67 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
c92a1acb | 68 | unsigned long flags; |
94b2a439 | 69 | |
c92a1acb | 70 | spin_lock_irqsave(&spu->register_lock, flags); |
94b2a439 BH |
71 | if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK) |
72 | out_be64(&priv2->slb_invalidate_all_W, 0UL); | |
c92a1acb | 73 | spin_unlock_irqrestore(&spu->register_lock, flags); |
94b2a439 BH |
74 | } |
75 | EXPORT_SYMBOL_GPL(spu_invalidate_slbs); | |
76 | ||
77 | /* This is called by the MM core when a segment size is changed, to | |
78 | * request a flush of all the SPEs using a given mm | |
79 | */ | |
80 | void spu_flush_all_slbs(struct mm_struct *mm) | |
81 | { | |
82 | struct spu *spu; | |
83 | unsigned long flags; | |
84 | ||
24140594 | 85 | spin_lock_irqsave(&spu_full_list_lock, flags); |
94b2a439 BH |
86 | list_for_each_entry(spu, &spu_full_list, full_list) { |
87 | if (spu->mm == mm) | |
88 | spu_invalidate_slbs(spu); | |
89 | } | |
24140594 | 90 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
94b2a439 BH |
91 | } |
92 | ||
93 | /* The hack below stinks... try to do something better one of | |
94 | * these days... Does it even work properly with NR_CPUS == 1 ? | |
95 | */ | |
96 | static inline void mm_needs_global_tlbie(struct mm_struct *mm) | |
97 | { | |
98 | int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1; | |
99 | ||
100 | /* Global TLBIE broadcast required with SPEs. */ | |
56aa4129 | 101 | bitmap_fill(cpumask_bits(mm_cpumask(mm)), nr); |
94b2a439 BH |
102 | } |
103 | ||
104 | void spu_associate_mm(struct spu *spu, struct mm_struct *mm) | |
105 | { | |
106 | unsigned long flags; | |
107 | ||
24140594 | 108 | spin_lock_irqsave(&spu_full_list_lock, flags); |
94b2a439 | 109 | spu->mm = mm; |
24140594 | 110 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
94b2a439 BH |
111 | if (mm) |
112 | mm_needs_global_tlbie(mm); | |
113 | } | |
114 | EXPORT_SYMBOL_GPL(spu_associate_mm); | |
115 | ||
f6eb7d7f JK |
116 | int spu_64k_pages_available(void) |
117 | { | |
118 | return mmu_psize_defs[MMU_PAGE_64K].shift != 0; | |
119 | } | |
120 | EXPORT_SYMBOL_GPL(spu_64k_pages_available); | |
121 | ||
67207b96 AB |
122 | static void spu_restart_dma(struct spu *spu) |
123 | { | |
124 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
5473af04 | 125 | |
8837d921 | 126 | if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags)) |
5473af04 | 127 | out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); |
de102892 LB |
128 | else { |
129 | set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags); | |
130 | mb(); | |
131 | } | |
67207b96 AB |
132 | } |
133 | ||
73d16a6e | 134 | static inline void spu_load_slb(struct spu *spu, int slbe, struct copro_slb *slb) |
58bd403c JK |
135 | { |
136 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
137 | ||
fe333321 | 138 | pr_debug("%s: adding SLB[%d] 0x%016llx 0x%016llx\n", |
58bd403c JK |
139 | __func__, slbe, slb->vsid, slb->esid); |
140 | ||
141 | out_be64(&priv2->slb_index_W, slbe); | |
cc4b7c18 AB |
142 | /* set invalid before writing vsid */ |
143 | out_be64(&priv2->slb_esid_RW, 0); | |
144 | /* now it's safe to write the vsid */ | |
58bd403c | 145 | out_be64(&priv2->slb_vsid_RW, slb->vsid); |
cc4b7c18 | 146 | /* setting the new esid makes the entry valid again */ |
58bd403c JK |
147 | out_be64(&priv2->slb_esid_RW, slb->esid); |
148 | } | |
149 | ||
67207b96 AB |
150 | static int __spu_trap_data_seg(struct spu *spu, unsigned long ea) |
151 | { | |
73d16a6e IM |
152 | struct copro_slb slb; |
153 | int ret; | |
154 | ||
155 | ret = copro_calculate_slb(spu->mm, ea, &slb); | |
156 | if (ret) | |
157 | return ret; | |
67207b96 | 158 | |
4d43466d | 159 | spu_load_slb(spu, spu->slb_replace, &slb); |
8b3d6663 AB |
160 | |
161 | spu->slb_replace++; | |
67207b96 AB |
162 | if (spu->slb_replace >= 8) |
163 | spu->slb_replace = 0; | |
164 | ||
67207b96 | 165 | spu_restart_dma(spu); |
e9f8a0b6 | 166 | spu->stats.slb_flt++; |
67207b96 AB |
167 | return 0; |
168 | } | |
169 | ||
aefa5688 AK |
170 | extern int hash_page(unsigned long ea, unsigned long access, |
171 | unsigned long trap, unsigned long dsisr); //XXX | |
8b3d6663 | 172 | static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr) |
67207b96 | 173 | { |
2c911a14 LB |
174 | int ret; |
175 | ||
fe333321 | 176 | pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea); |
67207b96 | 177 | |
2c911a14 LB |
178 | /* |
179 | * Handle kernel space hash faults immediately. User hash | |
180 | * faults need to be deferred to process context. | |
181 | */ | |
182 | if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) && | |
0034d395 | 183 | (get_region_id(ea) != USER_REGION_ID)) { |
2c911a14 LB |
184 | |
185 | spin_unlock(&spu->register_lock); | |
d75e4919 JK |
186 | ret = hash_page(ea, |
187 | _PAGE_PRESENT | _PAGE_READ | _PAGE_PRIVILEGED, | |
188 | 0x300, dsisr); | |
2c911a14 LB |
189 | spin_lock(&spu->register_lock); |
190 | ||
191 | if (!ret) { | |
192 | spu_restart_dma(spu); | |
193 | return 0; | |
194 | } | |
5473af04 MN |
195 | } |
196 | ||
f3d69e05 LB |
197 | spu->class_1_dar = ea; |
198 | spu->class_1_dsisr = dsisr; | |
199 | ||
200 | spu->stop_callback(spu, 1); | |
d6ad39bc | 201 | |
f3d69e05 LB |
202 | spu->class_1_dar = 0; |
203 | spu->class_1_dsisr = 0; | |
d6ad39bc | 204 | |
67207b96 AB |
205 | return 0; |
206 | } | |
207 | ||
73d16a6e | 208 | static void __spu_kernel_slb(void *addr, struct copro_slb *slb) |
58bd403c JK |
209 | { |
210 | unsigned long ea = (unsigned long)addr; | |
211 | u64 llp; | |
212 | ||
5f53d286 | 213 | if (get_region_id(ea) == LINEAR_MAP_REGION_ID) |
58bd403c JK |
214 | llp = mmu_psize_defs[mmu_linear_psize].sllp; |
215 | else | |
216 | llp = mmu_psize_defs[mmu_virtual_psize].sllp; | |
217 | ||
218 | slb->vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) << SLB_VSID_SHIFT) | | |
219 | SLB_VSID_KERNEL | llp; | |
220 | slb->esid = (ea & ESID_MASK) | SLB_ESID_V; | |
221 | } | |
222 | ||
684bd614 JK |
223 | /** |
224 | * Given an array of @nr_slbs SLB entries, @slbs, return non-zero if the | |
225 | * address @new_addr is present. | |
226 | */ | |
73d16a6e | 227 | static inline int __slb_present(struct copro_slb *slbs, int nr_slbs, |
684bd614 JK |
228 | void *new_addr) |
229 | { | |
230 | unsigned long ea = (unsigned long)new_addr; | |
231 | int i; | |
232 | ||
233 | for (i = 0; i < nr_slbs; i++) | |
234 | if (!((slbs[i].esid ^ ea) & ESID_MASK)) | |
235 | return 1; | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
58bd403c JK |
240 | /** |
241 | * Setup the SPU kernel SLBs, in preparation for a context save/restore. We | |
242 | * need to map both the context save area, and the save/restore code. | |
684bd614 | 243 | * |
027dfac6 | 244 | * Because the lscsa and code may cross segment boundaries, we check to see |
684bd614 JK |
245 | * if mappings are required for the start and end of each range. We currently |
246 | * assume that the mappings are smaller that one segment - if not, something | |
247 | * is seriously wrong. | |
58bd403c | 248 | */ |
684bd614 JK |
249 | void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa, |
250 | void *code, int code_size) | |
58bd403c | 251 | { |
73d16a6e | 252 | struct copro_slb slbs[4]; |
684bd614 JK |
253 | int i, nr_slbs = 0; |
254 | /* start and end addresses of both mappings */ | |
255 | void *addrs[] = { | |
256 | lscsa, (void *)lscsa + sizeof(*lscsa) - 1, | |
257 | code, code + code_size - 1 | |
258 | }; | |
259 | ||
260 | /* check the set of addresses, and create a new entry in the slbs array | |
261 | * if there isn't already a SLB for that address */ | |
262 | for (i = 0; i < ARRAY_SIZE(addrs); i++) { | |
263 | if (__slb_present(slbs, nr_slbs, addrs[i])) | |
264 | continue; | |
265 | ||
266 | __spu_kernel_slb(addrs[i], &slbs[nr_slbs]); | |
267 | nr_slbs++; | |
268 | } | |
58bd403c | 269 | |
c92a1acb | 270 | spin_lock_irq(&spu->register_lock); |
684bd614 JK |
271 | /* Add the set of SLBs */ |
272 | for (i = 0; i < nr_slbs; i++) | |
273 | spu_load_slb(spu, i, &slbs[i]); | |
c92a1acb | 274 | spin_unlock_irq(&spu->register_lock); |
58bd403c JK |
275 | } |
276 | EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs); | |
277 | ||
67207b96 | 278 | static irqreturn_t |
f5a92458 | 279 | spu_irq_class_0(int irq, void *data) |
67207b96 AB |
280 | { |
281 | struct spu *spu; | |
b7f90a40 | 282 | unsigned long stat, mask; |
67207b96 AB |
283 | |
284 | spu = data; | |
b7f90a40 | 285 | |
d6ad39bc | 286 | spin_lock(&spu->register_lock); |
b7f90a40 | 287 | mask = spu_int_mask_get(spu, 0); |
d6ad39bc | 288 | stat = spu_int_stat_get(spu, 0) & mask; |
b7f90a40 | 289 | |
b7f90a40 | 290 | spu->class_0_pending |= stat; |
f3d69e05 | 291 | spu->class_0_dar = spu_mfc_dar_get(spu); |
f3d69e05 | 292 | spu->stop_callback(spu, 0); |
f3d69e05 | 293 | spu->class_0_pending = 0; |
f3d69e05 | 294 | spu->class_0_dar = 0; |
67207b96 | 295 | |
b7f90a40 | 296 | spu_int_stat_clear(spu, 0, stat); |
2c911a14 | 297 | spin_unlock(&spu->register_lock); |
b7f90a40 | 298 | |
67207b96 AB |
299 | return IRQ_HANDLED; |
300 | } | |
301 | ||
67207b96 | 302 | static irqreturn_t |
f5a92458 | 303 | spu_irq_class_1(int irq, void *data) |
67207b96 AB |
304 | { |
305 | struct spu *spu; | |
8b3d6663 | 306 | unsigned long stat, mask, dar, dsisr; |
67207b96 AB |
307 | |
308 | spu = data; | |
8b3d6663 AB |
309 | |
310 | /* atomically read & clear class1 status. */ | |
311 | spin_lock(&spu->register_lock); | |
f0831acc AB |
312 | mask = spu_int_mask_get(spu, 1); |
313 | stat = spu_int_stat_get(spu, 1) & mask; | |
314 | dar = spu_mfc_dar_get(spu); | |
315 | dsisr = spu_mfc_dsisr_get(spu); | |
8af30675 | 316 | if (stat & CLASS1_STORAGE_FAULT_INTR) |
f0831acc AB |
317 | spu_mfc_dsisr_set(spu, 0ul); |
318 | spu_int_stat_clear(spu, 1, stat); | |
67207b96 | 319 | |
e48b1b45 | 320 | pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat, |
c92a1acb AB |
321 | dar, dsisr); |
322 | ||
2c911a14 LB |
323 | if (stat & CLASS1_SEGMENT_FAULT_INTR) |
324 | __spu_trap_data_seg(spu, dar); | |
325 | ||
8af30675 | 326 | if (stat & CLASS1_STORAGE_FAULT_INTR) |
8b3d6663 | 327 | __spu_trap_data_map(spu, dar, dsisr); |
67207b96 | 328 | |
f3d69e05 LB |
329 | spu->class_1_dsisr = 0; |
330 | spu->class_1_dar = 0; | |
331 | ||
2c911a14 LB |
332 | spin_unlock(&spu->register_lock); |
333 | ||
67207b96 AB |
334 | return stat ? IRQ_HANDLED : IRQ_NONE; |
335 | } | |
336 | ||
337 | static irqreturn_t | |
f5a92458 | 338 | spu_irq_class_2(int irq, void *data) |
67207b96 AB |
339 | { |
340 | struct spu *spu; | |
341 | unsigned long stat; | |
3a843d7c | 342 | unsigned long mask; |
8af30675 JK |
343 | const int mailbox_intrs = |
344 | CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR; | |
67207b96 AB |
345 | |
346 | spu = data; | |
ba723fe2 | 347 | spin_lock(&spu->register_lock); |
f0831acc AB |
348 | stat = spu_int_stat_get(spu, 2); |
349 | mask = spu_int_mask_get(spu, 2); | |
ba723fe2 MN |
350 | /* ignore interrupts we're not waiting for */ |
351 | stat &= mask; | |
8af30675 JK |
352 | /* mailbox interrupts are level triggered. mask them now before |
353 | * acknowledging */ | |
354 | if (stat & mailbox_intrs) | |
355 | spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs)); | |
ba723fe2 MN |
356 | /* acknowledge all interrupts before the callbacks */ |
357 | spu_int_stat_clear(spu, 2, stat); | |
67207b96 | 358 | |
3a843d7c | 359 | pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask); |
67207b96 | 360 | |
8af30675 | 361 | if (stat & CLASS2_MAILBOX_INTR) |
ba723fe2 | 362 | spu->ibox_callback(spu); |
67207b96 | 363 | |
8af30675 | 364 | if (stat & CLASS2_SPU_STOP_INTR) |
f3d69e05 | 365 | spu->stop_callback(spu, 2); |
67207b96 | 366 | |
8af30675 | 367 | if (stat & CLASS2_SPU_HALT_INTR) |
f3d69e05 | 368 | spu->stop_callback(spu, 2); |
67207b96 | 369 | |
8af30675 | 370 | if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR) |
ba723fe2 | 371 | spu->mfc_callback(spu); |
67207b96 | 372 | |
8af30675 | 373 | if (stat & CLASS2_MAILBOX_THRESHOLD_INTR) |
ba723fe2 | 374 | spu->wbox_callback(spu); |
67207b96 | 375 | |
e9f8a0b6 | 376 | spu->stats.class2_intr++; |
2c911a14 LB |
377 | |
378 | spin_unlock(&spu->register_lock); | |
379 | ||
67207b96 AB |
380 | return stat ? IRQ_HANDLED : IRQ_NONE; |
381 | } | |
382 | ||
7c1ab16b | 383 | static int __init spu_request_irqs(struct spu *spu) |
67207b96 | 384 | { |
0ebfff14 | 385 | int ret = 0; |
67207b96 | 386 | |
ef24ba70 | 387 | if (spu->irqs[0]) { |
0ebfff14 BH |
388 | snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", |
389 | spu->number); | |
390 | ret = request_irq(spu->irqs[0], spu_irq_class_0, | |
a3a9f3b4 | 391 | 0, spu->irq_c0, spu); |
0ebfff14 BH |
392 | if (ret) |
393 | goto bail0; | |
394 | } | |
ef24ba70 | 395 | if (spu->irqs[1]) { |
0ebfff14 BH |
396 | snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", |
397 | spu->number); | |
398 | ret = request_irq(spu->irqs[1], spu_irq_class_1, | |
a3a9f3b4 | 399 | 0, spu->irq_c1, spu); |
0ebfff14 BH |
400 | if (ret) |
401 | goto bail1; | |
402 | } | |
ef24ba70 | 403 | if (spu->irqs[2]) { |
0ebfff14 BH |
404 | snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", |
405 | spu->number); | |
406 | ret = request_irq(spu->irqs[2], spu_irq_class_2, | |
a3a9f3b4 | 407 | 0, spu->irq_c2, spu); |
0ebfff14 BH |
408 | if (ret) |
409 | goto bail2; | |
410 | } | |
411 | return 0; | |
67207b96 | 412 | |
0ebfff14 | 413 | bail2: |
ef24ba70 | 414 | if (spu->irqs[1]) |
0ebfff14 BH |
415 | free_irq(spu->irqs[1], spu); |
416 | bail1: | |
ef24ba70 | 417 | if (spu->irqs[0]) |
0ebfff14 BH |
418 | free_irq(spu->irqs[0], spu); |
419 | bail0: | |
67207b96 AB |
420 | return ret; |
421 | } | |
422 | ||
0ebfff14 | 423 | static void spu_free_irqs(struct spu *spu) |
67207b96 | 424 | { |
ef24ba70 | 425 | if (spu->irqs[0]) |
0ebfff14 | 426 | free_irq(spu->irqs[0], spu); |
ef24ba70 | 427 | if (spu->irqs[1]) |
0ebfff14 | 428 | free_irq(spu->irqs[1], spu); |
ef24ba70 | 429 | if (spu->irqs[2]) |
0ebfff14 | 430 | free_irq(spu->irqs[2], spu); |
67207b96 AB |
431 | } |
432 | ||
486acd48 | 433 | void spu_init_channels(struct spu *spu) |
67207b96 AB |
434 | { |
435 | static const struct { | |
436 | unsigned channel; | |
437 | unsigned count; | |
438 | } zero_list[] = { | |
439 | { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, }, | |
440 | { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, }, | |
441 | }, count_list[] = { | |
442 | { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, }, | |
443 | { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, }, | |
444 | { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, }, | |
445 | }; | |
6ff730c3 | 446 | struct spu_priv2 __iomem *priv2; |
67207b96 AB |
447 | int i; |
448 | ||
449 | priv2 = spu->priv2; | |
450 | ||
451 | /* initialize all channel data to zero */ | |
452 | for (i = 0; i < ARRAY_SIZE(zero_list); i++) { | |
453 | int count; | |
454 | ||
455 | out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel); | |
456 | for (count = 0; count < zero_list[i].count; count++) | |
457 | out_be64(&priv2->spu_chnldata_RW, 0); | |
458 | } | |
459 | ||
460 | /* initialize channel counts to meaningful values */ | |
461 | for (i = 0; i < ARRAY_SIZE(count_list); i++) { | |
462 | out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel); | |
463 | out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count); | |
464 | } | |
465 | } | |
486acd48 | 466 | EXPORT_SYMBOL_GPL(spu_init_channels); |
67207b96 | 467 | |
8a25a2fd | 468 | static struct bus_type spu_subsys = { |
af5ca3f4 | 469 | .name = "spu", |
8a25a2fd | 470 | .dev_name = "spu", |
1d64093f JK |
471 | }; |
472 | ||
8a25a2fd | 473 | int spu_add_dev_attr(struct device_attribute *attr) |
e570beb6 CK |
474 | { |
475 | struct spu *spu; | |
e570beb6 | 476 | |
24140594 | 477 | mutex_lock(&spu_full_list_mutex); |
e570beb6 | 478 | list_for_each_entry(spu, &spu_full_list, full_list) |
8a25a2fd | 479 | device_create_file(&spu->dev, attr); |
24140594 | 480 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 481 | |
e570beb6 CK |
482 | return 0; |
483 | } | |
8a25a2fd | 484 | EXPORT_SYMBOL_GPL(spu_add_dev_attr); |
e570beb6 | 485 | |
6b3a3e12 | 486 | int spu_add_dev_attr_group(const struct attribute_group *attrs) |
e570beb6 CK |
487 | { |
488 | struct spu *spu; | |
1e771039 | 489 | int rc = 0; |
e570beb6 | 490 | |
24140594 | 491 | mutex_lock(&spu_full_list_mutex); |
1e771039 | 492 | list_for_each_entry(spu, &spu_full_list, full_list) { |
8a25a2fd | 493 | rc = sysfs_create_group(&spu->dev.kobj, attrs); |
1e771039 JK |
494 | |
495 | /* we're in trouble here, but try unwinding anyway */ | |
496 | if (rc) { | |
497 | printk(KERN_ERR "%s: can't create sysfs group '%s'\n", | |
498 | __func__, attrs->name); | |
499 | ||
500 | list_for_each_entry_continue_reverse(spu, | |
501 | &spu_full_list, full_list) | |
8a25a2fd | 502 | sysfs_remove_group(&spu->dev.kobj, attrs); |
1e771039 JK |
503 | break; |
504 | } | |
505 | } | |
506 | ||
24140594 | 507 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 508 | |
1e771039 | 509 | return rc; |
e570beb6 | 510 | } |
8a25a2fd | 511 | EXPORT_SYMBOL_GPL(spu_add_dev_attr_group); |
e570beb6 CK |
512 | |
513 | ||
8a25a2fd | 514 | void spu_remove_dev_attr(struct device_attribute *attr) |
e570beb6 CK |
515 | { |
516 | struct spu *spu; | |
e570beb6 | 517 | |
24140594 | 518 | mutex_lock(&spu_full_list_mutex); |
e570beb6 | 519 | list_for_each_entry(spu, &spu_full_list, full_list) |
8a25a2fd | 520 | device_remove_file(&spu->dev, attr); |
24140594 | 521 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 522 | } |
8a25a2fd | 523 | EXPORT_SYMBOL_GPL(spu_remove_dev_attr); |
e570beb6 | 524 | |
6b3a3e12 | 525 | void spu_remove_dev_attr_group(const struct attribute_group *attrs) |
e570beb6 CK |
526 | { |
527 | struct spu *spu; | |
e570beb6 | 528 | |
24140594 | 529 | mutex_lock(&spu_full_list_mutex); |
e570beb6 | 530 | list_for_each_entry(spu, &spu_full_list, full_list) |
8a25a2fd | 531 | sysfs_remove_group(&spu->dev.kobj, attrs); |
24140594 | 532 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 533 | } |
8a25a2fd | 534 | EXPORT_SYMBOL_GPL(spu_remove_dev_attr_group); |
e570beb6 | 535 | |
7c1ab16b | 536 | static int __init spu_create_dev(struct spu *spu) |
1d64093f JK |
537 | { |
538 | int ret; | |
539 | ||
8a25a2fd KS |
540 | spu->dev.id = spu->number; |
541 | spu->dev.bus = &spu_subsys; | |
542 | ret = device_register(&spu->dev); | |
1d64093f JK |
543 | if (ret) { |
544 | printk(KERN_ERR "Can't register SPU %d with sysfs\n", | |
545 | spu->number); | |
546 | return ret; | |
547 | } | |
548 | ||
8a25a2fd | 549 | sysfs_add_device_to_node(&spu->dev, spu->node); |
1d64093f JK |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
e28b0031 | 554 | static int __init create_spu(void *data) |
67207b96 AB |
555 | { |
556 | struct spu *spu; | |
557 | int ret; | |
558 | static int number; | |
94b2a439 | 559 | unsigned long flags; |
67207b96 AB |
560 | |
561 | ret = -ENOMEM; | |
ecec2177 | 562 | spu = kzalloc(sizeof (*spu), GFP_KERNEL); |
67207b96 AB |
563 | if (!spu) |
564 | goto out; | |
565 | ||
486acd48 CH |
566 | spu->alloc_state = SPU_FREE; |
567 | ||
e28b0031 | 568 | spin_lock_init(&spu->register_lock); |
24140594 | 569 | spin_lock(&spu_lock); |
e28b0031 | 570 | spu->number = number++; |
24140594 | 571 | spin_unlock(&spu_lock); |
e28b0031 GL |
572 | |
573 | ret = spu_create_spu(spu, data); | |
e5267b4b | 574 | |
67207b96 AB |
575 | if (ret) |
576 | goto out_free; | |
577 | ||
24f43b33 | 578 | spu_mfc_sdr_setup(spu); |
f0831acc | 579 | spu_mfc_sr1_set(spu, 0x33); |
67207b96 AB |
580 | ret = spu_request_irqs(spu); |
581 | if (ret) | |
e28b0031 | 582 | goto out_destroy; |
67207b96 | 583 | |
8a25a2fd | 584 | ret = spu_create_dev(spu); |
1d64093f JK |
585 | if (ret) |
586 | goto out_free_irqs; | |
587 | ||
486acd48 | 588 | mutex_lock(&cbe_spu_info[spu->node].list_mutex); |
aa6d5b20 AB |
589 | list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus); |
590 | cbe_spu_info[spu->node].n_spus++; | |
486acd48 | 591 | mutex_unlock(&cbe_spu_info[spu->node].list_mutex); |
24140594 CH |
592 | |
593 | mutex_lock(&spu_full_list_mutex); | |
594 | spin_lock_irqsave(&spu_full_list_lock, flags); | |
e570beb6 | 595 | list_add(&spu->full_list, &spu_full_list); |
24140594 CH |
596 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
597 | mutex_unlock(&spu_full_list_mutex); | |
67207b96 | 598 | |
27ec41d3 | 599 | spu->stats.util_state = SPU_UTIL_IDLE_LOADED; |
f2dec1ea | 600 | spu->stats.tstamp = ktime_get_ns(); |
fe2f896d | 601 | |
9d92af62 AB |
602 | INIT_LIST_HEAD(&spu->aff_list); |
603 | ||
67207b96 AB |
604 | goto out; |
605 | ||
1d64093f JK |
606 | out_free_irqs: |
607 | spu_free_irqs(spu); | |
e28b0031 GL |
608 | out_destroy: |
609 | spu_destroy_spu(spu); | |
67207b96 AB |
610 | out_free: |
611 | kfree(spu); | |
612 | out: | |
613 | return ret; | |
614 | } | |
615 | ||
fe2f896d CH |
616 | static const char *spu_state_names[] = { |
617 | "user", "system", "iowait", "idle" | |
618 | }; | |
619 | ||
620 | static unsigned long long spu_acct_time(struct spu *spu, | |
621 | enum spu_utilization_state state) | |
622 | { | |
623 | unsigned long long time = spu->stats.times[state]; | |
624 | ||
27ec41d3 AD |
625 | /* |
626 | * If the spu is idle or the context is stopped, utilization | |
627 | * statistics are not updated. Apply the time delta from the | |
628 | * last recorded state of the spu. | |
629 | */ | |
f2dec1ea TG |
630 | if (spu->stats.util_state == state) |
631 | time += ktime_get_ns() - spu->stats.tstamp; | |
fe2f896d | 632 | |
27ec41d3 | 633 | return time / NSEC_PER_MSEC; |
fe2f896d CH |
634 | } |
635 | ||
636 | ||
8a25a2fd KS |
637 | static ssize_t spu_stat_show(struct device *dev, |
638 | struct device_attribute *attr, char *buf) | |
fe2f896d | 639 | { |
8a25a2fd | 640 | struct spu *spu = container_of(dev, struct spu, dev); |
fe2f896d CH |
641 | |
642 | return sprintf(buf, "%s %llu %llu %llu %llu " | |
643 | "%llu %llu %llu %llu %llu %llu %llu %llu\n", | |
27ec41d3 | 644 | spu_state_names[spu->stats.util_state], |
fe2f896d CH |
645 | spu_acct_time(spu, SPU_UTIL_USER), |
646 | spu_acct_time(spu, SPU_UTIL_SYSTEM), | |
647 | spu_acct_time(spu, SPU_UTIL_IOWAIT), | |
27ec41d3 | 648 | spu_acct_time(spu, SPU_UTIL_IDLE_LOADED), |
fe2f896d CH |
649 | spu->stats.vol_ctx_switch, |
650 | spu->stats.invol_ctx_switch, | |
651 | spu->stats.slb_flt, | |
652 | spu->stats.hash_flt, | |
653 | spu->stats.min_flt, | |
654 | spu->stats.maj_flt, | |
655 | spu->stats.class2_intr, | |
656 | spu->stats.libassist); | |
657 | } | |
658 | ||
96cf3f66 | 659 | static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL); |
fe2f896d | 660 | |
da665885 | 661 | #ifdef CONFIG_KEXEC_CORE |
158d5b5e AB |
662 | |
663 | struct crash_spu_info { | |
664 | struct spu *spu; | |
665 | u32 saved_spu_runcntl_RW; | |
666 | u32 saved_spu_status_R; | |
667 | u32 saved_spu_npc_RW; | |
668 | u64 saved_mfc_sr1_RW; | |
669 | u64 saved_mfc_dar; | |
670 | u64 saved_mfc_dsisr; | |
671 | }; | |
672 | ||
673 | #define CRASH_NUM_SPUS 16 /* Enough for current hardware */ | |
674 | static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS]; | |
675 | ||
676 | static void crash_kexec_stop_spus(void) | |
677 | { | |
678 | struct spu *spu; | |
679 | int i; | |
680 | u64 tmp; | |
681 | ||
682 | for (i = 0; i < CRASH_NUM_SPUS; i++) { | |
683 | if (!crash_spu_info[i].spu) | |
684 | continue; | |
685 | ||
686 | spu = crash_spu_info[i].spu; | |
687 | ||
688 | crash_spu_info[i].saved_spu_runcntl_RW = | |
689 | in_be32(&spu->problem->spu_runcntl_RW); | |
690 | crash_spu_info[i].saved_spu_status_R = | |
691 | in_be32(&spu->problem->spu_status_R); | |
692 | crash_spu_info[i].saved_spu_npc_RW = | |
693 | in_be32(&spu->problem->spu_npc_RW); | |
694 | ||
695 | crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu); | |
696 | crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu); | |
697 | tmp = spu_mfc_sr1_get(spu); | |
698 | crash_spu_info[i].saved_mfc_sr1_RW = tmp; | |
699 | ||
700 | tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; | |
701 | spu_mfc_sr1_set(spu, tmp); | |
702 | ||
703 | __delay(200); | |
704 | } | |
705 | } | |
706 | ||
7c1ab16b | 707 | static void __init crash_register_spus(struct list_head *list) |
158d5b5e AB |
708 | { |
709 | struct spu *spu; | |
710 | int ret; | |
711 | ||
712 | list_for_each_entry(spu, list, full_list) { | |
713 | if (WARN_ON(spu->number >= CRASH_NUM_SPUS)) | |
714 | continue; | |
715 | ||
716 | crash_spu_info[spu->number].spu = spu; | |
717 | } | |
718 | ||
719 | ret = crash_shutdown_register(&crash_kexec_stop_spus); | |
720 | if (ret) | |
721 | printk(KERN_ERR "Could not register SPU crash handler"); | |
722 | } | |
723 | ||
724 | #else | |
725 | static inline void crash_register_spus(struct list_head *list) | |
726 | { | |
727 | } | |
728 | #endif | |
729 | ||
f5a592f7 RW |
730 | static void spu_shutdown(void) |
731 | { | |
732 | struct spu *spu; | |
733 | ||
734 | mutex_lock(&spu_full_list_mutex); | |
735 | list_for_each_entry(spu, &spu_full_list, full_list) { | |
736 | spu_free_irqs(spu); | |
737 | spu_destroy_spu(spu); | |
738 | } | |
739 | mutex_unlock(&spu_full_list_mutex); | |
740 | } | |
741 | ||
742 | static struct syscore_ops spu_syscore_ops = { | |
743 | .shutdown = spu_shutdown, | |
744 | }; | |
745 | ||
67207b96 AB |
746 | static int __init init_spu_base(void) |
747 | { | |
befdc746 | 748 | int i, ret = 0; |
67207b96 | 749 | |
aa6d5b20 | 750 | for (i = 0; i < MAX_NUMNODES; i++) { |
486acd48 | 751 | mutex_init(&cbe_spu_info[i].list_mutex); |
aa6d5b20 | 752 | INIT_LIST_HEAD(&cbe_spu_info[i].spus); |
aa6d5b20 | 753 | } |
ccf17e9d | 754 | |
da06aa08 | 755 | if (!spu_management_ops) |
befdc746 | 756 | goto out; |
da06aa08 | 757 | |
8a25a2fd KS |
758 | /* create system subsystem for spus */ |
759 | ret = subsys_system_register(&spu_subsys, NULL); | |
1d64093f | 760 | if (ret) |
befdc746 | 761 | goto out; |
1d64093f | 762 | |
e28b0031 GL |
763 | ret = spu_enumerate_spus(create_spu); |
764 | ||
bce94513 | 765 | if (ret < 0) { |
e28b0031 | 766 | printk(KERN_WARNING "%s: Error initializing spus\n", |
e48b1b45 | 767 | __func__); |
8a25a2fd | 768 | goto out_unregister_subsys; |
67207b96 | 769 | } |
ff8a8f25 | 770 | |
ae52bb23 | 771 | if (ret > 0) |
bce94513 | 772 | fb_append_extra_logo(&logo_spe_clut224, ret); |
bce94513 | 773 | |
24140594 | 774 | mutex_lock(&spu_full_list_mutex); |
ff8a8f25 | 775 | xmon_register_spus(&spu_full_list); |
8d2655e6 | 776 | crash_register_spus(&spu_full_list); |
24140594 | 777 | mutex_unlock(&spu_full_list_mutex); |
8a25a2fd | 778 | spu_add_dev_attr(&dev_attr_stat); |
f5a592f7 | 779 | register_syscore_ops(&spu_syscore_ops); |
fe2f896d | 780 | |
f5996449 | 781 | spu_init_affinity(); |
3ad216ca | 782 | |
befdc746 CH |
783 | return 0; |
784 | ||
8a25a2fd KS |
785 | out_unregister_subsys: |
786 | bus_unregister(&spu_subsys); | |
befdc746 | 787 | out: |
67207b96 AB |
788 | return ret; |
789 | } | |
8038665f | 790 | device_initcall(init_spu_base); |