[linux-2.6-block.git] / arch / powerpc / platforms / cell / pmu.c

/*
 * Cell Broadband Engine Performance Monitor
 *
 * (C) Copyright IBM Corporation 2001,2006
 *
 * Author:
 *    David Erb (djerb@us.ibm.com)
 *    Kevin Corry (kevcorry@us.ibm.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/export.h>
#include <asm/io.h>
#include <asm/irq_regs.h>
#include <asm/machdep.h>
#include <asm/pmc.h>
#include <asm/reg.h>
#include <asm/spu.h>
#include <asm/cell-regs.h>

#include "interrupt.h"

/*
 * When writing to write-only mmio addresses, save a shadow copy. All of the
 * registers are 32-bit, but stored in the upper-half of a 64-bit field in
 * pmd_regs.
 */

#define WRITE_WO_MMIO(reg, x)					\
	do {							\
		u32 _x = (x);					\
		struct cbe_pmd_regs __iomem *pmd_regs;		\
		struct cbe_pmd_shadow_regs *shadow_regs;	\
		pmd_regs = cbe_get_cpu_pmd_regs(cpu);		\
		shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);	\
		out_be64(&(pmd_regs->reg), (((u64)_x) << 32));	\
		shadow_regs->reg = _x;				\
	} while (0)

#define READ_SHADOW_REG(val, reg)				\
	do {							\
		struct cbe_pmd_shadow_regs *shadow_regs;	\
		shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);	\
		(val) = shadow_regs->reg;			\
	} while (0)

#define READ_MMIO_UPPER32(val, reg)				\
	do {							\
		struct cbe_pmd_regs __iomem *pmd_regs;		\
		pmd_regs = cbe_get_cpu_pmd_regs(cpu);		\
		(val) = (u32)(in_be64(&pmd_regs->reg) >> 32);	\
	} while (0)

/*
 * Physical counter registers.
 * Each physical counter can act as one 32-bit counter or two 16-bit counters.
 */

u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
{
	u32 val_in_latch, val = 0;

	if (phys_ctr < NR_PHYS_CTRS) {
		READ_SHADOW_REG(val_in_latch, counter_value_in_latch);

		/* Read the latch or the actual counter, whichever is newer. */
		if (val_in_latch & (1 << phys_ctr)) {
			READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
		} else {
			READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
		}
	}

	return val;
}
EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);

void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
{
	struct cbe_pmd_shadow_regs *shadow_regs;
	u32 pm_ctrl;

	if (phys_ctr < NR_PHYS_CTRS) {
		/* Writing to a counter only writes to a hardware latch.
		 * The new value is not propagated to the actual counter
		 * until the performance monitor is enabled.
		 */
		WRITE_WO_MMIO(pm_ctr[phys_ctr], val);

		pm_ctrl = cbe_read_pm(cpu, pm_control);
		if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
			/* The counters are already active, so we need to
			 * rewrite the pm_control register to "re-enable"
			 * the PMU.
			 */
			cbe_write_pm(cpu, pm_control, pm_ctrl);
		} else {
			shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
			shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
		}
	}
}
EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);

/*
 * "Logical" counter registers.
 * These will read/write 16-bits or 32-bits depending on the
 * current size of the counter. Counters 4 - 7 are always 16-bit.
 */

u32 cbe_read_ctr(u32 cpu, u32 ctr)
{
	u32 val;
	u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);

	val = cbe_read_phys_ctr(cpu, phys_ctr);

	if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
		val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);

	return val;
}
EXPORT_SYMBOL_GPL(cbe_read_ctr);

void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
{
	u32 phys_ctr;
	u32 phys_val;

	phys_ctr = ctr & (NR_PHYS_CTRS - 1);

	if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
		phys_val = cbe_read_phys_ctr(cpu, phys_ctr);

		if (ctr < NR_PHYS_CTRS)
			val = (val << 16) | (phys_val & 0xffff);
		else
			val = (val & 0xffff) | (phys_val & 0xffff0000);
	}

	cbe_write_phys_ctr(cpu, phys_ctr, val);
}
EXPORT_SYMBOL_GPL(cbe_write_ctr);

/*
 * Counter-control registers.
 * Each "logical" counter has a corresponding control register.
 */

u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
{
	u32 pm07_control = 0;

	if (ctr < NR_CTRS)
		READ_SHADOW_REG(pm07_control, pm07_control[ctr]);

	return pm07_control;
}
EXPORT_SYMBOL_GPL(cbe_read_pm07_control);

void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
{
	if (ctr < NR_CTRS)
		WRITE_WO_MMIO(pm07_control[ctr], val);
}
EXPORT_SYMBOL_GPL(cbe_write_pm07_control);

/*
 * Other PMU control registers. Most of these are write-only.
 */

u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
{
	u32 val = 0;

	switch (reg) {
	case group_control:
		READ_SHADOW_REG(val, group_control);
		break;

	case debug_bus_control:
		READ_SHADOW_REG(val, debug_bus_control);
		break;

	case trace_address:
		READ_MMIO_UPPER32(val, trace_address);
		break;

	case ext_tr_timer:
		READ_SHADOW_REG(val, ext_tr_timer);
		break;

	case pm_status:
		READ_MMIO_UPPER32(val, pm_status);
		break;

	case pm_control:
		READ_SHADOW_REG(val, pm_control);
		break;

	case pm_interval:
		READ_MMIO_UPPER32(val, pm_interval);
		break;

	case pm_start_stop:
		READ_SHADOW_REG(val, pm_start_stop);
		break;
	}

	return val;
}
EXPORT_SYMBOL_GPL(cbe_read_pm);

void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
{
	switch (reg) {
	case group_control:
		WRITE_WO_MMIO(group_control, val);
		break;

	case debug_bus_control:
		WRITE_WO_MMIO(debug_bus_control, val);
		break;

	case trace_address:
		WRITE_WO_MMIO(trace_address, val);
		break;

	case ext_tr_timer:
		WRITE_WO_MMIO(ext_tr_timer, val);
		break;

	case pm_status:
		WRITE_WO_MMIO(pm_status, val);
		break;

	case pm_control:
		WRITE_WO_MMIO(pm_control, val);
		break;

	case pm_interval:
		WRITE_WO_MMIO(pm_interval, val);
		break;

	case pm_start_stop:
		WRITE_WO_MMIO(pm_start_stop, val);
		break;
	}
}
EXPORT_SYMBOL_GPL(cbe_write_pm);

/*
 * Get/set the size of a physical counter to either 16 or 32 bits.
 */

u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
{
	u32 pm_ctrl, size = 0;

	if (phys_ctr < NR_PHYS_CTRS) {
		pm_ctrl = cbe_read_pm(cpu, pm_control);
		size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
	}

	return size;
}
EXPORT_SYMBOL_GPL(cbe_get_ctr_size);

void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
{
	u32 pm_ctrl;

	if (phys_ctr < NR_PHYS_CTRS) {
		pm_ctrl = cbe_read_pm(cpu, pm_control);
		switch (ctr_size) {
		case 16:
			pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
			break;

		case 32:
			pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
			break;
		}
		cbe_write_pm(cpu, pm_control, pm_ctrl);
	}
}
EXPORT_SYMBOL_GPL(cbe_set_ctr_size);

/*
 * Enable/disable the entire performance monitoring unit.
 * When we enable the PMU, all pending writes to counters get committed.
 */

void cbe_enable_pm(u32 cpu)
{
	struct cbe_pmd_shadow_regs *shadow_regs;
	u32 pm_ctrl;

	shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
	shadow_regs->counter_value_in_latch = 0;

	pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
	cbe_write_pm(cpu, pm_control, pm_ctrl);
}
EXPORT_SYMBOL_GPL(cbe_enable_pm);

void cbe_disable_pm(u32 cpu)
{
	u32 pm_ctrl;
	pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
	cbe_write_pm(cpu, pm_control, pm_ctrl);
}
EXPORT_SYMBOL_GPL(cbe_disable_pm);

/*
 * Reading from the trace_buffer.
 * The trace buffer is two 64-bit registers. Reading from
 * the second half automatically increments the trace_address.
 */

void cbe_read_trace_buffer(u32 cpu, u64 *buf)
{
	struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);

	*buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
	*buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
}
EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);

/*
 * Enabling/disabling interrupts for the entire performance monitoring unit.
 */

u32 cbe_get_and_clear_pm_interrupts(u32 cpu)
{
	/* Reading pm_status clears the interrupt bits. */
	return cbe_read_pm(cpu, pm_status);
}
EXPORT_SYMBOL_GPL(cbe_get_and_clear_pm_interrupts);

void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
{
	/* Set which node and thread will handle the next interrupt. */
	iic_set_interrupt_routing(cpu, thread, 0);

	/* Enable the interrupt bits in the pm_status register. */
	if (mask)
		cbe_write_pm(cpu, pm_status, mask);
}
EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);

void cbe_disable_pm_interrupts(u32 cpu)
{
	cbe_get_and_clear_pm_interrupts(cpu);
	cbe_write_pm(cpu, pm_status, 0);
}
EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);

static irqreturn_t cbe_pm_irq(int irq, void *dev_id)
{
	perf_irq(get_irq_regs());
	return IRQ_HANDLED;
}

static int __init cbe_init_pm_irq(void)
{
	unsigned int irq;
	int rc, node;

	for_each_node(node) {
		irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
					       (node << IIC_IRQ_NODE_SHIFT));
		if (irq == NO_IRQ) {
			printk("ERROR: Unable to allocate irq for node %d\n",
			       node);
			return -EINVAL;
		}

		rc = request_irq(irq, cbe_pm_irq,
				 0, "cbe-pmu-0", NULL);
		if (rc) {
			printk("ERROR: Request for irq on node %d failed\n",
			       node);
			return rc;
		}
	}

	return 0;
}
machine_arch_initcall(cell, cbe_init_pm_irq);

void cbe_sync_irq(int node)
{
	unsigned int irq;

	irq = irq_find_mapping(NULL,
			       IIC_IRQ_IOEX_PMI
			       | (node << IIC_IRQ_NODE_SHIFT));

	if (irq == NO_IRQ) {
		printk(KERN_WARNING "ERROR, unable to get existing irq %d " \
		"for node %d\n", irq, node);
		return;
	}

	synchronize_irq(irq);
}
EXPORT_SYMBOL_GPL(cbe_sync_irq);
Commit	Line	Data
d8bf96e0 KC	1	/*
	2	* Cell Broadband Engine Performance Monitor
	3	*
	4	* (C) Copyright IBM Corporation 2001,2006
	5	*
	6	* Author:
	7	* David Erb (djerb@us.ibm.com)
	8	* Kevin Corry (kevcorry@us.ibm.com)
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2, or (at your option)
	13	* any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24
0443bbd3	25	#include <linux/interrupt.h>
d8bf96e0	26	#include <linux/types.h>
66b15db6	27	#include <linux/export.h>
d8bf96e0	28	#include <asm/io.h>
18f2190d	29	#include <asm/irq_regs.h>
d8bf96e0	30	#include <asm/machdep.h>
0443bbd3	31	#include <asm/pmc.h>
d8bf96e0 KC	32	#include <asm/reg.h>
d8bf96e0 KC	33	#include <asm/spu.h>
eef686a0	34	#include <asm/cell-regs.h>
d8bf96e0	35
d8bf96e0	36	#include "interrupt.h"
d8bf96e0 KC	37
	38	/*
	39	* When writing to write-only mmio addresses, save a shadow copy. All of the
	40	* registers are 32-bit, but stored in the upper-half of a 64-bit field in
	41	* pmd_regs.
	42	*/
	43
	44	#define WRITE_WO_MMIO(reg, x) \
	45	do { \
	46	u32 _x = (x); \
	47	struct cbe_pmd_regs __iomem *pmd_regs; \
	48	struct cbe_pmd_shadow_regs *shadow_regs; \
	49	pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
	50	shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
	51	out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
	52	shadow_regs->reg = _x; \
	53	} while (0)
	54
	55	#define READ_SHADOW_REG(val, reg) \
	56	do { \
	57	struct cbe_pmd_shadow_regs *shadow_regs; \
	58	shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
	59	(val) = shadow_regs->reg; \
	60	} while (0)
	61
	62	#define READ_MMIO_UPPER32(val, reg) \
	63	do { \
	64	struct cbe_pmd_regs __iomem *pmd_regs; \
	65	pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
	66	(val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
	67	} while (0)
	68
	69	/*
	70	* Physical counter registers.
	71	* Each physical counter can act as one 32-bit counter or two 16-bit counters.
	72	*/
	73
	74	u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
	75	{
	76	u32 val_in_latch, val = 0;
	77
	78	if (phys_ctr < NR_PHYS_CTRS) {
	79	READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
	80
	81	/* Read the latch or the actual counter, whichever is newer. */
	82	if (val_in_latch & (1 << phys_ctr)) {
	83	READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
	84	} else {
	85	READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
	86	}
	87	}
	88
	89	return val;
	90	}
5231800c	91	EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);
d8bf96e0 KC	92
	93	void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
	94	{
	95	struct cbe_pmd_shadow_regs *shadow_regs;
	96	u32 pm_ctrl;
	97
	98	if (phys_ctr < NR_PHYS_CTRS) {
	99	/* Writing to a counter only writes to a hardware latch.
	100	* The new value is not propagated to the actual counter
	101	* until the performance monitor is enabled.
	102	*/
	103	WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
	104
	105	pm_ctrl = cbe_read_pm(cpu, pm_control);
	106	if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
	107	/* The counters are already active, so we need to
	108	* rewrite the pm_control register to "re-enable"
	109	* the PMU.
	110	*/
	111	cbe_write_pm(cpu, pm_control, pm_ctrl);
	112	} else {
	113	shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
	114	shadow_regs->counter_value_in_latch \|= (1 << phys_ctr);
	115	}
	116	}
	117	}
5231800c	118	EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);
d8bf96e0 KC	119
	120	/*
	121	* "Logical" counter registers.
	122	* These will read/write 16-bits or 32-bits depending on the
	123	* current size of the counter. Counters 4 - 7 are always 16-bit.
	124	*/
	125
	126	u32 cbe_read_ctr(u32 cpu, u32 ctr)
	127	{
	128	u32 val;
	129	u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
	130
	131	val = cbe_read_phys_ctr(cpu, phys_ctr);
	132
	133	if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
	134	val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
	135
	136	return val;
	137	}
5231800c	138	EXPORT_SYMBOL_GPL(cbe_read_ctr);
d8bf96e0 KC	139
	140	void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
	141	{
	142	u32 phys_ctr;
	143	u32 phys_val;
	144
	145	phys_ctr = ctr & (NR_PHYS_CTRS - 1);
	146
	147	if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
	148	phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
	149
	150	if (ctr < NR_PHYS_CTRS)
	151	val = (val << 16) \| (phys_val & 0xffff);
	152	else
	153	val = (val & 0xffff) \| (phys_val & 0xffff0000);
	154	}
	155
	156	cbe_write_phys_ctr(cpu, phys_ctr, val);
	157	}
5231800c	158	EXPORT_SYMBOL_GPL(cbe_write_ctr);
d8bf96e0 KC	159
	160	/*
	161	* Counter-control registers.
	162	* Each "logical" counter has a corresponding control register.
	163	*/
	164
	165	u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
	166	{
	167	u32 pm07_control = 0;
	168
	169	if (ctr < NR_CTRS)
	170	READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
	171
	172	return pm07_control;
	173	}
5231800c	174	EXPORT_SYMBOL_GPL(cbe_read_pm07_control);
d8bf96e0 KC	175
	176	void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
	177	{
	178	if (ctr < NR_CTRS)
	179	WRITE_WO_MMIO(pm07_control[ctr], val);
	180	}
5231800c	181	EXPORT_SYMBOL_GPL(cbe_write_pm07_control);
d8bf96e0 KC	182
	183	/*
	184	* Other PMU control registers. Most of these are write-only.
	185	*/
	186
	187	u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
	188	{
	189	u32 val = 0;
	190
	191	switch (reg) {
	192	case group_control:
	193	READ_SHADOW_REG(val, group_control);
	194	break;
	195
	196	case debug_bus_control:
	197	READ_SHADOW_REG(val, debug_bus_control);
	198	break;
	199
	200	case trace_address:
	201	READ_MMIO_UPPER32(val, trace_address);
	202	break;
	203
	204	case ext_tr_timer:
	205	READ_SHADOW_REG(val, ext_tr_timer);
	206	break;
	207
	208	case pm_status:
	209	READ_MMIO_UPPER32(val, pm_status);
	210	break;
	211
	212	case pm_control:
	213	READ_SHADOW_REG(val, pm_control);
	214	break;
	215
	216	case pm_interval:
29641ce1	217	READ_MMIO_UPPER32(val, pm_interval);
d8bf96e0 KC	218	break;
	219
	220	case pm_start_stop:
	221	READ_SHADOW_REG(val, pm_start_stop);
	222	break;
	223	}
	224
	225	return val;
	226	}
5231800c	227	EXPORT_SYMBOL_GPL(cbe_read_pm);
d8bf96e0 KC	228
	229	void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
	230	{
	231	switch (reg) {
	232	case group_control:
	233	WRITE_WO_MMIO(group_control, val);
	234	break;
	235
	236	case debug_bus_control:
	237	WRITE_WO_MMIO(debug_bus_control, val);
	238	break;
	239
	240	case trace_address:
	241	WRITE_WO_MMIO(trace_address, val);
	242	break;
	243
	244	case ext_tr_timer:
	245	WRITE_WO_MMIO(ext_tr_timer, val);
	246	break;
	247
	248	case pm_status:
	249	WRITE_WO_MMIO(pm_status, val);
	250	break;
	251
	252	case pm_control:
	253	WRITE_WO_MMIO(pm_control, val);
	254	break;
	255
	256	case pm_interval:
	257	WRITE_WO_MMIO(pm_interval, val);
	258	break;
	259
	260	case pm_start_stop:
	261	WRITE_WO_MMIO(pm_start_stop, val);
	262	break;
	263	}
	264	}
5231800c	265	EXPORT_SYMBOL_GPL(cbe_write_pm);
d8bf96e0 KC	266
	267	/*
	268	* Get/set the size of a physical counter to either 16 or 32 bits.
	269	*/
	270
	271	u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
	272	{
	273	u32 pm_ctrl, size = 0;
	274
	275	if (phys_ctr < NR_PHYS_CTRS) {
	276	pm_ctrl = cbe_read_pm(cpu, pm_control);
	277	size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
	278	}
	279
	280	return size;
	281	}
5231800c	282	EXPORT_SYMBOL_GPL(cbe_get_ctr_size);
d8bf96e0 KC	283
	284	void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
	285	{
	286	u32 pm_ctrl;
	287
	288	if (phys_ctr < NR_PHYS_CTRS) {
	289	pm_ctrl = cbe_read_pm(cpu, pm_control);
	290	switch (ctr_size) {
	291	case 16:
	292	pm_ctrl \|= CBE_PM_16BIT_CTR(phys_ctr);
	293	break;
	294
	295	case 32:
	296	pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
	297	break;
	298	}
	299	cbe_write_pm(cpu, pm_control, pm_ctrl);
	300	}
	301	}
5231800c	302	EXPORT_SYMBOL_GPL(cbe_set_ctr_size);
d8bf96e0 KC	303
	304	/*
	305	* Enable/disable the entire performance monitoring unit.
	306	* When we enable the PMU, all pending writes to counters get committed.
	307	*/
	308
	309	void cbe_enable_pm(u32 cpu)
	310	{
	311	struct cbe_pmd_shadow_regs *shadow_regs;
	312	u32 pm_ctrl;
	313
	314	shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
	315	shadow_regs->counter_value_in_latch = 0;
	316
	317	pm_ctrl = cbe_read_pm(cpu, pm_control) \| CBE_PM_ENABLE_PERF_MON;
	318	cbe_write_pm(cpu, pm_control, pm_ctrl);
	319	}
5231800c	320	EXPORT_SYMBOL_GPL(cbe_enable_pm);
d8bf96e0 KC	321
	322	void cbe_disable_pm(u32 cpu)
	323	{
	324	u32 pm_ctrl;
	325	pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
	326	cbe_write_pm(cpu, pm_control, pm_ctrl);
	327	}
5231800c	328	EXPORT_SYMBOL_GPL(cbe_disable_pm);
d8bf96e0 KC	329
	330	/*
	331	* Reading from the trace_buffer.
	332	* The trace buffer is two 64-bit registers. Reading from
	333	* the second half automatically increments the trace_address.
	334	*/
	335
	336	void cbe_read_trace_buffer(u32 cpu, u64 *buf)
	337	{
	338	struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
	339
	340	*buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
	341	*buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
	342	}
5231800c	343	EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
d8bf96e0	344
0443bbd3 KC	345	/*
	346	* Enabling/disabling interrupts for the entire performance monitoring unit.
	347	*/
	348
bcb63e25	349	u32 cbe_get_and_clear_pm_interrupts(u32 cpu)
0443bbd3 KC	350	{
0443bbd3 KC	351	/* Reading pm_status clears the interrupt bits. */
bcb63e25	352	return cbe_read_pm(cpu, pm_status);
0443bbd3	353	}
bcb63e25	354	EXPORT_SYMBOL_GPL(cbe_get_and_clear_pm_interrupts);
0443bbd3 KC	355
	356	void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
	357	{
	358	/* Set which node and thread will handle the next interrupt. */
	359	iic_set_interrupt_routing(cpu, thread, 0);
	360
	361	/* Enable the interrupt bits in the pm_status register. */
	362	if (mask)
	363	cbe_write_pm(cpu, pm_status, mask);
	364	}
	365	EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
	366
	367	void cbe_disable_pm_interrupts(u32 cpu)
	368	{
bcb63e25	369	cbe_get_and_clear_pm_interrupts(cpu);
0443bbd3 KC	370	cbe_write_pm(cpu, pm_status, 0);
	371	}
	372	EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
	373
18f2190d	374	static irqreturn_t cbe_pm_irq(int irq, void *dev_id)
0443bbd3	375	{
18f2190d	376	perf_irq(get_irq_regs());
0443bbd3 KC	377	return IRQ_HANDLED;
	378	}
	379
a081e126	380	static int __init cbe_init_pm_irq(void)
0443bbd3 KC	381	{
	382	unsigned int irq;
	383	int rc, node;
	384
	385	for_each_node(node) {
	386	irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI \|
	387	(node << IIC_IRQ_NODE_SHIFT));
	388	if (irq == NO_IRQ) {
	389	printk("ERROR: Unable to allocate irq for node %d\n",
	390	node);
	391	return -EINVAL;
	392	}
	393
	394	rc = request_irq(irq, cbe_pm_irq,
a3a9f3b4	395	0, "cbe-pmu-0", NULL);
0443bbd3 KC	396	if (rc) {
	397	printk("ERROR: Request for irq on node %d failed\n",
	398	node);
	399	return rc;
	400	}
	401	}
	402
	403	return 0;
	404	}
e25c47ff	405	machine_arch_initcall(cell, cbe_init_pm_irq);
0443bbd3	406
18f2190d MJ	407	void cbe_sync_irq(int node)
	408	{
	409	unsigned int irq;
	410
	411	irq = irq_find_mapping(NULL,
	412	IIC_IRQ_IOEX_PMI
	413	\| (node << IIC_IRQ_NODE_SHIFT));
	414
	415	if (irq == NO_IRQ) {
	416	printk(KERN_WARNING "ERROR, unable to get existing irq %d " \
	417	"for node %d\n", irq, node);
	418	return;
	419	}
	420
	421	synchronize_irq(irq);
	422	}
	423	EXPORT_SYMBOL_GPL(cbe_sync_irq);
	424