Commit | Line | Data |
---|---|---|
cebf589c | 1 | /* |
f3f66f59 | 2 | * Cell Internal Interrupt Controller |
cebf589c | 3 | * |
0ebfff14 BH |
4 | * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
5 | * IBM, Corp. | |
6 | * | |
cebf589c AB |
7 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 |
8 | * | |
9 | * Author: Arnd Bergmann <arndb@de.ibm.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
2e194583 BH |
24 | * |
25 | * TODO: | |
26 | * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers | |
27 | * vs node numbers in the setup code | |
28 | * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from | |
29 | * a non-active node to the active node) | |
cebf589c AB |
30 | */ |
31 | ||
cebf589c AB |
32 | #include <linux/interrupt.h> |
33 | #include <linux/irq.h> | |
4b16f8e2 | 34 | #include <linux/export.h> |
cebf589c AB |
35 | #include <linux/percpu.h> |
36 | #include <linux/types.h> | |
0ebfff14 | 37 | #include <linux/ioport.h> |
5711fe90 | 38 | #include <linux/kernel_stat.h> |
cebf589c AB |
39 | |
40 | #include <asm/io.h> | |
41 | #include <asm/pgtable.h> | |
42 | #include <asm/prom.h> | |
43 | #include <asm/ptrace.h> | |
0ebfff14 | 44 | #include <asm/machdep.h> |
eef686a0 | 45 | #include <asm/cell-regs.h> |
cebf589c | 46 | |
f3f66f59 | 47 | #include "interrupt.h" |
cebf589c AB |
48 | |
49 | struct iic { | |
acf7d768 | 50 | struct cbe_iic_thread_regs __iomem *regs; |
2fb9d206 | 51 | u8 target_id; |
b9e5b4e6 BH |
52 | u8 eoi_stack[16]; |
53 | int eoi_ptr; | |
2e194583 | 54 | struct device_node *node; |
cebf589c AB |
55 | }; |
56 | ||
6b7487fc | 57 | static DEFINE_PER_CPU(struct iic, cpu_iic); |
0ebfff14 | 58 | #define IIC_NODE_COUNT 2 |
bae1d8f1 | 59 | static struct irq_domain *iic_host; |
0ebfff14 BH |
60 | |
61 | /* Convert between "pending" bits and hw irq number */ | |
62 | static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits) | |
63 | { | |
64 | unsigned char unit = bits.source & 0xf; | |
2e194583 BH |
65 | unsigned char node = bits.source >> 4; |
66 | unsigned char class = bits.class & 3; | |
0ebfff14 | 67 | |
2e194583 | 68 | /* Decode IPIs */ |
0ebfff14 | 69 | if (bits.flags & CBE_IIC_IRQ_IPI) |
2e194583 | 70 | return IIC_IRQ_TYPE_IPI | (bits.prio >> 4); |
0ebfff14 | 71 | else |
2e194583 | 72 | return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit; |
0ebfff14 | 73 | } |
cebf589c | 74 | |
d1ae63d4 | 75 | static void iic_mask(struct irq_data *d) |
cebf589c | 76 | { |
cebf589c AB |
77 | } |
78 | ||
d1ae63d4 | 79 | static void iic_unmask(struct irq_data *d) |
cebf589c AB |
80 | { |
81 | } | |
82 | ||
d1ae63d4 | 83 | static void iic_eoi(struct irq_data *d) |
cebf589c | 84 | { |
69111bac | 85 | struct iic *iic = this_cpu_ptr(&cpu_iic); |
b9e5b4e6 BH |
86 | out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); |
87 | BUG_ON(iic->eoi_ptr < 0); | |
cebf589c AB |
88 | } |
89 | ||
b9e5b4e6 | 90 | static struct irq_chip iic_chip = { |
fc380c0c | 91 | .name = "CELL-IIC", |
d1ae63d4 LB |
92 | .irq_mask = iic_mask, |
93 | .irq_unmask = iic_unmask, | |
94 | .irq_eoi = iic_eoi, | |
cebf589c AB |
95 | }; |
96 | ||
2e194583 | 97 | |
d1ae63d4 | 98 | static void iic_ioexc_eoi(struct irq_data *d) |
2e194583 BH |
99 | { |
100 | } | |
101 | ||
bd0b9ac4 | 102 | static void iic_ioexc_cascade(struct irq_desc *desc) |
2e194583 | 103 | { |
ec775d0e | 104 | struct irq_chip *chip = irq_desc_get_chip(desc); |
d1ae63d4 | 105 | struct cbe_iic_regs __iomem *node_iic = |
ec775d0e | 106 | (void __iomem *)irq_desc_get_handler_data(desc); |
391de7f9 | 107 | unsigned int irq = irq_desc_get_irq(desc); |
2e194583 BH |
108 | unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; |
109 | unsigned long bits, ack; | |
110 | int cascade; | |
111 | ||
112 | for (;;) { | |
113 | bits = in_be64(&node_iic->iic_is); | |
114 | if (bits == 0) | |
115 | break; | |
116 | /* pre-ack edge interrupts */ | |
117 | ack = bits & IIC_ISR_EDGE_MASK; | |
118 | if (ack) | |
119 | out_be64(&node_iic->iic_is, ack); | |
120 | /* handle them */ | |
121 | for (cascade = 63; cascade >= 0; cascade--) | |
122 | if (bits & (0x8000000000000000UL >> cascade)) { | |
123 | unsigned int cirq = | |
124 | irq_linear_revmap(iic_host, | |
125 | base | cascade); | |
ef24ba70 | 126 | if (cirq) |
49f19ce4 | 127 | generic_handle_irq(cirq); |
2e194583 BH |
128 | } |
129 | /* post-ack level interrupts */ | |
130 | ack = bits & ~IIC_ISR_EDGE_MASK; | |
131 | if (ack) | |
132 | out_be64(&node_iic->iic_is, ack); | |
133 | } | |
d1ae63d4 | 134 | chip->irq_eoi(&desc->irq_data); |
2e194583 BH |
135 | } |
136 | ||
137 | ||
138 | static struct irq_chip iic_ioexc_chip = { | |
fc380c0c | 139 | .name = "CELL-IOEX", |
d1ae63d4 LB |
140 | .irq_mask = iic_mask, |
141 | .irq_unmask = iic_unmask, | |
142 | .irq_eoi = iic_ioexc_eoi, | |
2e194583 BH |
143 | }; |
144 | ||
cebf589c | 145 | /* Get an IRQ number from the pending state register of the IIC */ |
35a84c2f | 146 | static unsigned int iic_get_irq(void) |
d0e57c68 | 147 | { |
9e6ee340 GL |
148 | struct cbe_iic_pending_bits pending; |
149 | struct iic *iic; | |
2e194583 | 150 | unsigned int virq; |
9e6ee340 | 151 | |
69111bac | 152 | iic = this_cpu_ptr(&cpu_iic); |
9e6ee340 | 153 | *(unsigned long *) &pending = |
b36ac9e8 | 154 | in_be64((u64 __iomem *) &iic->regs->pending_destr); |
2e194583 | 155 | if (!(pending.flags & CBE_IIC_IRQ_VALID)) |
ef24ba70 | 156 | return 0; |
2e194583 | 157 | virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending)); |
ef24ba70 ME |
158 | if (!virq) |
159 | return 0; | |
9e6ee340 GL |
160 | iic->eoi_stack[++iic->eoi_ptr] = pending.prio; |
161 | BUG_ON(iic->eoi_ptr > 15); | |
2e194583 | 162 | return virq; |
cebf589c AB |
163 | } |
164 | ||
4bfac368 OJ |
165 | void iic_setup_cpu(void) |
166 | { | |
b0dd00ad | 167 | out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff); |
4bfac368 OJ |
168 | } |
169 | ||
170 | u8 iic_get_target_id(int cpu) | |
171 | { | |
6b7487fc | 172 | return per_cpu(cpu_iic, cpu).target_id; |
4bfac368 OJ |
173 | } |
174 | ||
175 | EXPORT_SYMBOL_GPL(iic_get_target_id); | |
176 | ||
cebf589c | 177 | #ifdef CONFIG_SMP |
a84195f3 AB |
178 | |
179 | /* Use the highest interrupt priorities for IPI */ | |
d5a1c193 | 180 | static inline int iic_msg_to_irq(int msg) |
a84195f3 | 181 | { |
d5a1c193 | 182 | return IIC_IRQ_TYPE_IPI + 0xf - msg; |
a84195f3 AB |
183 | } |
184 | ||
d5a1c193 | 185 | void iic_message_pass(int cpu, int msg) |
cebf589c | 186 | { |
d5a1c193 | 187 | out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4); |
cebf589c AB |
188 | } |
189 | ||
d5a1c193 | 190 | static void iic_request_ipi(int msg) |
cebf589c | 191 | { |
2e194583 | 192 | int virq; |
a84195f3 | 193 | |
d5a1c193 | 194 | virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg)); |
ef24ba70 | 195 | if (!virq) { |
2e194583 | 196 | printk(KERN_ERR |
d5a1c193 | 197 | "iic: failed to map IPI %s\n", smp_ipi_name[msg]); |
2e194583 | 198 | return; |
0ebfff14 | 199 | } |
7ef71d75 MM |
200 | |
201 | /* | |
202 | * If smp_request_message_ipi encounters an error it will notify | |
203 | * the error. If a message is not needed it will return non-zero. | |
204 | */ | |
d5a1c193 | 205 | if (smp_request_message_ipi(virq, msg)) |
7ef71d75 | 206 | irq_dispose_mapping(virq); |
cebf589c AB |
207 | } |
208 | ||
209 | void iic_request_IPIs(void) | |
210 | { | |
7ef71d75 MM |
211 | iic_request_ipi(PPC_MSG_CALL_FUNCTION); |
212 | iic_request_ipi(PPC_MSG_RESCHEDULE); | |
1b67bee1 | 213 | iic_request_ipi(PPC_MSG_TICK_BROADCAST); |
ddd703ca | 214 | iic_request_ipi(PPC_MSG_NMI_IPI); |
cebf589c | 215 | } |
0ebfff14 | 216 | |
cebf589c AB |
217 | #endif /* CONFIG_SMP */ |
218 | ||
0ebfff14 | 219 | |
ad3aedfb MZ |
220 | static int iic_host_match(struct irq_domain *h, struct device_node *node, |
221 | enum irq_domain_bus_token bus_token) | |
0ebfff14 | 222 | { |
55b61fec | 223 | return of_device_is_compatible(node, |
2e194583 | 224 | "IBM,CBEA-Internal-Interrupt-Controller"); |
0ebfff14 BH |
225 | } |
226 | ||
bae1d8f1 | 227 | static int iic_host_map(struct irq_domain *h, unsigned int virq, |
6e99e458 | 228 | irq_hw_number_t hw) |
0ebfff14 | 229 | { |
2e194583 BH |
230 | switch (hw & IIC_IRQ_TYPE_MASK) { |
231 | case IIC_IRQ_TYPE_IPI: | |
ec775d0e | 232 | irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq); |
2e194583 BH |
233 | break; |
234 | case IIC_IRQ_TYPE_IOEXC: | |
ec775d0e | 235 | irq_set_chip_and_handler(virq, &iic_ioexc_chip, |
e122996a | 236 | handle_edge_eoi_irq); |
2e194583 BH |
237 | break; |
238 | default: | |
ec775d0e | 239 | irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq); |
2e194583 | 240 | } |
0ebfff14 BH |
241 | return 0; |
242 | } | |
243 | ||
bae1d8f1 | 244 | static int iic_host_xlate(struct irq_domain *h, struct device_node *ct, |
40d50cf7 | 245 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
246 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
247 | ||
cebf589c | 248 | { |
2e194583 BH |
249 | unsigned int node, ext, unit, class; |
250 | const u32 *val; | |
251 | ||
55b61fec | 252 | if (!of_device_is_compatible(ct, |
2e194583 BH |
253 | "IBM,CBEA-Internal-Interrupt-Controller")) |
254 | return -ENODEV; | |
255 | if (intsize != 1) | |
256 | return -ENODEV; | |
e2eb6392 | 257 | val = of_get_property(ct, "#interrupt-cells", NULL); |
2e194583 BH |
258 | if (val == NULL || *val != 1) |
259 | return -ENODEV; | |
260 | ||
261 | node = intspec[0] >> 24; | |
262 | ext = (intspec[0] >> 16) & 0xff; | |
263 | class = (intspec[0] >> 8) & 0xff; | |
264 | unit = intspec[0] & 0xff; | |
265 | ||
266 | /* Check if node is in supported range */ | |
267 | if (node > 1) | |
268 | return -EINVAL; | |
269 | ||
270 | /* Build up interrupt number, special case for IO exceptions */ | |
271 | *out_hwirq = (node << IIC_IRQ_NODE_SHIFT); | |
272 | if (unit == IIC_UNIT_IIC && class == 1) | |
273 | *out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext; | |
274 | else | |
275 | *out_hwirq |= IIC_IRQ_TYPE_NORMAL | | |
276 | (class << IIC_IRQ_CLASS_SHIFT) | unit; | |
277 | ||
278 | /* Dummy flags, ignored by iic code */ | |
279 | *out_flags = IRQ_TYPE_EDGE_RISING; | |
280 | ||
281 | return 0; | |
0ebfff14 BH |
282 | } |
283 | ||
9f70b8eb | 284 | static const struct irq_domain_ops iic_host_ops = { |
0ebfff14 BH |
285 | .match = iic_host_match, |
286 | .map = iic_host_map, | |
287 | .xlate = iic_host_xlate, | |
288 | }; | |
289 | ||
290 | static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr, | |
2e194583 | 291 | struct device_node *node) |
0ebfff14 BH |
292 | { |
293 | /* XXX FIXME: should locate the linux CPU number from the HW cpu | |
294 | * number properly. We are lucky for now | |
295 | */ | |
6b7487fc | 296 | struct iic *iic = &per_cpu(cpu_iic, hw_cpu); |
cebf589c | 297 | |
0ebfff14 BH |
298 | iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs)); |
299 | BUG_ON(iic->regs == NULL); | |
b9e5b4e6 | 300 | |
0ebfff14 BH |
301 | iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe); |
302 | iic->eoi_stack[0] = 0xff; | |
2e194583 | 303 | iic->node = of_node_get(node); |
0ebfff14 BH |
304 | out_be64(&iic->regs->prio, 0); |
305 | ||
2e194583 BH |
306 | printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n", |
307 | hw_cpu, iic->target_id, node->full_name); | |
0ebfff14 BH |
308 | } |
309 | ||
310 | static int __init setup_iic(void) | |
311 | { | |
312 | struct device_node *dn; | |
313 | struct resource r0, r1; | |
2e194583 | 314 | unsigned int node, cascade, found = 0; |
43b4f406 | 315 | struct cbe_iic_regs __iomem *node_iic; |
9e6ee340 | 316 | const u32 *np; |
0ebfff14 BH |
317 | |
318 | for (dn = NULL; | |
319 | (dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) { | |
55b61fec | 320 | if (!of_device_is_compatible(dn, |
0ebfff14 BH |
321 | "IBM,CBEA-Internal-Interrupt-Controller")) |
322 | continue; | |
e2eb6392 | 323 | np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL); |
9e6ee340 | 324 | if (np == NULL) { |
0ebfff14 BH |
325 | printk(KERN_WARNING "IIC: CPU association not found\n"); |
326 | of_node_put(dn); | |
327 | return -ENODEV; | |
cebf589c | 328 | } |
0ebfff14 BH |
329 | if (of_address_to_resource(dn, 0, &r0) || |
330 | of_address_to_resource(dn, 1, &r1)) { | |
331 | printk(KERN_WARNING "IIC: Can't resolve addresses\n"); | |
332 | of_node_put(dn); | |
333 | return -ENODEV; | |
334 | } | |
2e194583 BH |
335 | found++; |
336 | init_one_iic(np[0], r0.start, dn); | |
337 | init_one_iic(np[1], r1.start, dn); | |
338 | ||
339 | /* Setup cascade for IO exceptions. XXX cleanup tricks to get | |
340 | * node vs CPU etc... | |
341 | * Note that we configure the IIC_IRR here with a hard coded | |
342 | * priority of 1. We might want to improve that later. | |
343 | */ | |
344 | node = np[0] >> 1; | |
345 | node_iic = cbe_get_cpu_iic_regs(np[0]); | |
346 | cascade = node << IIC_IRQ_NODE_SHIFT; | |
347 | cascade |= 1 << IIC_IRQ_CLASS_SHIFT; | |
348 | cascade |= IIC_UNIT_IIC; | |
349 | cascade = irq_create_mapping(iic_host, cascade); | |
ef24ba70 | 350 | if (!cascade) |
2e194583 | 351 | continue; |
43b4f406 AB |
352 | /* |
353 | * irq_data is a generic pointer that gets passed back | |
354 | * to us later, so the forced cast is fine. | |
355 | */ | |
ec775d0e TG |
356 | irq_set_handler_data(cascade, (void __force *)node_iic); |
357 | irq_set_chained_handler(cascade, iic_ioexc_cascade); | |
2e194583 BH |
358 | out_be64(&node_iic->iic_ir, |
359 | (1 << 12) /* priority */ | | |
360 | (node << 4) /* dest node */ | | |
361 | IIC_UNIT_THREAD_0 /* route them to thread 0 */); | |
362 | /* Flush pending (make sure it triggers if there is | |
363 | * anything pending | |
364 | */ | |
365 | out_be64(&node_iic->iic_is, 0xfffffffffffffffful); | |
cebf589c | 366 | } |
0ebfff14 BH |
367 | |
368 | if (found) | |
369 | return 0; | |
370 | else | |
371 | return -ENODEV; | |
cebf589c AB |
372 | } |
373 | ||
b9e5b4e6 | 374 | void __init iic_init_IRQ(void) |
cebf589c | 375 | { |
2e194583 | 376 | /* Setup an irq host data structure */ |
a8db8cf0 GL |
377 | iic_host = irq_domain_add_linear(NULL, IIC_SOURCE_COUNT, &iic_host_ops, |
378 | NULL); | |
2e194583 BH |
379 | BUG_ON(iic_host == NULL); |
380 | irq_set_default_host(iic_host); | |
381 | ||
0ebfff14 | 382 | /* Discover and initialize iics */ |
d0e57c68 | 383 | if (setup_iic() < 0) |
0ebfff14 | 384 | panic("IIC: Failed to initialize !\n"); |
d0e57c68 | 385 | |
0ebfff14 BH |
386 | /* Set master interrupt handling function */ |
387 | ppc_md.get_irq = iic_get_irq; | |
b9e5b4e6 | 388 | |
0ebfff14 BH |
389 | /* Enable on current CPU */ |
390 | iic_setup_cpu(); | |
cebf589c | 391 | } |
0443bbd3 KC |
392 | |
393 | void iic_set_interrupt_routing(int cpu, int thread, int priority) | |
394 | { | |
395 | struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu); | |
396 | u64 iic_ir = 0; | |
397 | int node = cpu >> 1; | |
398 | ||
399 | /* Set which node and thread will handle the next interrupt */ | |
400 | iic_ir |= CBE_IIC_IR_PRIO(priority) | | |
401 | CBE_IIC_IR_DEST_NODE(node); | |
402 | if (thread == 0) | |
403 | iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0); | |
404 | else | |
405 | iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1); | |
406 | out_be64(&iic_regs->iic_ir, iic_ir); | |
407 | } |