[linux-2.6-block.git] / arch / powerpc / platforms / cell / celleb_scc_pciex.c

/*
 * Support for Celleb PCI-Express.
 *
 * (C) Copyright 2007-2008 TOSHIBA CORPORATION
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/iommu.h>
#include <asm/byteorder.h>

#include "celleb_scc.h"
#include "celleb_pci.h"

#define PEX_IN(base, off)	in_be32((void __iomem *)(base) + (off))
#define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data))

static void scc_pciex_io_flush(struct iowa_bus *bus)
{
	(void)PEX_IN(bus->phb->cfg_addr, PEXDMRDEN0);
}

/*
 * Memory space access to device on PCIEX
 */
#define PCIEX_MMIO_READ(name, ret)					\
static ret scc_pciex_##name(const PCI_IO_ADDR addr)			\
{									\
	ret val = __do_##name(addr);					\
	scc_pciex_io_flush(iowa_mem_find_bus(addr));			\
	return val;							\
}

#define PCIEX_MMIO_READ_STR(name)					\
static void scc_pciex_##name(const PCI_IO_ADDR addr, void *buf,		\
			     unsigned long count)			\
{									\
	__do_##name(addr, buf, count);					\
	scc_pciex_io_flush(iowa_mem_find_bus(addr));			\
}

PCIEX_MMIO_READ(readb, u8)
PCIEX_MMIO_READ(readw, u16)
PCIEX_MMIO_READ(readl, u32)
PCIEX_MMIO_READ(readq, u64)
PCIEX_MMIO_READ(readw_be, u16)
PCIEX_MMIO_READ(readl_be, u32)
PCIEX_MMIO_READ(readq_be, u64)
PCIEX_MMIO_READ_STR(readsb)
PCIEX_MMIO_READ_STR(readsw)
PCIEX_MMIO_READ_STR(readsl)

static void scc_pciex_memcpy_fromio(void *dest, const PCI_IO_ADDR src,
				    unsigned long n)
{
	__do_memcpy_fromio(dest, src, n);
	scc_pciex_io_flush(iowa_mem_find_bus(src));
}

/*
 * I/O port access to devices on PCIEX.
 */

static inline unsigned long get_bus_address(struct pci_controller *phb,
					    unsigned long port)
{
	return port - ((unsigned long)(phb->io_base_virt) - _IO_BASE);
}

static u32 scc_pciex_read_port(struct pci_controller *phb,
			       unsigned long port, int size)
{
	unsigned int byte_enable;
	unsigned int cmd, shift;
	unsigned long addr;
	u32 data, ret;

	BUG_ON(((port & 0x3ul) + size) > 4);

	addr = get_bus_address(phb, port);
	shift = addr & 0x3ul;
	byte_enable = ((1 << size) - 1) << shift;
	cmd = PEXDCMND_IO_READ | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
	PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
	PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
	data = PEX_IN(phb->cfg_addr, PEXDRDATA);
	ret = (data >> (shift * 8)) & (0xFFFFFFFF >> ((4 - size) * 8));

	pr_debug("PCIEX:PIO READ:port=0x%lx, addr=0x%lx, size=%d, be=%x,"
		 " cmd=%x, data=%x, ret=%x\n", port, addr, size, byte_enable,
		 cmd, data, ret);

	return ret;
}

static void scc_pciex_write_port(struct pci_controller *phb,
				 unsigned long port, int size, u32 val)
{
	unsigned int byte_enable;
	unsigned int cmd, shift;
	unsigned long addr;
	u32 data;

	BUG_ON(((port & 0x3ul) + size) > 4);

	addr = get_bus_address(phb, port);
	shift = addr & 0x3ul;
	byte_enable = ((1 << size) - 1) << shift;
	cmd = PEXDCMND_IO_WRITE | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
	data = (val & (0xFFFFFFFF >> (4 - size) * 8)) << (shift * 8);
	PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
	PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
	PEX_OUT(phb->cfg_addr, PEXDWDATA, data);

	pr_debug("PCIEX:PIO WRITE:port=0x%lx, addr=%lx, size=%d, val=%x,"
		 " be=%x, cmd=%x, data=%x\n", port, addr, size, val,
		 byte_enable, cmd, data);
}

static u8 __scc_pciex_inb(struct pci_controller *phb, unsigned long port)
{
	return (u8)scc_pciex_read_port(phb, port, 1);
}

static u16 __scc_pciex_inw(struct pci_controller *phb, unsigned long port)
{
	u32 data;
	if ((port & 0x3ul) < 3)
		data = scc_pciex_read_port(phb, port, 2);
	else {
		u32 d1 = scc_pciex_read_port(phb, port, 1);
		u32 d2 = scc_pciex_read_port(phb, port + 1, 1);
		data = d1 | (d2 << 8);
	}
	return (u16)data;
}

static u32 __scc_pciex_inl(struct pci_controller *phb, unsigned long port)
{
	unsigned int mod = port & 0x3ul;
	u32 data;
	if (mod == 0)
		data = scc_pciex_read_port(phb, port, 4);
	else {
		u32 d1 = scc_pciex_read_port(phb, port, 4 - mod);
		u32 d2 = scc_pciex_read_port(phb, port + 1, mod);
		data = d1 | (d2 << (mod * 8));
	}
	return data;
}

static void __scc_pciex_outb(struct pci_controller *phb,
			     u8 val, unsigned long port)
{
	scc_pciex_write_port(phb, port, 1, (u32)val);
}

static void __scc_pciex_outw(struct pci_controller *phb,
			     u16 val, unsigned long port)
{
	if ((port & 0x3ul) < 3)
		scc_pciex_write_port(phb, port, 2, (u32)val);
	else {
		u32 d1 = val & 0x000000FF;
		u32 d2 = (val & 0x0000FF00) >> 8;
		scc_pciex_write_port(phb, port, 1, d1);
		scc_pciex_write_port(phb, port + 1, 1, d2);
	}
}

static void __scc_pciex_outl(struct pci_controller *phb,
			     u32 val, unsigned long port)
{
	unsigned int mod = port & 0x3ul;
	if (mod == 0)
		scc_pciex_write_port(phb, port, 4, val);
	else {
		u32 d1 = val & (0xFFFFFFFFul >> (mod * 8));
		u32 d2 = val >> ((4 - mod) * 8);
		scc_pciex_write_port(phb, port, 4 - mod, d1);
		scc_pciex_write_port(phb, port + 1, mod, d2);
	}
}

#define PCIEX_PIO_FUNC(size, name)					\
static u##size scc_pciex_in##name(unsigned long port)			\
{									\
	struct iowa_bus *bus = iowa_pio_find_bus(port);			\
	u##size data = __scc_pciex_in##name(bus->phb, port);		\
	scc_pciex_io_flush(bus);					\
	return data;							\
}									\
static void scc_pciex_ins##name(unsigned long p, void *b, unsigned long c) \
{									\
	struct iowa_bus *bus = iowa_pio_find_bus(p);			\
	__le##size *dst = b;						\
	for (; c != 0; c--, dst++)					\
		*dst = cpu_to_le##size(__scc_pciex_in##name(bus->phb, p)); \
	scc_pciex_io_flush(bus);					\
}									\
static void scc_pciex_out##name(u##size val, unsigned long port)	\
{									\
	struct iowa_bus *bus = iowa_pio_find_bus(port);			\
	__scc_pciex_out##name(bus->phb, val, port);			\
}									\
static void scc_pciex_outs##name(unsigned long p, const void *b,	\
				 unsigned long c)			\
{									\
	struct iowa_bus *bus = iowa_pio_find_bus(p);			\
	const __le##size *src = b;					\
	for (; c != 0; c--, src++)					\
		__scc_pciex_out##name(bus->phb, le##size##_to_cpu(*src), p); \
}
#define __le8 u8
#define cpu_to_le8(x) (x)
#define le8_to_cpu(x) (x)
PCIEX_PIO_FUNC(8, b)
PCIEX_PIO_FUNC(16, w)
PCIEX_PIO_FUNC(32, l)

static struct ppc_pci_io scc_pciex_ops = {
	.readb = scc_pciex_readb,
	.readw = scc_pciex_readw,
	.readl = scc_pciex_readl,
	.readq = scc_pciex_readq,
	.readw_be = scc_pciex_readw_be,
	.readl_be = scc_pciex_readl_be,
	.readq_be = scc_pciex_readq_be,
	.readsb = scc_pciex_readsb,
	.readsw = scc_pciex_readsw,
	.readsl = scc_pciex_readsl,
	.memcpy_fromio = scc_pciex_memcpy_fromio,
	.inb = scc_pciex_inb,
	.inw = scc_pciex_inw,
	.inl = scc_pciex_inl,
	.outb = scc_pciex_outb,
	.outw = scc_pciex_outw,
	.outl = scc_pciex_outl,
	.insb = scc_pciex_insb,
	.insw = scc_pciex_insw,
	.insl = scc_pciex_insl,
	.outsb = scc_pciex_outsb,
	.outsw = scc_pciex_outsw,
	.outsl = scc_pciex_outsl,
};

static int __init scc_pciex_iowa_init(struct iowa_bus *bus, void *data)
{
	dma_addr_t dummy_page_da;
	void *dummy_page_va;

	dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
	if (!dummy_page_va) {
		pr_err("PCIEX:Alloc dummy_page_va failed\n");
		return -1;
	}

	dummy_page_da = dma_map_single(bus->phb->parent, dummy_page_va,
				       PAGE_SIZE, DMA_FROM_DEVICE);
	if (dma_mapping_error(bus->phb->parent, dummy_page_da)) {
		pr_err("PCIEX:Map dummy page failed.\n");
		kfree(dummy_page_va);
		return -1;
	}

	PEX_OUT(bus->phb->cfg_addr, PEXDMRDADR0, dummy_page_da);

	return 0;
}

/*
 * config space access
 */
#define MK_PEXDADRS(bus_no, dev_no, func_no, addr) \
	((uint32_t)(((addr) & ~0x3UL) | \
	((bus_no) << PEXDADRS_BUSNO_SHIFT) | \
	((dev_no)  << PEXDADRS_DEVNO_SHIFT) | \
	((func_no) << PEXDADRS_FUNCNO_SHIFT)))

#define MK_PEXDCMND_BYTE_EN(addr, size) \
	((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT)
#define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size))

static uint32_t config_read_pciex_dev(unsigned int __iomem *base,
		uint64_t bus_no, uint64_t dev_no, uint64_t func_no,
		uint64_t off, uint64_t size)
{
	uint32_t ret;
	uint32_t addr, cmd;

	addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
	cmd = MK_PEXDCMND(PEXDCMND_CONFIG_READ, off, size);
	PEX_OUT(base, PEXDADRS, addr);
	PEX_OUT(base, PEXDCMND, cmd);
	ret = (PEX_IN(base, PEXDRDATA)
		>> ((off & (4-size)) * 8)) & ((0x1 << (size * 8)) - 1);
	return ret;
}

static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no,
	uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size,
	uint32_t data)
{
	uint32_t addr, cmd;

	addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
	cmd = MK_PEXDCMND(PEXDCMND_CONFIG_WRITE, off, size);
	PEX_OUT(base, PEXDADRS, addr);
	PEX_OUT(base, PEXDCMND, cmd);
	PEX_OUT(base, PEXDWDATA,
		(data & ((0x1 << (size * 8)) - 1)) << ((off & (4-size)) * 8));
}

#define MK_PEXCADRS_BYTE_EN(off, len) \
	((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT)
#define MK_PEXCADRS(cmd, addr, size) \
	((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3))
static uint32_t config_read_pciex_rc(unsigned int __iomem *base,
				     uint32_t where, uint32_t size)
{
	PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size));
	return (PEX_IN(base, PEXCRDATA)
		>> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1);
}

static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
				  uint32_t size, uint32_t val)
{
	uint32_t data;

	data = (val & ((0x1 << (size * 8)) - 1)) << ((where & (4 - size)) * 8);
	PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_WRITE, where, size));
	PEX_OUT(base, PEXCWDATA, data);
}

/* Interfaces */
/* Note: Work-around
 *  On SCC PCIEXC, one device is seen on all 32 dev_no.
 *  As SCC PCIEXC can have only one device on the bus, we look only one dev_no.
 * (dev_no = 1)
 */
static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
				 int where, int size, unsigned int *val)
{
	struct pci_controller *phb = pci_bus_to_host(bus);

	if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) {
		*val = ~0;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	if (bus->number == 0 && PCI_SLOT(devfn) == 0)
		*val = config_read_pciex_rc(phb->cfg_addr, where, size);
	else
		*val = config_read_pciex_dev(phb->cfg_addr, bus->number,
				PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);

	return PCIBIOS_SUCCESSFUL;
}

static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
				  int where, int size, unsigned int val)
{
	struct pci_controller *phb = pci_bus_to_host(bus);

	if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (bus->number == 0 && PCI_SLOT(devfn) == 0)
		config_write_pciex_rc(phb->cfg_addr, where, size, val);
	else
		config_write_pciex_dev(phb->cfg_addr, bus->number,
			PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops scc_pciex_pci_ops = {
	.read = scc_pciex_read_config,
	.write = scc_pciex_write_config,
};

static void pciex_clear_intr_all(unsigned int __iomem *base)
{
	PEX_OUT(base, PEXAERRSTS, 0xffffffff);
	PEX_OUT(base, PEXPRERRSTS, 0xffffffff);
	PEX_OUT(base, PEXINTSTS, 0xffffffff);
}

#if 0
static void pciex_disable_intr_all(unsigned int *base)
{
	PEX_OUT(base, PEXINTMASK,   0x0);
	PEX_OUT(base, PEXAERRMASK,  0x0);
	PEX_OUT(base, PEXPRERRMASK, 0x0);
	PEX_OUT(base, PEXVDMASK,    0x0);
}
#endif

static void pciex_enable_intr_all(unsigned int __iomem *base)
{
	PEX_OUT(base, PEXINTMASK, 0x0000e7f1);
	PEX_OUT(base, PEXAERRMASK, 0x03ff01ff);
	PEX_OUT(base, PEXPRERRMASK, 0x0001010f);
	PEX_OUT(base, PEXVDMASK, 0x00000001);
}

static void pciex_check_status(unsigned int __iomem *base)
{
	uint32_t err = 0;
	uint32_t intsts, aerr, prerr, rcvcp, lenerr;
	uint32_t maea, maec;

	intsts = PEX_IN(base, PEXINTSTS);
	aerr = PEX_IN(base, PEXAERRSTS);
	prerr = PEX_IN(base, PEXPRERRSTS);
	rcvcp = PEX_IN(base, PEXRCVCPLIDA);
	lenerr = PEX_IN(base, PEXLENERRIDA);

	if (intsts || aerr || prerr || rcvcp || lenerr)
		err = 1;

	pr_info("PCEXC interrupt!!\n");
	pr_info("PEXINTSTS    :0x%08x\n", intsts);
	pr_info("PEXAERRSTS   :0x%08x\n", aerr);
	pr_info("PEXPRERRSTS  :0x%08x\n", prerr);
	pr_info("PEXRCVCPLIDA :0x%08x\n", rcvcp);
	pr_info("PEXLENERRIDA :0x%08x\n", lenerr);

	/* print detail of Protection Error */
	if (intsts & 0x00004000) {
		uint32_t i, n;
		for (i = 0; i < 4; i++) {
			n = 1 << i;
			if (prerr & n) {
				maea = PEX_IN(base, PEXMAEA(i));
				maec = PEX_IN(base, PEXMAEC(i));
				pr_info("PEXMAEC%d     :0x%08x\n", i, maec);
				pr_info("PEXMAEA%d     :0x%08x\n", i, maea);
			}
		}
	}

	if (err)
		pciex_clear_intr_all(base);
}

static irqreturn_t pciex_handle_internal_irq(int irq, void *dev_id)
{
	struct pci_controller *phb = dev_id;

	pr_debug("PCIEX:pciex_handle_internal_irq(irq=%d)\n", irq);

	BUG_ON(phb->cfg_addr == NULL);

	pciex_check_status(phb->cfg_addr);

	return IRQ_HANDLED;
}

static __init int celleb_setup_pciex(struct device_node *node,
				     struct pci_controller *phb)
{
	struct resource	r;
	int virq;

	/* SMMIO registers; used inside this file */
	if (of_address_to_resource(node, 0, &r)) {
		pr_err("PCIEXC:Failed to get config resource.\n");
		return 1;
	}
	phb->cfg_addr = ioremap(r.start, resource_size(&r));
	if (!phb->cfg_addr) {
		pr_err("PCIEXC:Failed to remap SMMIO region.\n");
		return 1;
	}

	/* Not use cfg_data,  cmd and data regs are near address reg */
	phb->cfg_data = NULL;

	/* set pci_ops */
	phb->ops = &scc_pciex_pci_ops;

	/* internal interrupt handler */
	virq = irq_of_parse_and_map(node, 1);
	if (!virq) {
		pr_err("PCIEXC:Failed to map irq\n");
		goto error;
	}
	if (request_irq(virq, pciex_handle_internal_irq,
			0, "pciex", (void *)phb)) {
		pr_err("PCIEXC:Failed to request irq\n");
		goto error;
	}

	/* enable all interrupts */
	pciex_clear_intr_all(phb->cfg_addr);
	pciex_enable_intr_all(phb->cfg_addr);
	/* MSI: TBD */

	return 0;

error:
	phb->cfg_data = NULL;
	if (phb->cfg_addr)
		iounmap(phb->cfg_addr);
	phb->cfg_addr = NULL;
	return 1;
}

struct celleb_phb_spec celleb_pciex_spec __initdata = {
	.setup = celleb_setup_pciex,
	.ops = &scc_pciex_ops,
	.iowa_init = &scc_pciex_iowa_init,
};
Commit	Line	Data
884d04cd IK	1	/*
	2	* Support for Celleb PCI-Express.
	3	*
	4	* (C) Copyright 2007-2008 TOSHIBA CORPORATION
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	#undef DEBUG
	22
	23	#include <linux/kernel.h>
	24	#include <linux/pci.h>
	25	#include <linux/string.h>
5a0e3ad6	26	#include <linux/slab.h>
884d04cd	27	#include <linux/init.h>
884d04cd IK	28	#include <linux/delay.h>
	29	#include <linux/interrupt.h>
	30
	31	#include <asm/io.h>
	32	#include <asm/irq.h>
	33	#include <asm/iommu.h>
	34	#include <asm/byteorder.h>
	35
	36	#include "celleb_scc.h"
	37	#include "celleb_pci.h"
	38
24caa6a0 AV	39	#define PEX_IN(base, off) in_be32((void __iomem *)(base) + (off))
24caa6a0 AV	40	#define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data))
884d04cd IK	41
	42	static void scc_pciex_io_flush(struct iowa_bus *bus)
	43	{
	44	(void)PEX_IN(bus->phb->cfg_addr, PEXDMRDEN0);
	45	}
	46
	47	/*
	48	* Memory space access to device on PCIEX
	49	*/
	50	#define PCIEX_MMIO_READ(name, ret) \
	51	static ret scc_pciex_##name(const PCI_IO_ADDR addr) \
	52	{ \
	53	ret val = __do_##name(addr); \
	54	scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
	55	return val; \
	56	}
	57
	58	#define PCIEX_MMIO_READ_STR(name) \
	59	static void scc_pciex_##name(const PCI_IO_ADDR addr, void *buf, \
	60	unsigned long count) \
	61	{ \
	62	__do_##name(addr, buf, count); \
	63	scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
	64	}
	65
	66	PCIEX_MMIO_READ(readb, u8)
	67	PCIEX_MMIO_READ(readw, u16)
	68	PCIEX_MMIO_READ(readl, u32)
	69	PCIEX_MMIO_READ(readq, u64)
	70	PCIEX_MMIO_READ(readw_be, u16)
	71	PCIEX_MMIO_READ(readl_be, u32)
	72	PCIEX_MMIO_READ(readq_be, u64)
	73	PCIEX_MMIO_READ_STR(readsb)
	74	PCIEX_MMIO_READ_STR(readsw)
	75	PCIEX_MMIO_READ_STR(readsl)
	76
	77	static void scc_pciex_memcpy_fromio(void *dest, const PCI_IO_ADDR src,
	78	unsigned long n)
	79	{
	80	__do_memcpy_fromio(dest, src, n);
	81	scc_pciex_io_flush(iowa_mem_find_bus(src));
	82	}
	83
	84	/*
	85	* I/O port access to devices on PCIEX.
	86	*/
	87
	88	static inline unsigned long get_bus_address(struct pci_controller *phb,
	89	unsigned long port)
	90	{
	91	return port - ((unsigned long)(phb->io_base_virt) - _IO_BASE);
	92	}
	93
	94	static u32 scc_pciex_read_port(struct pci_controller *phb,
	95	unsigned long port, int size)
	96	{
	97	unsigned int byte_enable;
	98	unsigned int cmd, shift;
	99	unsigned long addr;
	100	u32 data, ret;
	101
	102	BUG_ON(((port & 0x3ul) + size) > 4);
	103
	104	addr = get_bus_address(phb, port);
105	shift = addr & 0x3ul;
106	byte_enable = ((1 << size) - 1) << shift;
107	cmd = PEXDCMND_IO_READ \| (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
108	PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
109	PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
110	data = PEX_IN(phb->cfg_addr, PEXDRDATA);
111	ret = (data >> (shift * 8)) & (0xFFFFFFFF >> ((4 - size) * 8));
112
113	pr_debug("PCIEX:PIO READ:port=0x%lx, addr=0x%lx, size=%d, be=%x,"
114	" cmd=%x, data=%x, ret=%x\n", port, addr, size, byte_enable,
115	cmd, data, ret);
116
117	return ret;
118	}
119
120	static void scc_pciex_write_port(struct pci_controller *phb,
121	unsigned long port, int size, u32 val)
122	{
123	unsigned int byte_enable;
124	unsigned int cmd, shift;
125	unsigned long addr;
126	u32 data;
127
128	BUG_ON(((port & 0x3ul) + size) > 4);
129
130	addr = get_bus_address(phb, port);
131	shift = addr & 0x3ul;
132	byte_enable = ((1 << size) - 1) << shift;
133	cmd = PEXDCMND_IO_WRITE \| (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
134	data = (val & (0xFFFFFFFF >> (4 - size) * 8)) << (shift * 8);
135	PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
136	PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
137	PEX_OUT(phb->cfg_addr, PEXDWDATA, data);
138
139	pr_debug("PCIEX:PIO WRITE:port=0x%lx, addr=%lx, size=%d, val=%x,"
140	" be=%x, cmd=%x, data=%x\n", port, addr, size, val,
141	byte_enable, cmd, data);
142	}
143
144	static u8 __scc_pciex_inb(struct pci_controller *phb, unsigned long port)
145	{
146	return (u8)scc_pciex_read_port(phb, port, 1);
147	}
148
149	static u16 __scc_pciex_inw(struct pci_controller *phb, unsigned long port)
150	{
151	u32 data;
152	if ((port & 0x3ul) < 3)
153	data = scc_pciex_read_port(phb, port, 2);
154	else {
155	u32 d1 = scc_pciex_read_port(phb, port, 1);
156	u32 d2 = scc_pciex_read_port(phb, port + 1, 1);
157	data = d1 \| (d2 << 8);
158	}
159	return (u16)data;
160	}
161
162	static u32 __scc_pciex_inl(struct pci_controller *phb, unsigned long port)
163	{
164	unsigned int mod = port & 0x3ul;
165	u32 data;
166	if (mod == 0)
167	data = scc_pciex_read_port(phb, port, 4);
168	else {
169	u32 d1 = scc_pciex_read_port(phb, port, 4 - mod);
170	u32 d2 = scc_pciex_read_port(phb, port + 1, mod);
171	data = d1 \| (d2 << (mod * 8));
172	}
173	return data;
174	}
175
176	static void __scc_pciex_outb(struct pci_controller *phb,
177	u8 val, unsigned long port)
178	{
179	scc_pciex_write_port(phb, port, 1, (u32)val);
180	}
181
182	static void __scc_pciex_outw(struct pci_controller *phb,
183	u16 val, unsigned long port)
184	{
185	if ((port & 0x3ul) < 3)
186	scc_pciex_write_port(phb, port, 2, (u32)val);
187	else {
188	u32 d1 = val & 0x000000FF;
189	u32 d2 = (val & 0x0000FF00) >> 8;
190	scc_pciex_write_port(phb, port, 1, d1);
191	scc_pciex_write_port(phb, port + 1, 1, d2);
192	}
193	}
194
195	static void __scc_pciex_outl(struct pci_controller *phb,
196	u32 val, unsigned long port)
197	{
198	unsigned int mod = port & 0x3ul;
199	if (mod == 0)
200	scc_pciex_write_port(phb, port, 4, val);
201	else {
202	u32 d1 = val & (0xFFFFFFFFul >> (mod * 8));
203	u32 d2 = val >> ((4 - mod) * 8);
204	scc_pciex_write_port(phb, port, 4 - mod, d1);
205	scc_pciex_write_port(phb, port + 1, mod, d2);
206	}
207	}
208
209	#define PCIEX_PIO_FUNC(size, name) \
210	static u##size scc_pciex_in##name(unsigned long port) \
211	{ \
212	struct iowa_bus *bus = iowa_pio_find_bus(port); \
213	u##size data = __scc_pciex_in##name(bus->phb, port); \
214	scc_pciex_io_flush(bus); \
215	return data; \
216	} \
217	static void scc_pciex_ins##name(unsigned long p, void *b, unsigned long c) \
218	{ \
219	struct iowa_bus *bus = iowa_pio_find_bus(p); \
c409d52b	220	__le##size *dst = b; \
884d04cd IK	221	for (; c != 0; c--, dst++) \
	222	*dst = cpu_to_le##size(__scc_pciex_in##name(bus->phb, p)); \
	223	scc_pciex_io_flush(bus); \
	224	} \
	225	static void scc_pciex_out##name(u##size val, unsigned long port) \
	226	{ \
	227	struct iowa_bus *bus = iowa_pio_find_bus(port); \
	228	__scc_pciex_out##name(bus->phb, val, port); \
	229	} \
	230	static void scc_pciex_outs##name(unsigned long p, const void *b, \
	231	unsigned long c) \
	232	{ \
	233	struct iowa_bus *bus = iowa_pio_find_bus(p); \
c409d52b	234	const __le##size *src = b; \
884d04cd IK	235	for (; c != 0; c--, src++) \
	236	__scc_pciex_out##name(bus->phb, le##size##_to_cpu(*src), p); \
	237	}
c409d52b	238	#define __le8 u8
884d04cd IK	239	#define cpu_to_le8(x) (x)
	240	#define le8_to_cpu(x) (x)
	241	PCIEX_PIO_FUNC(8, b)
	242	PCIEX_PIO_FUNC(16, w)
	243	PCIEX_PIO_FUNC(32, l)
	244
	245	static struct ppc_pci_io scc_pciex_ops = {
	246	.readb = scc_pciex_readb,
	247	.readw = scc_pciex_readw,
	248	.readl = scc_pciex_readl,
	249	.readq = scc_pciex_readq,
	250	.readw_be = scc_pciex_readw_be,
	251	.readl_be = scc_pciex_readl_be,
	252	.readq_be = scc_pciex_readq_be,
	253	.readsb = scc_pciex_readsb,
	254	.readsw = scc_pciex_readsw,
	255	.readsl = scc_pciex_readsl,
	256	.memcpy_fromio = scc_pciex_memcpy_fromio,
	257	.inb = scc_pciex_inb,
	258	.inw = scc_pciex_inw,
	259	.inl = scc_pciex_inl,
	260	.outb = scc_pciex_outb,
	261	.outw = scc_pciex_outw,
	262	.outl = scc_pciex_outl,
	263	.insb = scc_pciex_insb,
	264	.insw = scc_pciex_insw,
	265	.insl = scc_pciex_insl,
	266	.outsb = scc_pciex_outsb,
	267	.outsw = scc_pciex_outsw,
	268	.outsl = scc_pciex_outsl,
	269	};
	270
	271	static int __init scc_pciex_iowa_init(struct iowa_bus bus, void data)
	272	{
	273	dma_addr_t dummy_page_da;
	274	void *dummy_page_va;
	275
	276	dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
	277	if (!dummy_page_va) {
	278	pr_err("PCIEX:Alloc dummy_page_va failed\n");
	279	return -1;
	280	}
	281
	282	dummy_page_da = dma_map_single(bus->phb->parent, dummy_page_va,
	283	PAGE_SIZE, DMA_FROM_DEVICE);
8d8bb39b	284	if (dma_mapping_error(bus->phb->parent, dummy_page_da)) {
884d04cd IK	285	pr_err("PCIEX:Map dummy page failed.\n");
	286	kfree(dummy_page_va);
	287	return -1;
	288	}
	289
	290	PEX_OUT(bus->phb->cfg_addr, PEXDMRDADR0, dummy_page_da);
	291
	292	return 0;
	293	}
	294
	295	/*
	296	* config space access
	297	*/
	298	#define MK_PEXDADRS(bus_no, dev_no, func_no, addr) \
	299	((uint32_t)(((addr) & ~0x3UL) \| \
	300	((bus_no) << PEXDADRS_BUSNO_SHIFT) \| \
	301	((dev_no) << PEXDADRS_DEVNO_SHIFT) \| \
	302	((func_no) << PEXDADRS_FUNCNO_SHIFT)))
	303
	304	#define MK_PEXDCMND_BYTE_EN(addr, size) \
	305	((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT)
	306	#define MK_PEXDCMND(cmd, addr, size) ((cmd) \| MK_PEXDCMND_BYTE_EN(addr, size))
	307
24caa6a0	308	static uint32_t config_read_pciex_dev(unsigned int __iomem *base,
884d04cd IK	309	uint64_t bus_no, uint64_t dev_no, uint64_t func_no,
	310	uint64_t off, uint64_t size)
	311	{
	312	uint32_t ret;
	313	uint32_t addr, cmd;
	314
	315	addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
	316	cmd = MK_PEXDCMND(PEXDCMND_CONFIG_READ, off, size);
	317	PEX_OUT(base, PEXDADRS, addr);
	318	PEX_OUT(base, PEXDCMND, cmd);
	319	ret = (PEX_IN(base, PEXDRDATA)
	320	>> ((off & (4-size)) * 8)) & ((0x1 << (size * 8)) - 1);
	321	return ret;
	322	}
	323
24caa6a0	324	static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no,
884d04cd IK	325	uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size,
	326	uint32_t data)
	327	{
	328	uint32_t addr, cmd;
	329
	330	addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
	331	cmd = MK_PEXDCMND(PEXDCMND_CONFIG_WRITE, off, size);
	332	PEX_OUT(base, PEXDADRS, addr);
	333	PEX_OUT(base, PEXDCMND, cmd);
	334	PEX_OUT(base, PEXDWDATA,
	335	(data & ((0x1 << (size * 8)) - 1)) << ((off & (4-size)) * 8));
	336	}
	337
	338	#define MK_PEXCADRS_BYTE_EN(off, len) \
	339	((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT)
	340	#define MK_PEXCADRS(cmd, addr, size) \
	341	((cmd) \| MK_PEXCADRS_BYTE_EN(addr, size) \| ((addr) & ~0x3))
24caa6a0	342	static uint32_t config_read_pciex_rc(unsigned int __iomem *base,
884d04cd IK	343	uint32_t where, uint32_t size)
	344	{
	345	PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size));
	346	return (PEX_IN(base, PEXCRDATA)
	347	>> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1);
	348	}
	349
24caa6a0	350	static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
884d04cd IK	351	uint32_t size, uint32_t val)
	352	{
	353	uint32_t data;
	354
	355	data = (val & ((0x1 << (size * 8)) - 1)) << ((where & (4 - size)) * 8);
	356	PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_WRITE, where, size));
	357	PEX_OUT(base, PEXCWDATA, data);
	358	}
	359
	360	/* Interfaces */
	361	/* Note: Work-around
	362	* On SCC PCIEXC, one device is seen on all 32 dev_no.
	363	* As SCC PCIEXC can have only one device on the bus, we look only one dev_no.
	364	* (dev_no = 1)
	365	*/
	366	static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
	367	int where, int size, unsigned int *val)
	368	{
58513dc4	369	struct pci_controller *phb = pci_bus_to_host(bus);
884d04cd IK	370
	371	if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) {
	372	*val = ~0;
	373	return PCIBIOS_DEVICE_NOT_FOUND;
	374	}
	375
	376	if (bus->number == 0 && PCI_SLOT(devfn) == 0)
	377	*val = config_read_pciex_rc(phb->cfg_addr, where, size);
	378	else
	379	*val = config_read_pciex_dev(phb->cfg_addr, bus->number,
	380	PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
	381
	382	return PCIBIOS_SUCCESSFUL;
	383	}
	384
	385	static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
	386	int where, int size, unsigned int val)
	387	{
58513dc4	388	struct pci_controller *phb = pci_bus_to_host(bus);
884d04cd IK	389
	390	if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1)
	391	return PCIBIOS_DEVICE_NOT_FOUND;
	392
	393	if (bus->number == 0 && PCI_SLOT(devfn) == 0)
	394	config_write_pciex_rc(phb->cfg_addr, where, size, val);
	395	else
	396	config_write_pciex_dev(phb->cfg_addr, bus->number,
	397	PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
	398	return PCIBIOS_SUCCESSFUL;
	399	}
	400
	401	static struct pci_ops scc_pciex_pci_ops = {
453c02c2 RH	402	.read = scc_pciex_read_config,
453c02c2 RH	403	.write = scc_pciex_write_config,
884d04cd IK	404	};
884d04cd IK	405
24caa6a0	406	static void pciex_clear_intr_all(unsigned int __iomem *base)
884d04cd IK	407	{
	408	PEX_OUT(base, PEXAERRSTS, 0xffffffff);
	409	PEX_OUT(base, PEXPRERRSTS, 0xffffffff);
	410	PEX_OUT(base, PEXINTSTS, 0xffffffff);
	411	}
	412
	413	#if 0
	414	static void pciex_disable_intr_all(unsigned int *base)
	415	{
	416	PEX_OUT(base, PEXINTMASK, 0x0);
	417	PEX_OUT(base, PEXAERRMASK, 0x0);
	418	PEX_OUT(base, PEXPRERRMASK, 0x0);
	419	PEX_OUT(base, PEXVDMASK, 0x0);
	420	}
	421	#endif
	422
24caa6a0	423	static void pciex_enable_intr_all(unsigned int __iomem *base)
884d04cd IK	424	{
	425	PEX_OUT(base, PEXINTMASK, 0x0000e7f1);
	426	PEX_OUT(base, PEXAERRMASK, 0x03ff01ff);
	427	PEX_OUT(base, PEXPRERRMASK, 0x0001010f);
	428	PEX_OUT(base, PEXVDMASK, 0x00000001);
	429	}
	430
24caa6a0	431	static void pciex_check_status(unsigned int __iomem *base)
884d04cd IK	432	{
	433	uint32_t err = 0;
	434	uint32_t intsts, aerr, prerr, rcvcp, lenerr;
	435	uint32_t maea, maec;
	436
	437	intsts = PEX_IN(base, PEXINTSTS);
	438	aerr = PEX_IN(base, PEXAERRSTS);
	439	prerr = PEX_IN(base, PEXPRERRSTS);
	440	rcvcp = PEX_IN(base, PEXRCVCPLIDA);
	441	lenerr = PEX_IN(base, PEXLENERRIDA);
	442
	443	if (intsts \|\| aerr \|\| prerr \|\| rcvcp \|\| lenerr)
	444	err = 1;
	445
	446	pr_info("PCEXC interrupt!!\n");
	447	pr_info("PEXINTSTS :0x%08x\n", intsts);
	448	pr_info("PEXAERRSTS :0x%08x\n", aerr);
	449	pr_info("PEXPRERRSTS :0x%08x\n", prerr);
	450	pr_info("PEXRCVCPLIDA :0x%08x\n", rcvcp);
	451	pr_info("PEXLENERRIDA :0x%08x\n", lenerr);
	452
	453	/* print detail of Protection Error */
	454	if (intsts & 0x00004000) {
	455	uint32_t i, n;
	456	for (i = 0; i < 4; i++) {
	457	n = 1 << i;
	458	if (prerr & n) {
	459	maea = PEX_IN(base, PEXMAEA(i));
	460	maec = PEX_IN(base, PEXMAEC(i));
	461	pr_info("PEXMAEC%d :0x%08x\n", i, maec);
	462	pr_info("PEXMAEA%d :0x%08x\n", i, maea);
	463	}
	464	}
	465	}
	466
	467	if (err)
	468	pciex_clear_intr_all(base);
	469	}
	470
	471	static irqreturn_t pciex_handle_internal_irq(int irq, void *dev_id)
	472	{
	473	struct pci_controller *phb = dev_id;
	474
	475	pr_debug("PCIEX:pciex_handle_internal_irq(irq=%d)\n", irq);
	476
	477	BUG_ON(phb->cfg_addr == NULL);
	478
	479	pciex_check_status(phb->cfg_addr);
	480
	481	return IRQ_HANDLED;
	482	}
	483
	484	static __init int celleb_setup_pciex(struct device_node *node,
	485	struct pci_controller *phb)
	486	{
	487	struct resource r;
884d04cd IK	488	int virq;
	489
	490	/* SMMIO registers; used inside this file */
	491	if (of_address_to_resource(node, 0, &r)) {
	492	pr_err("PCIEXC:Failed to get config resource.\n");
	493	return 1;
	494	}
28f65c11	495	phb->cfg_addr = ioremap(r.start, resource_size(&r));
884d04cd IK	496	if (!phb->cfg_addr) {
	497	pr_err("PCIEXC:Failed to remap SMMIO region.\n");
	498	return 1;
	499	}
	500
	501	/* Not use cfg_data, cmd and data regs are near address reg */
	502	phb->cfg_data = NULL;
	503
	504	/* set pci_ops */
	505	phb->ops = &scc_pciex_pci_ops;
	506
	507	/* internal interrupt handler */
f7578496 TR	508	virq = irq_of_parse_and_map(node, 1);
f7578496 TR	509	if (!virq) {
884d04cd IK	510	pr_err("PCIEXC:Failed to map irq\n");
	511	goto error;
	512	}
884d04cd	513	if (request_irq(virq, pciex_handle_internal_irq,
a3a9f3b4	514	0, "pciex", (void *)phb)) {
884d04cd IK	515	pr_err("PCIEXC:Failed to request irq\n");
	516	goto error;
	517	}
	518
	519	/* enable all interrupts */
	520	pciex_clear_intr_all(phb->cfg_addr);
	521	pciex_enable_intr_all(phb->cfg_addr);
	522	/* MSI: TBD */
	523
	524	return 0;
	525
	526	error:
	527	phb->cfg_data = NULL;
	528	if (phb->cfg_addr)
	529	iounmap(phb->cfg_addr);
	530	phb->cfg_addr = NULL;
	531	return 1;
	532	}
	533
	534	struct celleb_phb_spec celleb_pciex_spec __initdata = {
	535	.setup = celleb_setup_pciex,
	536	.ops = &scc_pciex_ops,
	537	.iowa_init = &scc_pciex_iowa_init,
	538	};