[linux-2.6-block.git] / arch / powerpc / platforms / cell / axon_msi.c

/*
 * Copyright 2007, Michael Ellerman, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */


#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/export.h>
#include <linux/of_platform.h>
#include <linux/debugfs.h>
#include <linux/slab.h>

#include <asm/dcr.h>
#include <asm/machdep.h>
#include <asm/prom.h>

#include "cell.h"

/*
 * MSIC registers, specified as offsets from dcr_base
 */
#define MSIC_CTRL_REG	0x0

/* Base Address registers specify FIFO location in BE memory */
#define MSIC_BASE_ADDR_HI_REG	0x3
#define MSIC_BASE_ADDR_LO_REG	0x4

/* Hold the read/write offsets into the FIFO */
#define MSIC_READ_OFFSET_REG	0x5
#define MSIC_WRITE_OFFSET_REG	0x6


/* MSIC control register flags */
#define MSIC_CTRL_ENABLE		0x0001
#define MSIC_CTRL_FIFO_FULL_ENABLE	0x0002
#define MSIC_CTRL_IRQ_ENABLE		0x0008
#define MSIC_CTRL_FULL_STOP_ENABLE	0x0010

/*
 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
 * Currently we're using a 64KB FIFO size.
 */
#define MSIC_FIFO_SIZE_SHIFT	16
#define MSIC_FIFO_SIZE_BYTES	(1 << MSIC_FIFO_SIZE_SHIFT)

/*
 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
 * 8-9 of the MSIC control reg.
 */
#define MSIC_CTRL_FIFO_SIZE	(((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)

/*
 * We need to mask the read/write offsets to make sure they stay within
 * the bounds of the FIFO. Also they should always be 16-byte aligned.
 */
#define MSIC_FIFO_SIZE_MASK	((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)

/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
#define MSIC_FIFO_ENTRY_SIZE	0x10


struct axon_msic {
	struct irq_domain *irq_domain;
	__le32 *fifo_virt;
	dma_addr_t fifo_phys;
	dcr_host_t dcr_host;
	u32 read_offset;
#ifdef DEBUG
	u32 __iomem *trigger;
#endif
};

#ifdef DEBUG
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
#else
static inline void axon_msi_debug_setup(struct device_node *dn,
					struct axon_msic *msic) { }
#endif


static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
{
	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);

	dcr_write(msic->dcr_host, dcr_n, val);
}

static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct axon_msic *msic = irq_desc_get_handler_data(desc);
	u32 write_offset, msi;
	int idx;
	int retry = 0;

	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);

	/* write_offset doesn't wrap properly, so we have to mask it */
	write_offset &= MSIC_FIFO_SIZE_MASK;

	while (msic->read_offset != write_offset && retry < 100) {
		idx  = msic->read_offset / sizeof(__le32);
		msi  = le32_to_cpu(msic->fifo_virt[idx]);
		msi &= 0xFFFF;

		pr_devel("axon_msi: woff %x roff %x msi %x\n",
			  write_offset, msic->read_offset, msi);

		if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
			generic_handle_irq(msi);
			msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
		} else {
			/*
			 * Reading the MSIC_WRITE_OFFSET_REG does not
			 * reliably flush the outstanding DMA to the
			 * FIFO buffer. Here we were reading stale
			 * data, so we need to retry.
			 */
			udelay(1);
			retry++;
			pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
			continue;
		}

		if (retry) {
			pr_devel("axon_msi: late irq 0x%x, retry %d\n",
				 msi, retry);
			retry = 0;
		}

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	if (retry) {
		printk(KERN_WARNING "axon_msi: irq timed out\n");

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	chip->irq_eoi(&desc->irq_data);
}

static struct axon_msic *find_msi_translator(struct pci_dev *dev)
{
	struct irq_domain *irq_domain;
	struct device_node *dn, *tmp;
	const phandle *ph;
	struct axon_msic *msic = NULL;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return NULL;
	}

	for (; dn; dn = of_get_next_parent(dn)) {
		ph = of_get_property(dn, "msi-translator", NULL);
		if (ph)
			break;
	}

	if (!ph) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-translator property found\n");
		goto out_error;
	}

	tmp = dn;
	dn = of_find_node_by_phandle(*ph);
	of_node_put(tmp);
	if (!dn) {
		dev_dbg(&dev->dev,
			"axon_msi: msi-translator doesn't point to a node\n");
		goto out_error;
	}

	irq_domain = irq_find_host(dn);
	if (!irq_domain) {
		dev_dbg(&dev->dev, "axon_msi: no irq_domain found for node %s\n",
			dn->full_name);
		goto out_error;
	}

	msic = irq_domain->host_data;

out_error:
	of_node_put(dn);

	return msic;
}

static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
{
	struct device_node *dn;
	struct msi_desc *entry;
	int len;
	const u32 *prop;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return -ENODEV;
	}

	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);

	for (; dn; dn = of_get_next_parent(dn)) {
		if (entry->msi_attrib.is_64) {
			prop = of_get_property(dn, "msi-address-64", &len);
			if (prop)
				break;
		}

		prop = of_get_property(dn, "msi-address-32", &len);
		if (prop)
			break;
	}

	if (!prop) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-address-(32|64) properties found\n");
		return -ENOENT;
	}

	switch (len) {
	case 8:
		msg->address_hi = prop[0];
		msg->address_lo = prop[1];
		break;
	case 4:
		msg->address_hi = 0;
		msg->address_lo = prop[0];
		break;
	default:
		dev_dbg(&dev->dev,
			"axon_msi: malformed msi-address-(32|64) property\n");
		of_node_put(dn);
		return -EINVAL;
	}

	of_node_put(dn);

	return 0;
}

static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	unsigned int virq, rc;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct axon_msic *msic;

	msic = find_msi_translator(dev);
	if (!msic)
		return -ENODEV;

	rc = setup_msi_msg_address(dev, &msg);
	if (rc)
		return rc;

	list_for_each_entry(entry, &dev->msi_list, list) {
		virq = irq_create_direct_mapping(msic->irq_domain);
		if (virq == NO_IRQ) {
			dev_warn(&dev->dev,
				 "axon_msi: virq allocation failed!\n");
			return -1;
		}
		dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);

		irq_set_msi_desc(virq, entry);
		msg.data = virq;
		pci_write_msi_msg(virq, &msg);
	}

	return 0;
}

static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
{
	struct msi_desc *entry;

	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");

	list_for_each_entry(entry, &dev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;

		irq_set_msi_desc(entry->irq, NULL);
		irq_dispose_mapping(entry->irq);
	}
}

static struct irq_chip msic_irq_chip = {
	.irq_mask	= pci_msi_mask_irq,
	.irq_unmask	= pci_msi_unmask_irq,
	.irq_shutdown	= pci_msi_mask_irq,
	.name		= "AXON-MSI",
};

static int msic_host_map(struct irq_domain *h, unsigned int virq,
			 irq_hw_number_t hw)
{
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);

	return 0;
}

static const struct irq_domain_ops msic_host_ops = {
	.map	= msic_host_map,
};

static void axon_msi_shutdown(struct platform_device *device)
{
	struct axon_msic *msic = dev_get_drvdata(&device->dev);
	u32 tmp;

	pr_devel("axon_msi: disabling %s\n",
		  msic->irq_domain->of_node->full_name);
	tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
}

static int axon_msi_probe(struct platform_device *device)
{
	struct device_node *dn = device->dev.of_node;
	struct axon_msic *msic;
	unsigned int virq;
	int dcr_base, dcr_len;

	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);

	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	if (!msic) {
		printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
		       dn->full_name);
		goto out;
	}

	dcr_base = dcr_resource_start(dn, 0);
	dcr_len = dcr_resource_len(dn, 0);

	if (dcr_base == 0 || dcr_len == 0) {
		printk(KERN_ERR
		       "axon_msi: couldn't parse dcr properties on %s\n",
			dn->full_name);
		goto out_free_msic;
	}

	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
	if (!DCR_MAP_OK(msic->dcr_host)) {
		printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
					     &msic->fifo_phys, GFP_KERNEL);
	if (!msic->fifo_virt) {
		printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	virq = irq_of_parse_and_map(dn, 0);
	if (virq == NO_IRQ) {
		printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}
	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);

	/* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
	msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
	if (!msic->irq_domain) {
		printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}

	irq_set_handler_data(virq, msic);
	irq_set_chained_handler(virq, axon_msi_cascade);
	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);

	/* Enable the MSIC hardware */
	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
				  msic->fifo_phys & 0xFFFFFFFF);
	msic_dcr_write(msic, MSIC_CTRL_REG,
			MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
			MSIC_CTRL_FIFO_SIZE);

	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
				& MSIC_FIFO_SIZE_MASK;

	dev_set_drvdata(&device->dev, msic);

	cell_pci_controller_ops.setup_msi_irqs = axon_msi_setup_msi_irqs;
	cell_pci_controller_ops.teardown_msi_irqs = axon_msi_teardown_msi_irqs;

	axon_msi_debug_setup(dn, msic);

	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);

	return 0;

out_free_fifo:
	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
			  msic->fifo_phys);
out_free_msic:
	kfree(msic);
out:

	return -1;
}

static const struct of_device_id axon_msi_device_id[] = {
	{
		.compatible	= "ibm,axon-msic"
	},
	{}
};

static struct platform_driver axon_msi_driver = {
	.probe		= axon_msi_probe,
	.shutdown	= axon_msi_shutdown,
	.driver = {
		.name = "axon-msi",
		.of_match_table = axon_msi_device_id,
	},
};

static int __init axon_msi_init(void)
{
	return platform_driver_register(&axon_msi_driver);
}
subsys_initcall(axon_msi_init);


#ifdef DEBUG
static int msic_set(void *data, u64 val)
{
	struct axon_msic *msic = data;
	out_le32(msic->trigger, val);
	return 0;
}

static int msic_get(void *data, u64 *val)
{
	*val = 0;
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");

void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
{
	char name[8];
	u64 addr;

	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	if (addr == OF_BAD_ADDR) {
		pr_devel("axon_msi: couldn't translate reg property\n");
		return;
	}

	msic->trigger = ioremap(addr, 0x4);
	if (!msic->trigger) {
		pr_devel("axon_msi: ioremap failed\n");
		return;
	}

	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));

	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
				 msic, &fops_msic)) {
		pr_devel("axon_msi: debugfs_create_file failed!\n");
		return;
	}
}
#endif /* DEBUG */
Commit	Line	Data
ce21b3c9 ME	1	/*
	2	* Copyright 2007, Michael Ellerman, IBM Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/msi.h>
66b15db6	16	#include <linux/export.h>
e4347dfb	17	#include <linux/of_platform.h>
72cac213	18	#include <linux/debugfs.h>
5a0e3ad6	19	#include <linux/slab.h>
ce21b3c9 ME	20
	21	#include <asm/dcr.h>
	22	#include <asm/machdep.h>
	23	#include <asm/prom.h>
	24
7e3d6c5a	25	#include "cell.h"
ce21b3c9 ME	26
	27	/*
	28	* MSIC registers, specified as offsets from dcr_base
	29	*/
	30	#define MSIC_CTRL_REG 0x0
	31
	32	/* Base Address registers specify FIFO location in BE memory */
	33	#define MSIC_BASE_ADDR_HI_REG 0x3
	34	#define MSIC_BASE_ADDR_LO_REG 0x4
	35
	36	/* Hold the read/write offsets into the FIFO */
	37	#define MSIC_READ_OFFSET_REG 0x5
	38	#define MSIC_WRITE_OFFSET_REG 0x6
	39
	40
	41	/* MSIC control register flags */
	42	#define MSIC_CTRL_ENABLE 0x0001
	43	#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
	44	#define MSIC_CTRL_IRQ_ENABLE 0x0008
	45	#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
	46
	47	/*
	48	* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
	49	* Currently we're using a 64KB FIFO size.
	50	*/
	51	#define MSIC_FIFO_SIZE_SHIFT 16
	52	#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
	53
	54	/*
	55	* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
	56	* 8-9 of the MSIC control reg.
	57	*/
	58	#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
	59
	60	/*
	61	* We need to mask the read/write offsets to make sure they stay within
	62	* the bounds of the FIFO. Also they should always be 16-byte aligned.
	63	*/
	64	#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
	65
	66	/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
	67	#define MSIC_FIFO_ENTRY_SIZE 0x10
	68
	69
	70	struct axon_msic {
bae1d8f1	71	struct irq_domain *irq_domain;
de4c928b ME	72	__le32 *fifo_virt;
de4c928b ME	73	dma_addr_t fifo_phys;
ce21b3c9	74	dcr_host_t dcr_host;
ce21b3c9	75	u32 read_offset;
72cac213 ME	76	#ifdef DEBUG
	77	u32 __iomem *trigger;
	78	#endif
ce21b3c9 ME	79	};
ce21b3c9 ME	80
72cac213 ME	81	#ifdef DEBUG
	82	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic);
	83	#else
	84	static inline void axon_msi_debug_setup(struct device_node *dn,
	85	struct axon_msic *msic) { }
	86	#endif
	87
	88
ce21b3c9 ME	89	static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
ce21b3c9 ME	90	{
33875f03	91	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
ce21b3c9	92
83f34df4	93	dcr_write(msic->dcr_host, dcr_n, val);
ce21b3c9 ME	94	}
ce21b3c9 ME	95
ce21b3c9 ME	96	static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
ce21b3c9 ME	97	{
ec775d0e	98	struct irq_chip *chip = irq_desc_get_chip(desc);
c1231a78	99	struct axon_msic *msic = irq_desc_get_handler_data(desc);
ce21b3c9 ME	100	u32 write_offset, msi;
ce21b3c9 ME	101	int idx;
d015fe99	102	int retry = 0;
ce21b3c9	103
2843e7f7	104	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
33875f03	105	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
ce21b3c9 ME	106
	107	/* write_offset doesn't wrap properly, so we have to mask it */
	108	write_offset &= MSIC_FIFO_SIZE_MASK;
	109
d015fe99	110	while (msic->read_offset != write_offset && retry < 100) {
ce21b3c9	111	idx = msic->read_offset / sizeof(__le32);
de4c928b	112	msi = le32_to_cpu(msic->fifo_virt[idx]);
ce21b3c9 ME	113	msi &= 0xFFFF;
ce21b3c9 ME	114
33875f03	115	pr_devel("axon_msi: woff %x roff %x msi %x\n",
ce21b3c9 ME	116	write_offset, msic->read_offset, msi);
ce21b3c9 ME	117
4013369f	118	if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
d015fe99 AB	119	generic_handle_irq(msi);
	120	msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
	121	} else {
	122	/*
	123	* Reading the MSIC_WRITE_OFFSET_REG does not
	124	* reliably flush the outstanding DMA to the
	125	* FIFO buffer. Here we were reading stale
	126	* data, so we need to retry.
	127	*/
	128	udelay(1);
	129	retry++;
33875f03	130	pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
d015fe99 AB	131	continue;
	132	}
	133
	134	if (retry) {
33875f03	135	pr_devel("axon_msi: late irq 0x%x, retry %d\n",
d015fe99 AB	136	msi, retry);
	137	retry = 0;
	138	}
	139
ce21b3c9 ME	140	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
ce21b3c9 ME	141	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
d015fe99	142	}
ce21b3c9	143
d015fe99 AB	144	if (retry) {
	145	printk(KERN_WARNING "axon_msi: irq timed out\n");
	146
	147	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
	148	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
ce21b3c9 ME	149	}
ce21b3c9 ME	150
d1ae63d4	151	chip->irq_eoi(&desc->irq_data);
ce21b3c9 ME	152	}
	153
	154	static struct axon_msic find_msi_translator(struct pci_dev dev)
	155	{
bae1d8f1	156	struct irq_domain *irq_domain;
ce21b3c9 ME	157	struct device_node dn, tmp;
	158	const phandle *ph;
	159	struct axon_msic *msic = NULL;
	160
db220b23	161	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	162	if (!dn) {
	163	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	164	return NULL;
	165	}
	166
988479eb	167	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	168	ph = of_get_property(dn, "msi-translator", NULL);
	169	if (ph)
	170	break;
	171	}
	172
	173	if (!ph) {
	174	dev_dbg(&dev->dev,
	175	"axon_msi: no msi-translator property found\n");
	176	goto out_error;
	177	}
	178
	179	tmp = dn;
	180	dn = of_find_node_by_phandle(*ph);
c6d01179	181	of_node_put(tmp);
ce21b3c9 ME	182	if (!dn) {
	183	dev_dbg(&dev->dev,
	184	"axon_msi: msi-translator doesn't point to a node\n");
	185	goto out_error;
	186	}
	187
bae1d8f1 GL	188	irq_domain = irq_find_host(dn);
	189	if (!irq_domain) {
	190	dev_dbg(&dev->dev, "axon_msi: no irq_domain found for node %s\n",
ce21b3c9 ME	191	dn->full_name);
	192	goto out_error;
	193	}
	194
bae1d8f1	195	msic = irq_domain->host_data;
ce21b3c9 ME	196
	197	out_error:
	198	of_node_put(dn);
ce21b3c9 ME	199
	200	return msic;
	201	}
	202
ce21b3c9 ME	203	static int setup_msi_msg_address(struct pci_dev dev, struct msi_msg msg)
ce21b3c9 ME	204	{
988479eb	205	struct device_node *dn;
ce21b3c9 ME	206	struct msi_desc *entry;
	207	int len;
	208	const u32 *prop;
	209
db220b23	210	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	211	if (!dn) {
	212	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	213	return -ENODEV;
	214	}
	215
	216	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
	217
988479eb	218	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	219	if (entry->msi_attrib.is_64) {
	220	prop = of_get_property(dn, "msi-address-64", &len);
	221	if (prop)
	222	break;
	223	}
	224
	225	prop = of_get_property(dn, "msi-address-32", &len);
	226	if (prop)
	227	break;
	228	}
	229
	230	if (!prop) {
	231	dev_dbg(&dev->dev,
	232	"axon_msi: no msi-address-(32\|64) properties found\n");
	233	return -ENOENT;
	234	}
	235
	236	switch (len) {
	237	case 8:
	238	msg->address_hi = prop[0];
	239	msg->address_lo = prop[1];
	240	break;
	241	case 4:
	242	msg->address_hi = 0;
	243	msg->address_lo = prop[0];
	244	break;
	245	default:
	246	dev_dbg(&dev->dev,
	247	"axon_msi: malformed msi-address-(32\|64) property\n");
	248	of_node_put(dn);
	249	return -EINVAL;
	250	}
	251
	252	of_node_put(dn);
	253
	254	return 0;
	255	}
	256
	257	static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	258	{
	259	unsigned int virq, rc;
	260	struct msi_desc *entry;
	261	struct msi_msg msg;
	262	struct axon_msic *msic;
	263
	264	msic = find_msi_translator(dev);
	265	if (!msic)
	266	return -ENODEV;
	267
	268	rc = setup_msi_msg_address(dev, &msg);
	269	if (rc)
	270	return rc;
	271
ce21b3c9	272	list_for_each_entry(entry, &dev->msi_list, list) {
bae1d8f1	273	virq = irq_create_direct_mapping(msic->irq_domain);
ce21b3c9 ME	274	if (virq == NO_IRQ) {
	275	dev_warn(&dev->dev,
	276	"axon_msi: virq allocation failed!\n");
	277	return -1;
	278	}
	279	dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
	280
ec775d0e	281	irq_set_msi_desc(virq, entry);
ce21b3c9	282	msg.data = virq;
83a18912	283	pci_write_msi_msg(virq, &msg);
ce21b3c9 ME	284	}
	285
	286	return 0;
	287	}
	288
	289	static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
	290	{
	291	struct msi_desc *entry;
	292
	293	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
	294
	295	list_for_each_entry(entry, &dev->msi_list, list) {
	296	if (entry->irq == NO_IRQ)
	297	continue;
	298
ec775d0e	299	irq_set_msi_desc(entry->irq, NULL);
ce21b3c9 ME	300	irq_dispose_mapping(entry->irq);
	301	}
	302	}
	303
	304	static struct irq_chip msic_irq_chip = {
280510f1 TG	305	.irq_mask = pci_msi_mask_irq,
	306	.irq_unmask = pci_msi_unmask_irq,
	307	.irq_shutdown = pci_msi_mask_irq,
b27df672	308	.name = "AXON-MSI",
ce21b3c9 ME	309	};
ce21b3c9 ME	310
bae1d8f1	311	static int msic_host_map(struct irq_domain *h, unsigned int virq,
ce21b3c9 ME	312	irq_hw_number_t hw)
ce21b3c9 ME	313	{
95533614	314	irq_set_chip_data(virq, h->host_data);
ec775d0e	315	irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
ce21b3c9 ME	316
	317	return 0;
	318	}
	319
9f70b8eb	320	static const struct irq_domain_ops msic_host_ops = {
ce21b3c9 ME	321	.map = msic_host_map,
	322	};
	323
00006124	324	static void axon_msi_shutdown(struct platform_device *device)
ce21b3c9	325	{
86c27656	326	struct axon_msic *msic = dev_get_drvdata(&device->dev);
ce21b3c9 ME	327	u32 tmp;
ce21b3c9 ME	328
33875f03	329	pr_devel("axon_msi: disabling %s\n",
bae1d8f1	330	msic->irq_domain->of_node->full_name);
e4347dfb ME	331	tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	332	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	333	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
ce21b3c9 ME	334	}
ce21b3c9 ME	335
00006124	336	static int axon_msi_probe(struct platform_device *device)
ce21b3c9	337	{
61c7a080	338	struct device_node *dn = device->dev.of_node;
ce21b3c9 ME	339	struct axon_msic *msic;
ce21b3c9 ME	340	unsigned int virq;
4acb8896	341	int dcr_base, dcr_len;
ce21b3c9	342
33875f03	343	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
ce21b3c9 ME	344
	345	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	346	if (!msic) {
	347	printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
	348	dn->full_name);
	349	goto out;
	350	}
	351
4acb8896	352	dcr_base = dcr_resource_start(dn, 0);
ce21b3c9 ME	353	dcr_len = dcr_resource_len(dn, 0);
ce21b3c9 ME	354
4acb8896	355	if (dcr_base == 0 \|\| dcr_len == 0) {
ce21b3c9 ME	356	printk(KERN_ERR
	357	"axon_msi: couldn't parse dcr properties on %s\n",
	358	dn->full_name);
aee7a283	359	goto out_free_msic;
ce21b3c9 ME	360	}
ce21b3c9 ME	361
4acb8896	362	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
ce21b3c9 ME	363	if (!DCR_MAP_OK(msic->dcr_host)) {
	364	printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
	365	dn->full_name);
	366	goto out_free_msic;
	367	}
	368
de4c928b ME	369	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
	370	&msic->fifo_phys, GFP_KERNEL);
	371	if (!msic->fifo_virt) {
ce21b3c9 ME	372	printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
	373	dn->full_name);
	374	goto out_free_msic;
	375	}
	376
997526db ME	377	virq = irq_of_parse_and_map(dn, 0);
	378	if (virq == NO_IRQ) {
	379	printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
	380	dn->full_name);
	381	goto out_free_fifo;
	382	}
d015fe99	383	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
997526db	384
4013369f GL	385	/* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
4013369f GL	386	msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
bae1d8f1 GL	387	if (!msic->irq_domain) {
bae1d8f1 GL	388	printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
ce21b3c9 ME	389	dn->full_name);
	390	goto out_free_fifo;
	391	}
	392
ec775d0e TG	393	irq_set_handler_data(virq, msic);
ec775d0e TG	394	irq_set_chained_handler(virq, axon_msi_cascade);
33875f03	395	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
ce21b3c9 ME	396
ce21b3c9 ME	397	/* Enable the MSIC hardware */
de4c928b	398	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
ce21b3c9	399	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
de4c928b	400	msic->fifo_phys & 0xFFFFFFFF);
ce21b3c9 ME	401	msic_dcr_write(msic, MSIC_CTRL_REG,
	402	MSIC_CTRL_IRQ_ENABLE \| MSIC_CTRL_ENABLE \|
	403	MSIC_CTRL_FIFO_SIZE);
	404
23e0e8af AB	405	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
	406	& MSIC_FIFO_SIZE_MASK;
	407
86c27656	408	dev_set_drvdata(&device->dev, msic);
e4347dfb	409
7e3d6c5a DA	410	cell_pci_controller_ops.setup_msi_irqs = axon_msi_setup_msi_irqs;
7e3d6c5a DA	411	cell_pci_controller_ops.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
ce21b3c9	412
72cac213 ME	413	axon_msi_debug_setup(dn, msic);
72cac213 ME	414
ce21b3c9 ME	415	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
	416
	417	return 0;
	418
ce21b3c9	419	out_free_fifo:
de4c928b ME	420	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
de4c928b ME	421	msic->fifo_phys);
ce21b3c9 ME	422	out_free_msic:
	423	kfree(msic);
	424	out:
	425
	426	return -1;
	427	}
	428
e4347dfb ME	429	static const struct of_device_id axon_msi_device_id[] = {
	430	{
	431	.compatible = "ibm,axon-msic"
	432	},
	433	{}
	434	};
ce21b3c9	435
00006124	436	static struct platform_driver axon_msi_driver = {
e4347dfb ME	437	.probe = axon_msi_probe,
e4347dfb ME	438	.shutdown = axon_msi_shutdown,
4018294b GL	439	.driver = {
4018294b GL	440	.name = "axon-msi",
4018294b	441	.of_match_table = axon_msi_device_id,
e4347dfb ME	442	},
e4347dfb ME	443	};
ce21b3c9	444
e4347dfb ME	445	static int __init axon_msi_init(void)
e4347dfb ME	446	{
00006124	447	return platform_driver_register(&axon_msi_driver);
ce21b3c9	448	}
e4347dfb	449	subsys_initcall(axon_msi_init);
72cac213 ME	450
	451
	452	#ifdef DEBUG
	453	static int msic_set(void *data, u64 val)
	454	{
	455	struct axon_msic *msic = data;
	456	out_le32(msic->trigger, val);
	457	return 0;
	458	}
	459
	460	static int msic_get(void data, u64 val)
	461	{
	462	*val = 0;
	463	return 0;
	464	}
	465
	466	DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
	467
	468	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic)
	469	{
	470	char name[8];
	471	u64 addr;
	472
	473	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	474	if (addr == OF_BAD_ADDR) {
33875f03	475	pr_devel("axon_msi: couldn't translate reg property\n");
72cac213 ME	476	return;
	477	}
	478
	479	msic->trigger = ioremap(addr, 0x4);
	480	if (!msic->trigger) {
33875f03	481	pr_devel("axon_msi: ioremap failed\n");
72cac213 ME	482	return;
	483	}
	484
	485	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
	486
	487	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
	488	msic, &fops_msic)) {
33875f03	489	pr_devel("axon_msi: debugfs_create_file failed!\n");
72cac213 ME	490	return;
	491	}
	492	}
	493	#endif /* DEBUG */