[linux-2.6-block.git] / arch / powerpc / platforms / cell / axon_msi.c

/*
 * Copyright 2007, Michael Ellerman, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */


#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/export.h>
#include <linux/of_platform.h>
#include <linux/debugfs.h>
#include <linux/slab.h>

#include <asm/dcr.h>
#include <asm/machdep.h>
#include <asm/prom.h>


/*
 * MSIC registers, specified as offsets from dcr_base
 */
#define MSIC_CTRL_REG	0x0

/* Base Address registers specify FIFO location in BE memory */
#define MSIC_BASE_ADDR_HI_REG	0x3
#define MSIC_BASE_ADDR_LO_REG	0x4

/* Hold the read/write offsets into the FIFO */
#define MSIC_READ_OFFSET_REG	0x5
#define MSIC_WRITE_OFFSET_REG	0x6


/* MSIC control register flags */
#define MSIC_CTRL_ENABLE		0x0001
#define MSIC_CTRL_FIFO_FULL_ENABLE	0x0002
#define MSIC_CTRL_IRQ_ENABLE		0x0008
#define MSIC_CTRL_FULL_STOP_ENABLE	0x0010

/*
 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
 * Currently we're using a 64KB FIFO size.
 */
#define MSIC_FIFO_SIZE_SHIFT	16
#define MSIC_FIFO_SIZE_BYTES	(1 << MSIC_FIFO_SIZE_SHIFT)

/*
 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
 * 8-9 of the MSIC control reg.
 */
#define MSIC_CTRL_FIFO_SIZE	(((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)

/*
 * We need to mask the read/write offsets to make sure they stay within
 * the bounds of the FIFO. Also they should always be 16-byte aligned.
 */
#define MSIC_FIFO_SIZE_MASK	((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)

/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
#define MSIC_FIFO_ENTRY_SIZE	0x10


struct axon_msic {
	struct irq_domain *irq_domain;
	__le32 *fifo_virt;
	dma_addr_t fifo_phys;
	dcr_host_t dcr_host;
	u32 read_offset;
#ifdef DEBUG
	u32 __iomem *trigger;
#endif
};

#ifdef DEBUG
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
#else
static inline void axon_msi_debug_setup(struct device_node *dn,
					struct axon_msic *msic) { }
#endif


static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
{
	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);

	dcr_write(msic->dcr_host, dcr_n, val);
}

static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct axon_msic *msic = irq_get_handler_data(irq);
	u32 write_offset, msi;
	int idx;
	int retry = 0;

	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);

	/* write_offset doesn't wrap properly, so we have to mask it */
	write_offset &= MSIC_FIFO_SIZE_MASK;

	while (msic->read_offset != write_offset && retry < 100) {
		idx  = msic->read_offset / sizeof(__le32);
		msi  = le32_to_cpu(msic->fifo_virt[idx]);
		msi &= 0xFFFF;

		pr_devel("axon_msi: woff %x roff %x msi %x\n",
			  write_offset, msic->read_offset, msi);

		if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
			generic_handle_irq(msi);
			msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
		} else {
			/*
			 * Reading the MSIC_WRITE_OFFSET_REG does not
			 * reliably flush the outstanding DMA to the
			 * FIFO buffer. Here we were reading stale
			 * data, so we need to retry.
			 */
			udelay(1);
			retry++;
			pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
			continue;
		}

		if (retry) {
			pr_devel("axon_msi: late irq 0x%x, retry %d\n",
				 msi, retry);
			retry = 0;
		}

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	if (retry) {
		printk(KERN_WARNING "axon_msi: irq timed out\n");

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	chip->irq_eoi(&desc->irq_data);
}

static struct axon_msic *find_msi_translator(struct pci_dev *dev)
{
	struct irq_domain *irq_domain;
	struct device_node *dn, *tmp;
	const phandle *ph;
	struct axon_msic *msic = NULL;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return NULL;
	}

	for (; dn; dn = of_get_next_parent(dn)) {
		ph = of_get_property(dn, "msi-translator", NULL);
		if (ph)
			break;
	}

	if (!ph) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-translator property found\n");
		goto out_error;
	}

	tmp = dn;
	dn = of_find_node_by_phandle(*ph);
	of_node_put(tmp);
	if (!dn) {
		dev_dbg(&dev->dev,
			"axon_msi: msi-translator doesn't point to a node\n");
		goto out_error;
	}

	irq_domain = irq_find_host(dn);
	if (!irq_domain) {
		dev_dbg(&dev->dev, "axon_msi: no irq_domain found for node %s\n",
			dn->full_name);
		goto out_error;
	}

	msic = irq_domain->host_data;

out_error:
	of_node_put(dn);

	return msic;
}

static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
{
	if (!find_msi_translator(dev))
		return -ENODEV;

	return 0;
}

static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
{
	struct device_node *dn;
	struct msi_desc *entry;
	int len;
	const u32 *prop;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return -ENODEV;
	}

	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);

	for (; dn; dn = of_get_next_parent(dn)) {
		if (entry->msi_attrib.is_64) {
			prop = of_get_property(dn, "msi-address-64", &len);
			if (prop)
				break;
		}

		prop = of_get_property(dn, "msi-address-32", &len);
		if (prop)
			break;
	}

	if (!prop) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-address-(32|64) properties found\n");
		return -ENOENT;
	}

	switch (len) {
	case 8:
		msg->address_hi = prop[0];
		msg->address_lo = prop[1];
		break;
	case 4:
		msg->address_hi = 0;
		msg->address_lo = prop[0];
		break;
	default:
		dev_dbg(&dev->dev,
			"axon_msi: malformed msi-address-(32|64) property\n");
		of_node_put(dn);
		return -EINVAL;
	}

	of_node_put(dn);

	return 0;
}

static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	unsigned int virq, rc;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct axon_msic *msic;

	msic = find_msi_translator(dev);
	if (!msic)
		return -ENODEV;

	rc = setup_msi_msg_address(dev, &msg);
	if (rc)
		return rc;

	/* We rely on being able to stash a virq in a u16 */
	BUILD_BUG_ON(NR_IRQS > 65536);

	list_for_each_entry(entry, &dev->msi_list, list) {
		virq = irq_create_direct_mapping(msic->irq_domain);
		if (virq == NO_IRQ) {
			dev_warn(&dev->dev,
				 "axon_msi: virq allocation failed!\n");
			return -1;
		}
		dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);

		irq_set_msi_desc(virq, entry);
		msg.data = virq;
		write_msi_msg(virq, &msg);
	}

	return 0;
}

static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
{
	struct msi_desc *entry;

	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");

	list_for_each_entry(entry, &dev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;

		irq_set_msi_desc(entry->irq, NULL);
		irq_dispose_mapping(entry->irq);
	}
}

static struct irq_chip msic_irq_chip = {
	.irq_mask	= mask_msi_irq,
	.irq_unmask	= unmask_msi_irq,
	.irq_shutdown	= mask_msi_irq,
	.name		= "AXON-MSI",
};

static int msic_host_map(struct irq_domain *h, unsigned int virq,
			 irq_hw_number_t hw)
{
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);

	return 0;
}

static struct irq_domain_ops msic_host_ops = {
	.map	= msic_host_map,
};

static void axon_msi_shutdown(struct platform_device *device)
{
	struct axon_msic *msic = dev_get_drvdata(&device->dev);
	u32 tmp;

	pr_devel("axon_msi: disabling %s\n",
		  msic->irq_domain->of_node->full_name);
	tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
}

static int axon_msi_probe(struct platform_device *device)
{
	struct device_node *dn = device->dev.of_node;
	struct axon_msic *msic;
	unsigned int virq;
	int dcr_base, dcr_len;

	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);

	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	if (!msic) {
		printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
		       dn->full_name);
		goto out;
	}

	dcr_base = dcr_resource_start(dn, 0);
	dcr_len = dcr_resource_len(dn, 0);

	if (dcr_base == 0 || dcr_len == 0) {
		printk(KERN_ERR
		       "axon_msi: couldn't parse dcr properties on %s\n",
			dn->full_name);
		goto out_free_msic;
	}

	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
	if (!DCR_MAP_OK(msic->dcr_host)) {
		printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
					     &msic->fifo_phys, GFP_KERNEL);
	if (!msic->fifo_virt) {
		printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	virq = irq_of_parse_and_map(dn, 0);
	if (virq == NO_IRQ) {
		printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}
	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);

	msic->irq_domain = irq_domain_add_nomap(dn, &msic_host_ops, msic);
	if (!msic->irq_domain) {
		printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}

	irq_set_handler_data(virq, msic);
	irq_set_chained_handler(virq, axon_msi_cascade);
	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);

	/* Enable the MSIC hardware */
	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
				  msic->fifo_phys & 0xFFFFFFFF);
	msic_dcr_write(msic, MSIC_CTRL_REG,
			MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
			MSIC_CTRL_FIFO_SIZE);

	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
				& MSIC_FIFO_SIZE_MASK;

	dev_set_drvdata(&device->dev, msic);

	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	ppc_md.msi_check_device = axon_msi_check_device;

	axon_msi_debug_setup(dn, msic);

	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);

	return 0;

out_free_fifo:
	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
			  msic->fifo_phys);
out_free_msic:
	kfree(msic);
out:

	return -1;
}

static const struct of_device_id axon_msi_device_id[] = {
	{
		.compatible	= "ibm,axon-msic"
	},
	{}
};

static struct platform_driver axon_msi_driver = {
	.probe		= axon_msi_probe,
	.shutdown	= axon_msi_shutdown,
	.driver = {
		.name = "axon-msi",
		.owner = THIS_MODULE,
		.of_match_table = axon_msi_device_id,
	},
};

static int __init axon_msi_init(void)
{
	return platform_driver_register(&axon_msi_driver);
}
subsys_initcall(axon_msi_init);


#ifdef DEBUG
static int msic_set(void *data, u64 val)
{
	struct axon_msic *msic = data;
	out_le32(msic->trigger, val);
	return 0;
}

static int msic_get(void *data, u64 *val)
{
	*val = 0;
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");

void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
{
	char name[8];
	u64 addr;

	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	if (addr == OF_BAD_ADDR) {
		pr_devel("axon_msi: couldn't translate reg property\n");
		return;
	}

	msic->trigger = ioremap(addr, 0x4);
	if (!msic->trigger) {
		pr_devel("axon_msi: ioremap failed\n");
		return;
	}

	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));

	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
				 msic, &fops_msic)) {
		pr_devel("axon_msi: debugfs_create_file failed!\n");
		return;
	}
}
#endif /* DEBUG */
Commit	Line	Data
ce21b3c9 ME	1	/*
	2	* Copyright 2007, Michael Ellerman, IBM Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/msi.h>
66b15db6	16	#include <linux/export.h>
e4347dfb	17	#include <linux/of_platform.h>
72cac213	18	#include <linux/debugfs.h>
5a0e3ad6	19	#include <linux/slab.h>
ce21b3c9 ME	20
	21	#include <asm/dcr.h>
	22	#include <asm/machdep.h>
	23	#include <asm/prom.h>
	24
	25
	26	/*
	27	* MSIC registers, specified as offsets from dcr_base
	28	*/
	29	#define MSIC_CTRL_REG 0x0
	30
	31	/* Base Address registers specify FIFO location in BE memory */
	32	#define MSIC_BASE_ADDR_HI_REG 0x3
	33	#define MSIC_BASE_ADDR_LO_REG 0x4
	34
	35	/* Hold the read/write offsets into the FIFO */
	36	#define MSIC_READ_OFFSET_REG 0x5
	37	#define MSIC_WRITE_OFFSET_REG 0x6
	38
	39
	40	/* MSIC control register flags */
	41	#define MSIC_CTRL_ENABLE 0x0001
	42	#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
	43	#define MSIC_CTRL_IRQ_ENABLE 0x0008
	44	#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
	45
	46	/*
	47	* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
	48	* Currently we're using a 64KB FIFO size.
	49	*/
	50	#define MSIC_FIFO_SIZE_SHIFT 16
	51	#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
	52
	53	/*
	54	* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
	55	* 8-9 of the MSIC control reg.
	56	*/
	57	#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
	58
	59	/*
	60	* We need to mask the read/write offsets to make sure they stay within
	61	* the bounds of the FIFO. Also they should always be 16-byte aligned.
	62	*/
	63	#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
	64
	65	/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
	66	#define MSIC_FIFO_ENTRY_SIZE 0x10
	67
	68
	69	struct axon_msic {
bae1d8f1	70	struct irq_domain *irq_domain;
de4c928b ME	71	__le32 *fifo_virt;
de4c928b ME	72	dma_addr_t fifo_phys;
ce21b3c9	73	dcr_host_t dcr_host;
ce21b3c9	74	u32 read_offset;
72cac213 ME	75	#ifdef DEBUG
	76	u32 __iomem *trigger;
	77	#endif
ce21b3c9 ME	78	};
ce21b3c9 ME	79
72cac213 ME	80	#ifdef DEBUG
	81	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic);
	82	#else
	83	static inline void axon_msi_debug_setup(struct device_node *dn,
	84	struct axon_msic *msic) { }
	85	#endif
	86
	87
ce21b3c9 ME	88	static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
ce21b3c9 ME	89	{
33875f03	90	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
ce21b3c9	91
83f34df4	92	dcr_write(msic->dcr_host, dcr_n, val);
ce21b3c9 ME	93	}
ce21b3c9 ME	94
ce21b3c9 ME	95	static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
ce21b3c9 ME	96	{
ec775d0e TG	97	struct irq_chip *chip = irq_desc_get_chip(desc);
ec775d0e TG	98	struct axon_msic *msic = irq_get_handler_data(irq);
ce21b3c9 ME	99	u32 write_offset, msi;
ce21b3c9 ME	100	int idx;
d015fe99	101	int retry = 0;
ce21b3c9	102
2843e7f7	103	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
33875f03	104	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
ce21b3c9 ME	105
	106	/* write_offset doesn't wrap properly, so we have to mask it */
	107	write_offset &= MSIC_FIFO_SIZE_MASK;
	108
d015fe99	109	while (msic->read_offset != write_offset && retry < 100) {
ce21b3c9	110	idx = msic->read_offset / sizeof(__le32);
de4c928b	111	msi = le32_to_cpu(msic->fifo_virt[idx]);
ce21b3c9 ME	112	msi &= 0xFFFF;
ce21b3c9 ME	113
33875f03	114	pr_devel("axon_msi: woff %x roff %x msi %x\n",
ce21b3c9 ME	115	write_offset, msic->read_offset, msi);
ce21b3c9 ME	116
95533614	117	if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
d015fe99 AB	118	generic_handle_irq(msi);
	119	msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
	120	} else {
	121	/*
	122	* Reading the MSIC_WRITE_OFFSET_REG does not
	123	* reliably flush the outstanding DMA to the
	124	* FIFO buffer. Here we were reading stale
	125	* data, so we need to retry.
	126	*/
	127	udelay(1);
	128	retry++;
33875f03	129	pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
d015fe99 AB	130	continue;
	131	}
	132
	133	if (retry) {
33875f03	134	pr_devel("axon_msi: late irq 0x%x, retry %d\n",
d015fe99 AB	135	msi, retry);
	136	retry = 0;
	137	}
	138
ce21b3c9 ME	139	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
ce21b3c9 ME	140	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
d015fe99	141	}
ce21b3c9	142
d015fe99 AB	143	if (retry) {
	144	printk(KERN_WARNING "axon_msi: irq timed out\n");
	145
	146	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
	147	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
ce21b3c9 ME	148	}
ce21b3c9 ME	149
d1ae63d4	150	chip->irq_eoi(&desc->irq_data);
ce21b3c9 ME	151	}
	152
	153	static struct axon_msic find_msi_translator(struct pci_dev dev)
	154	{
bae1d8f1	155	struct irq_domain *irq_domain;
ce21b3c9 ME	156	struct device_node dn, tmp;
	157	const phandle *ph;
	158	struct axon_msic *msic = NULL;
	159
db220b23	160	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	161	if (!dn) {
	162	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	163	return NULL;
	164	}
	165
988479eb	166	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	167	ph = of_get_property(dn, "msi-translator", NULL);
	168	if (ph)
	169	break;
	170	}
	171
	172	if (!ph) {
	173	dev_dbg(&dev->dev,
	174	"axon_msi: no msi-translator property found\n");
	175	goto out_error;
	176	}
	177
	178	tmp = dn;
	179	dn = of_find_node_by_phandle(*ph);
c6d01179	180	of_node_put(tmp);
ce21b3c9 ME	181	if (!dn) {
	182	dev_dbg(&dev->dev,
	183	"axon_msi: msi-translator doesn't point to a node\n");
	184	goto out_error;
	185	}
	186
bae1d8f1 GL	187	irq_domain = irq_find_host(dn);
	188	if (!irq_domain) {
	189	dev_dbg(&dev->dev, "axon_msi: no irq_domain found for node %s\n",
ce21b3c9 ME	190	dn->full_name);
	191	goto out_error;
	192	}
	193
bae1d8f1	194	msic = irq_domain->host_data;
ce21b3c9 ME	195
	196	out_error:
	197	of_node_put(dn);
ce21b3c9 ME	198
	199	return msic;
	200	}
	201
	202	static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
	203	{
	204	if (!find_msi_translator(dev))
	205	return -ENODEV;
	206
	207	return 0;
	208	}
	209
	210	static int setup_msi_msg_address(struct pci_dev dev, struct msi_msg msg)
	211	{
988479eb	212	struct device_node *dn;
ce21b3c9 ME	213	struct msi_desc *entry;
	214	int len;
	215	const u32 *prop;
	216
db220b23	217	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	218	if (!dn) {
	219	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	220	return -ENODEV;
	221	}
	222
	223	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
	224
988479eb	225	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	226	if (entry->msi_attrib.is_64) {
	227	prop = of_get_property(dn, "msi-address-64", &len);
	228	if (prop)
	229	break;
	230	}
	231
	232	prop = of_get_property(dn, "msi-address-32", &len);
	233	if (prop)
	234	break;
	235	}
	236
	237	if (!prop) {
	238	dev_dbg(&dev->dev,
	239	"axon_msi: no msi-address-(32\|64) properties found\n");
	240	return -ENOENT;
	241	}
	242
	243	switch (len) {
	244	case 8:
	245	msg->address_hi = prop[0];
	246	msg->address_lo = prop[1];
	247	break;
	248	case 4:
	249	msg->address_hi = 0;
	250	msg->address_lo = prop[0];
	251	break;
	252	default:
	253	dev_dbg(&dev->dev,
	254	"axon_msi: malformed msi-address-(32\|64) property\n");
	255	of_node_put(dn);
	256	return -EINVAL;
	257	}
	258
	259	of_node_put(dn);
	260
	261	return 0;
	262	}
	263
	264	static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	265	{
	266	unsigned int virq, rc;
	267	struct msi_desc *entry;
	268	struct msi_msg msg;
	269	struct axon_msic *msic;
	270
	271	msic = find_msi_translator(dev);
	272	if (!msic)
	273	return -ENODEV;
	274
	275	rc = setup_msi_msg_address(dev, &msg);
	276	if (rc)
	277	return rc;
	278
	279	/* We rely on being able to stash a virq in a u16 */
	280	BUILD_BUG_ON(NR_IRQS > 65536);
	281
	282	list_for_each_entry(entry, &dev->msi_list, list) {
bae1d8f1	283	virq = irq_create_direct_mapping(msic->irq_domain);
ce21b3c9 ME	284	if (virq == NO_IRQ) {
	285	dev_warn(&dev->dev,
	286	"axon_msi: virq allocation failed!\n");
	287	return -1;
	288	}
	289	dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
	290
ec775d0e	291	irq_set_msi_desc(virq, entry);
ce21b3c9 ME	292	msg.data = virq;
	293	write_msi_msg(virq, &msg);
	294	}
	295
	296	return 0;
	297	}
	298
	299	static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
	300	{
	301	struct msi_desc *entry;
	302
	303	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
	304
	305	list_for_each_entry(entry, &dev->msi_list, list) {
	306	if (entry->irq == NO_IRQ)
	307	continue;
	308
ec775d0e	309	irq_set_msi_desc(entry->irq, NULL);
ce21b3c9 ME	310	irq_dispose_mapping(entry->irq);
	311	}
	312	}
	313
	314	static struct irq_chip msic_irq_chip = {
1c9db525 TG	315	.irq_mask = mask_msi_irq,
	316	.irq_unmask = unmask_msi_irq,
	317	.irq_shutdown = mask_msi_irq,
b27df672	318	.name = "AXON-MSI",
ce21b3c9 ME	319	};
ce21b3c9 ME	320
bae1d8f1	321	static int msic_host_map(struct irq_domain *h, unsigned int virq,
ce21b3c9 ME	322	irq_hw_number_t hw)
ce21b3c9 ME	323	{
95533614	324	irq_set_chip_data(virq, h->host_data);
ec775d0e	325	irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
ce21b3c9 ME	326
	327	return 0;
	328	}
	329
bae1d8f1	330	static struct irq_domain_ops msic_host_ops = {
ce21b3c9 ME	331	.map = msic_host_map,
	332	};
	333
00006124	334	static void axon_msi_shutdown(struct platform_device *device)
ce21b3c9	335	{
86c27656	336	struct axon_msic *msic = dev_get_drvdata(&device->dev);
ce21b3c9 ME	337	u32 tmp;
ce21b3c9 ME	338
33875f03	339	pr_devel("axon_msi: disabling %s\n",
bae1d8f1	340	msic->irq_domain->of_node->full_name);
e4347dfb ME	341	tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	342	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	343	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
ce21b3c9 ME	344	}
ce21b3c9 ME	345
00006124	346	static int axon_msi_probe(struct platform_device *device)
ce21b3c9	347	{
61c7a080	348	struct device_node *dn = device->dev.of_node;
ce21b3c9 ME	349	struct axon_msic *msic;
ce21b3c9 ME	350	unsigned int virq;
4acb8896	351	int dcr_base, dcr_len;
ce21b3c9	352
33875f03	353	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
ce21b3c9 ME	354
	355	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	356	if (!msic) {
	357	printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
	358	dn->full_name);
	359	goto out;
	360	}
	361
4acb8896	362	dcr_base = dcr_resource_start(dn, 0);
ce21b3c9 ME	363	dcr_len = dcr_resource_len(dn, 0);
ce21b3c9 ME	364
4acb8896	365	if (dcr_base == 0 \|\| dcr_len == 0) {
ce21b3c9 ME	366	printk(KERN_ERR
	367	"axon_msi: couldn't parse dcr properties on %s\n",
	368	dn->full_name);
aee7a283	369	goto out_free_msic;
ce21b3c9 ME	370	}
ce21b3c9 ME	371
4acb8896	372	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
ce21b3c9 ME	373	if (!DCR_MAP_OK(msic->dcr_host)) {
	374	printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
	375	dn->full_name);
	376	goto out_free_msic;
	377	}
	378
de4c928b ME	379	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
	380	&msic->fifo_phys, GFP_KERNEL);
	381	if (!msic->fifo_virt) {
ce21b3c9 ME	382	printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
	383	dn->full_name);
	384	goto out_free_msic;
	385	}
	386
997526db ME	387	virq = irq_of_parse_and_map(dn, 0);
	388	if (virq == NO_IRQ) {
	389	printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
	390	dn->full_name);
	391	goto out_free_fifo;
	392	}
d015fe99	393	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
997526db	394
a8db8cf0	395	msic->irq_domain = irq_domain_add_nomap(dn, &msic_host_ops, msic);
bae1d8f1 GL	396	if (!msic->irq_domain) {
bae1d8f1 GL	397	printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
ce21b3c9 ME	398	dn->full_name);
	399	goto out_free_fifo;
	400	}
	401
ec775d0e TG	402	irq_set_handler_data(virq, msic);
ec775d0e TG	403	irq_set_chained_handler(virq, axon_msi_cascade);
33875f03	404	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
ce21b3c9 ME	405
ce21b3c9 ME	406	/* Enable the MSIC hardware */
de4c928b	407	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
ce21b3c9	408	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
de4c928b	409	msic->fifo_phys & 0xFFFFFFFF);
ce21b3c9 ME	410	msic_dcr_write(msic, MSIC_CTRL_REG,
	411	MSIC_CTRL_IRQ_ENABLE \| MSIC_CTRL_ENABLE \|
	412	MSIC_CTRL_FIFO_SIZE);
	413
23e0e8af AB	414	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
	415	& MSIC_FIFO_SIZE_MASK;
	416
86c27656	417	dev_set_drvdata(&device->dev, msic);
e4347dfb ME	418
	419	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	420	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	421	ppc_md.msi_check_device = axon_msi_check_device;
ce21b3c9	422
72cac213 ME	423	axon_msi_debug_setup(dn, msic);
72cac213 ME	424
ce21b3c9 ME	425	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
	426
	427	return 0;
	428
ce21b3c9	429	out_free_fifo:
de4c928b ME	430	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
de4c928b ME	431	msic->fifo_phys);
ce21b3c9 ME	432	out_free_msic:
	433	kfree(msic);
	434	out:
	435
	436	return -1;
	437	}
	438
e4347dfb ME	439	static const struct of_device_id axon_msi_device_id[] = {
	440	{
	441	.compatible = "ibm,axon-msic"
	442	},
	443	{}
	444	};
ce21b3c9	445
00006124	446	static struct platform_driver axon_msi_driver = {
e4347dfb ME	447	.probe = axon_msi_probe,
e4347dfb ME	448	.shutdown = axon_msi_shutdown,
4018294b GL	449	.driver = {
	450	.name = "axon-msi",
	451	.owner = THIS_MODULE,
	452	.of_match_table = axon_msi_device_id,
e4347dfb ME	453	},
e4347dfb ME	454	};
ce21b3c9	455
e4347dfb ME	456	static int __init axon_msi_init(void)
e4347dfb ME	457	{
00006124	458	return platform_driver_register(&axon_msi_driver);
ce21b3c9	459	}
e4347dfb	460	subsys_initcall(axon_msi_init);
72cac213 ME	461
	462
	463	#ifdef DEBUG
	464	static int msic_set(void *data, u64 val)
	465	{
	466	struct axon_msic *msic = data;
	467	out_le32(msic->trigger, val);
	468	return 0;
	469	}
	470
	471	static int msic_get(void data, u64 val)
	472	{
	473	*val = 0;
	474	return 0;
	475	}
	476
	477	DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
	478
	479	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic)
	480	{
	481	char name[8];
	482	u64 addr;
	483
	484	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	485	if (addr == OF_BAD_ADDR) {
33875f03	486	pr_devel("axon_msi: couldn't translate reg property\n");
72cac213 ME	487	return;
	488	}
	489
	490	msic->trigger = ioremap(addr, 0x4);
	491	if (!msic->trigger) {
33875f03	492	pr_devel("axon_msi: ioremap failed\n");
72cac213 ME	493	return;
	494	}
	495
	496	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
	497
	498	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
	499	msic, &fops_msic)) {
33875f03	500	pr_devel("axon_msi: debugfs_create_file failed!\n");
72cac213 ME	501	return;
	502	}
	503	}
	504	#endif /* DEBUG */