[linux-2.6-block.git] / arch / powerpc / platforms / cell / axon_msi.c

/*
 * Copyright 2007, Michael Ellerman, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */


#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/of_platform.h>
#include <linux/debugfs.h>
#include <linux/slab.h>

#include <asm/dcr.h>
#include <asm/machdep.h>
#include <asm/prom.h>


/*
 * MSIC registers, specified as offsets from dcr_base
 */
#define MSIC_CTRL_REG	0x0

/* Base Address registers specify FIFO location in BE memory */
#define MSIC_BASE_ADDR_HI_REG	0x3
#define MSIC_BASE_ADDR_LO_REG	0x4

/* Hold the read/write offsets into the FIFO */
#define MSIC_READ_OFFSET_REG	0x5
#define MSIC_WRITE_OFFSET_REG	0x6


/* MSIC control register flags */
#define MSIC_CTRL_ENABLE		0x0001
#define MSIC_CTRL_FIFO_FULL_ENABLE	0x0002
#define MSIC_CTRL_IRQ_ENABLE		0x0008
#define MSIC_CTRL_FULL_STOP_ENABLE	0x0010

/*
 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
 * Currently we're using a 64KB FIFO size.
 */
#define MSIC_FIFO_SIZE_SHIFT	16
#define MSIC_FIFO_SIZE_BYTES	(1 << MSIC_FIFO_SIZE_SHIFT)

/*
 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
 * 8-9 of the MSIC control reg.
 */
#define MSIC_CTRL_FIFO_SIZE	(((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)

/*
 * We need to mask the read/write offsets to make sure they stay within
 * the bounds of the FIFO. Also they should always be 16-byte aligned.
 */
#define MSIC_FIFO_SIZE_MASK	((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)

/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
#define MSIC_FIFO_ENTRY_SIZE	0x10


struct axon_msic {
	struct irq_host *irq_host;
	__le32 *fifo_virt;
	dma_addr_t fifo_phys;
	dcr_host_t dcr_host;
	u32 read_offset;
#ifdef DEBUG
	u32 __iomem *trigger;
#endif
};

#ifdef DEBUG
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
#else
static inline void axon_msi_debug_setup(struct device_node *dn,
					struct axon_msic *msic) { }
#endif


static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
{
	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);

	dcr_write(msic->dcr_host, dcr_n, val);
}

static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct axon_msic *msic = get_irq_data(irq);
	u32 write_offset, msi;
	int idx;
	int retry = 0;

	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);

	/* write_offset doesn't wrap properly, so we have to mask it */
	write_offset &= MSIC_FIFO_SIZE_MASK;

	while (msic->read_offset != write_offset && retry < 100) {
		idx  = msic->read_offset / sizeof(__le32);
		msi  = le32_to_cpu(msic->fifo_virt[idx]);
		msi &= 0xFFFF;

		pr_devel("axon_msi: woff %x roff %x msi %x\n",
			  write_offset, msic->read_offset, msi);

		if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
			generic_handle_irq(msi);
			msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
		} else {
			/*
			 * Reading the MSIC_WRITE_OFFSET_REG does not
			 * reliably flush the outstanding DMA to the
			 * FIFO buffer. Here we were reading stale
			 * data, so we need to retry.
			 */
			udelay(1);
			retry++;
			pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
			continue;
		}

		if (retry) {
			pr_devel("axon_msi: late irq 0x%x, retry %d\n",
				 msi, retry);
			retry = 0;
		}

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	if (retry) {
		printk(KERN_WARNING "axon_msi: irq timed out\n");

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	}

	desc->chip->eoi(irq);
}

static struct axon_msic *find_msi_translator(struct pci_dev *dev)
{
	struct irq_host *irq_host;
	struct device_node *dn, *tmp;
	const phandle *ph;
	struct axon_msic *msic = NULL;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return NULL;
	}

	for (; dn; dn = of_get_next_parent(dn)) {
		ph = of_get_property(dn, "msi-translator", NULL);
		if (ph)
			break;
	}

	if (!ph) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-translator property found\n");
		goto out_error;
	}

	tmp = dn;
	dn = of_find_node_by_phandle(*ph);
	of_node_put(tmp);
	if (!dn) {
		dev_dbg(&dev->dev,
			"axon_msi: msi-translator doesn't point to a node\n");
		goto out_error;
	}

	irq_host = irq_find_host(dn);
	if (!irq_host) {
		dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
			dn->full_name);
		goto out_error;
	}

	msic = irq_host->host_data;

out_error:
	of_node_put(dn);

	return msic;
}

static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
{
	if (!find_msi_translator(dev))
		return -ENODEV;

	return 0;
}

static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
{
	struct device_node *dn;
	struct msi_desc *entry;
	int len;
	const u32 *prop;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return -ENODEV;
	}

	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);

	for (; dn; dn = of_get_next_parent(dn)) {
		if (entry->msi_attrib.is_64) {
			prop = of_get_property(dn, "msi-address-64", &len);
			if (prop)
				break;
		}

		prop = of_get_property(dn, "msi-address-32", &len);
		if (prop)
			break;
	}

	if (!prop) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-address-(32|64) properties found\n");
		return -ENOENT;
	}

	switch (len) {
	case 8:
		msg->address_hi = prop[0];
		msg->address_lo = prop[1];
		break;
	case 4:
		msg->address_hi = 0;
		msg->address_lo = prop[0];
		break;
	default:
		dev_dbg(&dev->dev,
			"axon_msi: malformed msi-address-(32|64) property\n");
		of_node_put(dn);
		return -EINVAL;
	}

	of_node_put(dn);

	return 0;
}

static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	unsigned int virq, rc;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct axon_msic *msic;

	msic = find_msi_translator(dev);
	if (!msic)
		return -ENODEV;

	rc = setup_msi_msg_address(dev, &msg);
	if (rc)
		return rc;

	/* We rely on being able to stash a virq in a u16 */
	BUILD_BUG_ON(NR_IRQS > 65536);

	list_for_each_entry(entry, &dev->msi_list, list) {
		virq = irq_create_direct_mapping(msic->irq_host);
		if (virq == NO_IRQ) {
			dev_warn(&dev->dev,
				 "axon_msi: virq allocation failed!\n");
			return -1;
		}
		dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);

		set_irq_msi(virq, entry);
		msg.data = virq;
		write_msi_msg(virq, &msg);
	}

	return 0;
}

static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
{
	struct msi_desc *entry;

	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");

	list_for_each_entry(entry, &dev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;

		set_irq_msi(entry->irq, NULL);
		irq_dispose_mapping(entry->irq);
	}
}

static struct irq_chip msic_irq_chip = {
	.mask		= mask_msi_irq,
	.unmask		= unmask_msi_irq,
	.shutdown	= unmask_msi_irq,
	.name		= "AXON-MSI",
};

static int msic_host_map(struct irq_host *h, unsigned int virq,
			 irq_hw_number_t hw)
{
	set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);

	return 0;
}

static struct irq_host_ops msic_host_ops = {
	.map	= msic_host_map,
};

static int axon_msi_shutdown(struct of_device *device)
{
	struct axon_msic *msic = dev_get_drvdata(&device->dev);
	u32 tmp;

	pr_devel("axon_msi: disabling %s\n",
		  msic->irq_host->of_node->full_name);
	tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);

	return 0;
}

static int axon_msi_probe(struct of_device *device,
			  const struct of_device_id *device_id)
{
	struct device_node *dn = device->dev.of_node;
	struct axon_msic *msic;
	unsigned int virq;
	int dcr_base, dcr_len;

	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);

	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	if (!msic) {
		printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
		       dn->full_name);
		goto out;
	}

	dcr_base = dcr_resource_start(dn, 0);
	dcr_len = dcr_resource_len(dn, 0);

	if (dcr_base == 0 || dcr_len == 0) {
		printk(KERN_ERR
		       "axon_msi: couldn't parse dcr properties on %s\n",
			dn->full_name);
		goto out_free_msic;
	}

	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
	if (!DCR_MAP_OK(msic->dcr_host)) {
		printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
					     &msic->fifo_phys, GFP_KERNEL);
	if (!msic->fifo_virt) {
		printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	virq = irq_of_parse_and_map(dn, 0);
	if (virq == NO_IRQ) {
		printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}
	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);

	msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
					NR_IRQS, &msic_host_ops, 0);
	if (!msic->irq_host) {
		printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}

	msic->irq_host->host_data = msic;

	set_irq_data(virq, msic);
	set_irq_chained_handler(virq, axon_msi_cascade);
	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);

	/* Enable the MSIC hardware */
	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
				  msic->fifo_phys & 0xFFFFFFFF);
	msic_dcr_write(msic, MSIC_CTRL_REG,
			MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
			MSIC_CTRL_FIFO_SIZE);

	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
				& MSIC_FIFO_SIZE_MASK;

	dev_set_drvdata(&device->dev, msic);

	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	ppc_md.msi_check_device = axon_msi_check_device;

	axon_msi_debug_setup(dn, msic);

	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);

	return 0;

out_free_fifo:
	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
			  msic->fifo_phys);
out_free_msic:
	kfree(msic);
out:

	return -1;
}

static const struct of_device_id axon_msi_device_id[] = {
	{
		.compatible	= "ibm,axon-msic"
	},
	{}
};

static struct of_platform_driver axon_msi_driver = {
	.probe		= axon_msi_probe,
	.shutdown	= axon_msi_shutdown,
	.driver = {
		.name = "axon-msi",
		.owner = THIS_MODULE,
		.of_match_table = axon_msi_device_id,
	},
};

static int __init axon_msi_init(void)
{
	return of_register_platform_driver(&axon_msi_driver);
}
subsys_initcall(axon_msi_init);


#ifdef DEBUG
static int msic_set(void *data, u64 val)
{
	struct axon_msic *msic = data;
	out_le32(msic->trigger, val);
	return 0;
}

static int msic_get(void *data, u64 *val)
{
	*val = 0;
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");

void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
{
	char name[8];
	u64 addr;

	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	if (addr == OF_BAD_ADDR) {
		pr_devel("axon_msi: couldn't translate reg property\n");
		return;
	}

	msic->trigger = ioremap(addr, 0x4);
	if (!msic->trigger) {
		pr_devel("axon_msi: ioremap failed\n");
		return;
	}

	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));

	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
				 msic, &fops_msic)) {
		pr_devel("axon_msi: debugfs_create_file failed!\n");
		return;
	}
}
#endif /* DEBUG */
Commit	Line	Data
ce21b3c9 ME	1	/*
	2	* Copyright 2007, Michael Ellerman, IBM Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/msi.h>
e4347dfb	16	#include <linux/of_platform.h>
72cac213	17	#include <linux/debugfs.h>
5a0e3ad6	18	#include <linux/slab.h>
ce21b3c9 ME	19
	20	#include <asm/dcr.h>
	21	#include <asm/machdep.h>
	22	#include <asm/prom.h>
	23
	24
	25	/*
	26	* MSIC registers, specified as offsets from dcr_base
	27	*/
	28	#define MSIC_CTRL_REG 0x0
	29
	30	/* Base Address registers specify FIFO location in BE memory */
	31	#define MSIC_BASE_ADDR_HI_REG 0x3
	32	#define MSIC_BASE_ADDR_LO_REG 0x4
	33
	34	/* Hold the read/write offsets into the FIFO */
	35	#define MSIC_READ_OFFSET_REG 0x5
	36	#define MSIC_WRITE_OFFSET_REG 0x6
	37
	38
	39	/* MSIC control register flags */
	40	#define MSIC_CTRL_ENABLE 0x0001
	41	#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
	42	#define MSIC_CTRL_IRQ_ENABLE 0x0008
	43	#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
	44
	45	/*
	46	* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
	47	* Currently we're using a 64KB FIFO size.
	48	*/
	49	#define MSIC_FIFO_SIZE_SHIFT 16
	50	#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
	51
	52	/*
	53	* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
	54	* 8-9 of the MSIC control reg.
	55	*/
	56	#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
	57
	58	/*
	59	* We need to mask the read/write offsets to make sure they stay within
	60	* the bounds of the FIFO. Also they should always be 16-byte aligned.
	61	*/
	62	#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
	63
	64	/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
	65	#define MSIC_FIFO_ENTRY_SIZE 0x10
	66
	67
	68	struct axon_msic {
ce21b3c9	69	struct irq_host *irq_host;
de4c928b ME	70	__le32 *fifo_virt;
de4c928b ME	71	dma_addr_t fifo_phys;
ce21b3c9	72	dcr_host_t dcr_host;
ce21b3c9	73	u32 read_offset;
72cac213 ME	74	#ifdef DEBUG
	75	u32 __iomem *trigger;
	76	#endif
ce21b3c9 ME	77	};
ce21b3c9 ME	78
72cac213 ME	79	#ifdef DEBUG
	80	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic);
	81	#else
	82	static inline void axon_msi_debug_setup(struct device_node *dn,
	83	struct axon_msic *msic) { }
	84	#endif
	85
	86
ce21b3c9 ME	87	static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
ce21b3c9 ME	88	{
33875f03	89	pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
ce21b3c9	90
83f34df4	91	dcr_write(msic->dcr_host, dcr_n, val);
ce21b3c9 ME	92	}
ce21b3c9 ME	93
ce21b3c9 ME	94	static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
	95	{
	96	struct axon_msic *msic = get_irq_data(irq);
	97	u32 write_offset, msi;
	98	int idx;
d015fe99	99	int retry = 0;
ce21b3c9	100
2843e7f7	101	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
33875f03	102	pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
ce21b3c9 ME	103
	104	/* write_offset doesn't wrap properly, so we have to mask it */
	105	write_offset &= MSIC_FIFO_SIZE_MASK;
	106
d015fe99	107	while (msic->read_offset != write_offset && retry < 100) {
ce21b3c9	108	idx = msic->read_offset / sizeof(__le32);
de4c928b	109	msi = le32_to_cpu(msic->fifo_virt[idx]);
ce21b3c9 ME	110	msi &= 0xFFFF;
ce21b3c9 ME	111
33875f03	112	pr_devel("axon_msi: woff %x roff %x msi %x\n",
ce21b3c9 ME	113	write_offset, msic->read_offset, msi);
ce21b3c9 ME	114
d015fe99 AB	115	if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
	116	generic_handle_irq(msi);
	117	msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
	118	} else {
	119	/*
	120	* Reading the MSIC_WRITE_OFFSET_REG does not
	121	* reliably flush the outstanding DMA to the
	122	* FIFO buffer. Here we were reading stale
	123	* data, so we need to retry.
	124	*/
	125	udelay(1);
	126	retry++;
33875f03	127	pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
d015fe99 AB	128	continue;
	129	}
	130
	131	if (retry) {
33875f03	132	pr_devel("axon_msi: late irq 0x%x, retry %d\n",
d015fe99 AB	133	msi, retry);
	134	retry = 0;
	135	}
	136
ce21b3c9 ME	137	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
ce21b3c9 ME	138	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
d015fe99	139	}
ce21b3c9	140
d015fe99 AB	141	if (retry) {
	142	printk(KERN_WARNING "axon_msi: irq timed out\n");
	143
	144	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
	145	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
ce21b3c9 ME	146	}
	147
	148	desc->chip->eoi(irq);
	149	}
	150
	151	static struct axon_msic find_msi_translator(struct pci_dev dev)
	152	{
	153	struct irq_host *irq_host;
	154	struct device_node dn, tmp;
	155	const phandle *ph;
	156	struct axon_msic *msic = NULL;
	157
db220b23	158	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	159	if (!dn) {
	160	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	161	return NULL;
	162	}
	163
988479eb	164	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	165	ph = of_get_property(dn, "msi-translator", NULL);
	166	if (ph)
	167	break;
	168	}
	169
	170	if (!ph) {
	171	dev_dbg(&dev->dev,
	172	"axon_msi: no msi-translator property found\n");
	173	goto out_error;
	174	}
	175
	176	tmp = dn;
	177	dn = of_find_node_by_phandle(*ph);
c6d01179	178	of_node_put(tmp);
ce21b3c9 ME	179	if (!dn) {
	180	dev_dbg(&dev->dev,
	181	"axon_msi: msi-translator doesn't point to a node\n");
	182	goto out_error;
	183	}
	184
	185	irq_host = irq_find_host(dn);
	186	if (!irq_host) {
	187	dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
	188	dn->full_name);
	189	goto out_error;
	190	}
	191
	192	msic = irq_host->host_data;
	193
	194	out_error:
	195	of_node_put(dn);
ce21b3c9 ME	196
	197	return msic;
	198	}
	199
	200	static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
	201	{
	202	if (!find_msi_translator(dev))
	203	return -ENODEV;
	204
	205	return 0;
	206	}
	207
	208	static int setup_msi_msg_address(struct pci_dev dev, struct msi_msg msg)
	209	{
988479eb	210	struct device_node *dn;
ce21b3c9 ME	211	struct msi_desc *entry;
	212	int len;
	213	const u32 *prop;
	214
db220b23	215	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	216	if (!dn) {
	217	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	218	return -ENODEV;
	219	}
	220
	221	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
	222
988479eb	223	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	224	if (entry->msi_attrib.is_64) {
	225	prop = of_get_property(dn, "msi-address-64", &len);
	226	if (prop)
	227	break;
	228	}
	229
	230	prop = of_get_property(dn, "msi-address-32", &len);
	231	if (prop)
	232	break;
	233	}
	234
	235	if (!prop) {
	236	dev_dbg(&dev->dev,
	237	"axon_msi: no msi-address-(32\|64) properties found\n");
	238	return -ENOENT;
	239	}
	240
	241	switch (len) {
	242	case 8:
	243	msg->address_hi = prop[0];
	244	msg->address_lo = prop[1];
	245	break;
	246	case 4:
	247	msg->address_hi = 0;
	248	msg->address_lo = prop[0];
	249	break;
	250	default:
	251	dev_dbg(&dev->dev,
	252	"axon_msi: malformed msi-address-(32\|64) property\n");
	253	of_node_put(dn);
	254	return -EINVAL;
	255	}
	256
	257	of_node_put(dn);
	258
	259	return 0;
	260	}
	261
	262	static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	263	{
	264	unsigned int virq, rc;
	265	struct msi_desc *entry;
	266	struct msi_msg msg;
	267	struct axon_msic *msic;
	268
	269	msic = find_msi_translator(dev);
	270	if (!msic)
	271	return -ENODEV;
	272
	273	rc = setup_msi_msg_address(dev, &msg);
	274	if (rc)
	275	return rc;
	276
	277	/* We rely on being able to stash a virq in a u16 */
	278	BUILD_BUG_ON(NR_IRQS > 65536);
	279
	280	list_for_each_entry(entry, &dev->msi_list, list) {
	281	virq = irq_create_direct_mapping(msic->irq_host);
	282	if (virq == NO_IRQ) {
	283	dev_warn(&dev->dev,
	284	"axon_msi: virq allocation failed!\n");
	285	return -1;
	286	}
	287	dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
288
289	set_irq_msi(virq, entry);
290	msg.data = virq;
291	write_msi_msg(virq, &msg);
292	}
293
294	return 0;
295	}
296
297	static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
298	{
299	struct msi_desc *entry;
300
301	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
302
303	list_for_each_entry(entry, &dev->msi_list, list) {
304	if (entry->irq == NO_IRQ)
305	continue;
306
307	set_irq_msi(entry->irq, NULL);
308	irq_dispose_mapping(entry->irq);
309	}
310	}
311
312	static struct irq_chip msic_irq_chip = {
313	.mask = mask_msi_irq,
314	.unmask = unmask_msi_irq,
315	.shutdown = unmask_msi_irq,
b27df672	316	.name = "AXON-MSI",
ce21b3c9 ME	317	};
	318
	319	static int msic_host_map(struct irq_host *h, unsigned int virq,
	320	irq_hw_number_t hw)
	321	{
	322	set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
	323
	324	return 0;
	325	}
	326
ce21b3c9	327	static struct irq_host_ops msic_host_ops = {
ce21b3c9 ME	328	.map = msic_host_map,
	329	};
	330
e4347dfb	331	static int axon_msi_shutdown(struct of_device *device)
ce21b3c9	332	{
86c27656	333	struct axon_msic *msic = dev_get_drvdata(&device->dev);
ce21b3c9 ME	334	u32 tmp;
ce21b3c9 ME	335
33875f03	336	pr_devel("axon_msi: disabling %s\n",
e4347dfb ME	337	msic->irq_host->of_node->full_name);
	338	tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	339	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	340	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
ce21b3c9 ME	341
	342	return 0;
	343	}
	344
e4347dfb ME	345	static int axon_msi_probe(struct of_device *device,
e4347dfb ME	346	const struct of_device_id *device_id)
ce21b3c9	347	{
61c7a080	348	struct device_node *dn = device->dev.of_node;
ce21b3c9 ME	349	struct axon_msic *msic;
ce21b3c9 ME	350	unsigned int virq;
4acb8896	351	int dcr_base, dcr_len;
ce21b3c9	352
33875f03	353	pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
ce21b3c9 ME	354
	355	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	356	if (!msic) {
	357	printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
	358	dn->full_name);
	359	goto out;
	360	}
	361
4acb8896	362	dcr_base = dcr_resource_start(dn, 0);
ce21b3c9 ME	363	dcr_len = dcr_resource_len(dn, 0);
ce21b3c9 ME	364
4acb8896	365	if (dcr_base == 0 \|\| dcr_len == 0) {
ce21b3c9 ME	366	printk(KERN_ERR
	367	"axon_msi: couldn't parse dcr properties on %s\n",
	368	dn->full_name);
aee7a283	369	goto out_free_msic;
ce21b3c9 ME	370	}
ce21b3c9 ME	371
4acb8896	372	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
ce21b3c9 ME	373	if (!DCR_MAP_OK(msic->dcr_host)) {
	374	printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
	375	dn->full_name);
	376	goto out_free_msic;
	377	}
	378
de4c928b ME	379	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
	380	&msic->fifo_phys, GFP_KERNEL);
	381	if (!msic->fifo_virt) {
ce21b3c9 ME	382	printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
	383	dn->full_name);
	384	goto out_free_msic;
	385	}
	386
997526db ME	387	virq = irq_of_parse_and_map(dn, 0);
	388	if (virq == NO_IRQ) {
	389	printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
	390	dn->full_name);
	391	goto out_free_fifo;
	392	}
d015fe99	393	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
997526db	394
19fc65b5	395	msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
52964f87	396	NR_IRQS, &msic_host_ops, 0);
ce21b3c9 ME	397	if (!msic->irq_host) {
	398	printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
	399	dn->full_name);
	400	goto out_free_fifo;
	401	}
	402
	403	msic->irq_host->host_data = msic;
	404
ce21b3c9 ME	405	set_irq_data(virq, msic);
ce21b3c9 ME	406	set_irq_chained_handler(virq, axon_msi_cascade);
33875f03	407	pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
ce21b3c9 ME	408
ce21b3c9 ME	409	/* Enable the MSIC hardware */
de4c928b	410	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
ce21b3c9	411	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
de4c928b	412	msic->fifo_phys & 0xFFFFFFFF);
ce21b3c9 ME	413	msic_dcr_write(msic, MSIC_CTRL_REG,
	414	MSIC_CTRL_IRQ_ENABLE \| MSIC_CTRL_ENABLE \|
	415	MSIC_CTRL_FIFO_SIZE);
	416
23e0e8af AB	417	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
	418	& MSIC_FIFO_SIZE_MASK;
	419
86c27656	420	dev_set_drvdata(&device->dev, msic);
e4347dfb ME	421
	422	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	423	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	424	ppc_md.msi_check_device = axon_msi_check_device;
ce21b3c9	425
72cac213 ME	426	axon_msi_debug_setup(dn, msic);
72cac213 ME	427
ce21b3c9 ME	428	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
	429
	430	return 0;
	431
ce21b3c9	432	out_free_fifo:
de4c928b ME	433	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
de4c928b ME	434	msic->fifo_phys);
ce21b3c9 ME	435	out_free_msic:
	436	kfree(msic);
	437	out:
	438
	439	return -1;
	440	}
	441
e4347dfb ME	442	static const struct of_device_id axon_msi_device_id[] = {
	443	{
	444	.compatible = "ibm,axon-msic"
	445	},
	446	{}
	447	};
ce21b3c9	448
e4347dfb	449	static struct of_platform_driver axon_msi_driver = {
e4347dfb ME	450	.probe = axon_msi_probe,
e4347dfb ME	451	.shutdown = axon_msi_shutdown,
4018294b GL	452	.driver = {
	453	.name = "axon-msi",
	454	.owner = THIS_MODULE,
	455	.of_match_table = axon_msi_device_id,
e4347dfb ME	456	},
e4347dfb ME	457	};
ce21b3c9	458
e4347dfb ME	459	static int __init axon_msi_init(void)
	460	{
	461	return of_register_platform_driver(&axon_msi_driver);
ce21b3c9	462	}
e4347dfb	463	subsys_initcall(axon_msi_init);
72cac213 ME	464
	465
	466	#ifdef DEBUG
	467	static int msic_set(void *data, u64 val)
	468	{
	469	struct axon_msic *msic = data;
	470	out_le32(msic->trigger, val);
	471	return 0;
	472	}
	473
	474	static int msic_get(void data, u64 val)
	475	{
	476	*val = 0;
	477	return 0;
	478	}
	479
	480	DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
	481
	482	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic)
	483	{
	484	char name[8];
	485	u64 addr;
	486
	487	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	488	if (addr == OF_BAD_ADDR) {
33875f03	489	pr_devel("axon_msi: couldn't translate reg property\n");
72cac213 ME	490	return;
	491	}
	492
	493	msic->trigger = ioremap(addr, 0x4);
	494	if (!msic->trigger) {
33875f03	495	pr_devel("axon_msi: ioremap failed\n");
72cac213 ME	496	return;
	497	}
	498
	499	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
	500
	501	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
	502	msic, &fops_msic)) {
33875f03	503	pr_devel("axon_msi: debugfs_create_file failed!\n");
72cac213 ME	504	return;
	505	}
	506	}
	507	#endif /* DEBUG */