[linux-block.git] / arch / powerpc / platforms / 86xx / mpc8610_hpcd.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8610 HPCD board specific routines
 *
 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
 * Recode: Jason Jin <jason.jin@freescale.com>
 *         York Sun <yorksun@freescale.com>
 *
 * Rewrite the interrupt routing. remove the 8259PIC support,
 * All the integrated device in ULI use sideband interrupt.
 *
 * Copyright 2008 Freescale Semiconductor Inc.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/of.h>
#include <linux/fsl/guts.h>

#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/prom.h>
#include <mm/mmu_decl.h>
#include <asm/udbg.h>

#include <asm/mpic.h>

#include <linux/of_platform.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/simple_gpio.h>

#include "mpc86xx.h"

static struct device_node *pixis_node;
static unsigned char *pixis_bdcfg0, *pixis_arch;

/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
#define CLKDVDR_PXCKEN		0x80000000
#define CLKDVDR_PXCKINV		0x10000000
#define CLKDVDR_PXCKDLY		0x06000000
#define CLKDVDR_PXCLK_MASK	0x001F0000

#ifdef CONFIG_SUSPEND
static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
{
	pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
	return IRQ_HANDLED;
}

static void __init mpc8610_suspend_init(void)
{
	int irq;
	int ret;

	if (!pixis_node)
		return;

	irq = irq_of_parse_and_map(pixis_node, 0);
	if (!irq) {
		pr_err("%s: can't map pixis event IRQ.\n", __func__);
		return;
	}

	ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
	if (ret) {
		pr_err("%s: can't request pixis event IRQ: %d\n",
		       __func__, ret);
		irq_dispose_mapping(irq);
	}

	enable_irq_wake(irq);
}
#else
static inline void mpc8610_suspend_init(void) { }
#endif /* CONFIG_SUSPEND */

static const struct of_device_id mpc8610_ids[] __initconst = {
	{ .compatible = "fsl,mpc8610-immr", },
	{ .compatible = "fsl,mpc8610-guts", },
	/* So that the DMA channel nodes can be probed individually: */
	{ .compatible = "fsl,eloplus-dma", },
	/* PCI controllers */
	{ .compatible = "fsl,mpc8610-pci", },
	{}
};

static int __init mpc8610_declare_of_platform_devices(void)
{
	/* Firstly, register PIXIS GPIOs. */
	simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");

	/* Enable wakeup on PIXIS' event IRQ. */
	mpc8610_suspend_init();

	mpc86xx_common_publish_devices();

	/* Without this call, the SSI device driver won't get probed. */
	of_platform_bus_probe(NULL, mpc8610_ids, NULL);

	return 0;
}
machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)

/*
 * DIU Area Descriptor
 *
 * The MPC8610 reference manual shows the bits of the AD register in
 * little-endian order, which causes the BLUE_C field to be split into two
 * parts. To simplify the definition of the MAKE_AD() macro, we define the
 * fields in big-endian order and byte-swap the result.
 *
 * So even though the registers don't look like they're in the
 * same bit positions as they are on the P1022, the same value is written to
 * the AD register on the MPC8610 and on the P1022.
 */
#define AD_BYTE_F		0x10000000
#define AD_ALPHA_C_MASK		0x0E000000
#define AD_ALPHA_C_SHIFT	25
#define AD_BLUE_C_MASK		0x01800000
#define AD_BLUE_C_SHIFT		23
#define AD_GREEN_C_MASK		0x00600000
#define AD_GREEN_C_SHIFT	21
#define AD_RED_C_MASK		0x00180000
#define AD_RED_C_SHIFT		19
#define AD_PALETTE		0x00040000
#define AD_PIXEL_S_MASK		0x00030000
#define AD_PIXEL_S_SHIFT	16
#define AD_COMP_3_MASK		0x0000F000
#define AD_COMP_3_SHIFT		12
#define AD_COMP_2_MASK		0x00000F00
#define AD_COMP_2_SHIFT		8
#define AD_COMP_1_MASK		0x000000F0
#define AD_COMP_1_SHIFT		4
#define AD_COMP_0_MASK		0x0000000F
#define AD_COMP_0_SHIFT		0

#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
	cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
	(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
	(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
	(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
	(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))

u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
				 unsigned int bits_per_pixel)
{
	static const u32 pixelformat[][3] = {
		{
			MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
			MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
			MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
		},
		{
			MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
			MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
			MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
		},
	};
	unsigned int arch_monitor;

	/* The DVI port is mis-wired on revision 1 of this board. */
	arch_monitor =
		((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;

	switch (bits_per_pixel) {
	case 32:
		return pixelformat[arch_monitor][0];
	case 24:
		return pixelformat[arch_monitor][1];
	case 16:
		return pixelformat[arch_monitor][2];
	default:
		pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
		return 0;
	}
}

void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
				 char *gamma_table_base)
{
	int i;
	if (port == FSL_DIU_PORT_DLVDS) {
		for (i = 0; i < 256*3; i++)
			gamma_table_base[i] = (gamma_table_base[i] << 2) |
					 ((gamma_table_base[i] >> 6) & 0x03);
	}
}

#define PX_BRDCFG0_DVISEL	(1 << 3)
#define PX_BRDCFG0_DLINK	(1 << 4)
#define PX_BRDCFG0_DIU_MASK	(PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)

void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
{
	switch (port) {
	case FSL_DIU_PORT_DVI:
		clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
			     PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK);
		break;
	case FSL_DIU_PORT_LVDS:
		clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
			     PX_BRDCFG0_DLINK);
		break;
	case FSL_DIU_PORT_DLVDS:
		clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
		break;
	}
}

/**
 * mpc8610hpcd_set_pixel_clock: program the DIU's clock
 *
 * @pixclock: the wavelength, in picoseconds, of the clock
 */
void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
{
	struct device_node *guts_np = NULL;
	struct ccsr_guts __iomem *guts;
	unsigned long freq;
	u64 temp;
	u32 pxclk;

	/* Map the global utilities registers. */
	guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
	if (!guts_np) {
		pr_err("mpc8610hpcd: missing global utilities device node\n");
		return;
	}

	guts = of_iomap(guts_np, 0);
	of_node_put(guts_np);
	if (!guts) {
		pr_err("mpc8610hpcd: could not map global utilities device\n");
		return;
	}

	/* Convert pixclock from a wavelength to a frequency */
	temp = 1000000000000ULL;
	do_div(temp, pixclock);
	freq = temp;

	/*
	 * 'pxclk' is the ratio of the platform clock to the pixel clock.
	 * On the MPC8610, the value programmed into CLKDVDR is the ratio
	 * minus one.  The valid range of values is 2-31.
	 */
	pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
	pxclk = clamp_t(u32, pxclk, 2, 31);

	/* Disable the pixel clock, and set it to non-inverted and no delay */
	clrbits32(&guts->clkdvdr,
		  CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);

	/* Enable the clock and set the pxclk */
	setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));

	iounmap(guts);
}

enum fsl_diu_monitor_port
mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
{
	return port;
}

#endif

static void __init mpc86xx_hpcd_setup_arch(void)
{
	struct resource r;
	unsigned char *pixis;

	if (ppc_md.progress)
		ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);

	fsl_pci_assign_primary();

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
	diu_ops.get_pixel_format	= mpc8610hpcd_get_pixel_format;
	diu_ops.set_gamma_table		= mpc8610hpcd_set_gamma_table;
	diu_ops.set_monitor_port	= mpc8610hpcd_set_monitor_port;
	diu_ops.set_pixel_clock		= mpc8610hpcd_set_pixel_clock;
	diu_ops.valid_monitor_port	= mpc8610hpcd_valid_monitor_port;
#endif

	pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	if (pixis_node) {
		of_address_to_resource(pixis_node, 0, &r);
		of_node_put(pixis_node);
		pixis = ioremap(r.start, 32);
		if (!pixis) {
			printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
			return;
		}
		pixis_bdcfg0 = pixis + 8;
		pixis_arch = pixis + 1;
	} else
		printk(KERN_ERR "Err: "
				"can't find device node 'fsl,fpga-pixis'\n");

	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
}

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc86xx_hpcd_probe(void)
{
	if (of_machine_is_compatible("fsl,MPC8610HPCD"))
		return 1;	/* Looks good */

	return 0;
}

define_machine(mpc86xx_hpcd) {
	.name			= "MPC86xx HPCD",
	.probe			= mpc86xx_hpcd_probe,
	.setup_arch		= mpc86xx_hpcd_setup_arch,
	.init_IRQ		= mpc86xx_init_irq,
	.get_irq		= mpic_get_irq,
	.time_init		= mpc86xx_time_init,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#endif
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
0e65bfe3 XX	2	/*
	3	* MPC8610 HPCD board specific routines
	4	*
	5	* Initial author: Xianghua Xiao <x.xiao@freescale.com>
	6	* Recode: Jason Jin <jason.jin@freescale.com>
6f90a8bd	7	* York Sun <yorksun@freescale.com>
0e65bfe3 XX	8	*
	9	* Rewrite the interrupt routing. remove the 8259PIC support,
	10	* All the integrated device in ULI use sideband interrupt.
	11	*
6f90a8bd	12	* Copyright 2008 Freescale Semiconductor Inc.
0e65bfe3 XX	13	*/
	14
	15	#include <linux/stddef.h>
	16	#include <linux/kernel.h>
	17	#include <linux/pci.h>
8c68e2f7	18	#include <linux/interrupt.h>
0e65bfe3 XX	19	#include <linux/kdev_t.h>
	20	#include <linux/delay.h>
	21	#include <linux/seq_file.h>
	22	#include <linux/of.h>
94848654	23	#include <linux/fsl/guts.h>
0e65bfe3	24
0e65bfe3 XX	25	#include <asm/time.h>
	26	#include <asm/machdep.h>
	27	#include <asm/pci-bridge.h>
0e65bfe3 XX	28	#include <asm/prom.h>
	29	#include <mm/mmu_decl.h>
	30	#include <asm/udbg.h>
	31
	32	#include <asm/mpic.h>
	33
c7d24a2d	34	#include <linux/of_platform.h>
0e65bfe3 XX	35	#include <sysdev/fsl_pci.h>
0e65bfe3 XX	36	#include <sysdev/fsl_soc.h>
d2998c2c	37	#include <sysdev/simple_gpio.h>
0e65bfe3	38
98384c6c KG	39	#include "mpc86xx.h"
98384c6c KG	40
8c68e2f7	41	static struct device_node *pixis_node;
6f90a8bd YS	42	static unsigned char pixis_bdcfg0, pixis_arch;
6f90a8bd YS	43
c8bfa77b TT	44	/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
	45	#define CLKDVDR_PXCKEN 0x80000000
	46	#define CLKDVDR_PXCKINV 0x10000000
	47	#define CLKDVDR_PXCKDLY 0x06000000
	48	#define CLKDVDR_PXCLK_MASK 0x001F0000
	49
8c68e2f7 AV	50	#ifdef CONFIG_SUSPEND
	51	static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
	52	{
	53	pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
	54	return IRQ_HANDLED;
	55	}
	56
	57	static void __init mpc8610_suspend_init(void)
	58	{
	59	int irq;
	60	int ret;
	61
	62	if (!pixis_node)
	63	return;
	64
	65	irq = irq_of_parse_and_map(pixis_node, 0);
	66	if (!irq) {
	67	pr_err("%s: can't map pixis event IRQ.\n", __func__);
	68	return;
	69	}
	70
e0be2c21	71	ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
8c68e2f7 AV	72	if (ret) {
	73	pr_err("%s: can't request pixis event IRQ: %d\n",
	74	__func__, ret);
	75	irq_dispose_mapping(irq);
	76	}
	77
	78	enable_irq_wake(irq);
	79	}
	80	#else
	81	static inline void mpc8610_suspend_init(void) { }
	82	#endif /* CONFIG_SUSPEND */
	83
ce6d73c9	84	static const struct of_device_id mpc8610_ids[] __initconst = {
c7d24a2d	85	{ .compatible = "fsl,mpc8610-immr", },
8c68e2f7	86	{ .compatible = "fsl,mpc8610-guts", },
4c5ddd52 TT	87	/* So that the DMA channel nodes can be probed individually: */
4c5ddd52 TT	88	{ .compatible = "fsl,eloplus-dma", },
905e75c4 JH	89	/* PCI controllers */
905e75c4 JH	90	{ .compatible = "fsl,mpc8610-pci", },
c7d24a2d TT	91	{}
	92	};
	93
	94	static int __init mpc8610_declare_of_platform_devices(void)
	95	{
d2998c2c AV	96	/* Firstly, register PIXIS GPIOs. */
	97	simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
	98
8c68e2f7 AV	99	/* Enable wakeup on PIXIS' event IRQ. */
	100	mpc8610_suspend_init();
	101
4f9d6e95 AIB	102	mpc86xx_common_publish_devices();
4f9d6e95 AIB	103
c7d24a2d TT	104	/* Without this call, the SSI device driver won't get probed. */
	105	of_platform_bus_probe(NULL, mpc8610_ids, NULL);
	106
	107	return 0;
	108	}
905e75c4	109	machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
c7d24a2d	110
6f90a8bd YS	111	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
6f90a8bd YS	112
f46dad27 TT	113	/*
	114	* DIU Area Descriptor
	115	*
	116	* The MPC8610 reference manual shows the bits of the AD register in
	117	* little-endian order, which causes the BLUE_C field to be split into two
	118	* parts. To simplify the definition of the MAKE_AD() macro, we define the
	119	* fields in big-endian order and byte-swap the result.
	120	*
	121	* So even though the registers don't look like they're in the
	122	* same bit positions as they are on the P1022, the same value is written to
	123	* the AD register on the MPC8610 and on the P1022.
	124	*/
	125	#define AD_BYTE_F 0x10000000
	126	#define AD_ALPHA_C_MASK 0x0E000000
	127	#define AD_ALPHA_C_SHIFT 25
	128	#define AD_BLUE_C_MASK 0x01800000
	129	#define AD_BLUE_C_SHIFT 23
	130	#define AD_GREEN_C_MASK 0x00600000
	131	#define AD_GREEN_C_SHIFT 21
	132	#define AD_RED_C_MASK 0x00180000
	133	#define AD_RED_C_SHIFT 19
	134	#define AD_PALETTE 0x00040000
	135	#define AD_PIXEL_S_MASK 0x00030000
	136	#define AD_PIXEL_S_SHIFT 16
	137	#define AD_COMP_3_MASK 0x0000F000
	138	#define AD_COMP_3_SHIFT 12
	139	#define AD_COMP_2_MASK 0x00000F00
	140	#define AD_COMP_2_SHIFT 8
	141	#define AD_COMP_1_MASK 0x000000F0
	142	#define AD_COMP_1_SHIFT 4
	143	#define AD_COMP_0_MASK 0x0000000F
	144	#define AD_COMP_0_SHIFT 0
	145
	146	#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
	147	cpu_to_le32(AD_BYTE_F \| (alpha << AD_ALPHA_C_SHIFT) \| \
	148	(blue << AD_BLUE_C_SHIFT) \| (green << AD_GREEN_C_SHIFT) \| \
	149	(red << AD_RED_C_SHIFT) \| (c3 << AD_COMP_3_SHIFT) \| \
	150	(c2 << AD_COMP_2_SHIFT) \| (c1 << AD_COMP_1_SHIFT) \| \
	151	(c0 << AD_COMP_0_SHIFT) \| (size << AD_PIXEL_S_SHIFT))
6f90a8bd	152
7653aaab TT	153	u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
7653aaab TT	154	unsigned int bits_per_pixel)
6f90a8bd	155	{
7653aaab	156	static const u32 pixelformat[][3] = {
f46dad27 TT	157	{
	158	MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
	159	MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
	160	MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
	161	},
	162	{
	163	MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
	164	MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
	165	MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
	166	},
6f90a8bd	167	};
f46dad27	168	unsigned int arch_monitor;
6f90a8bd	169
f46dad27	170	/* The DVI port is mis-wired on revision 1 of this board. */
7653aaab TT	171	arch_monitor =
7653aaab TT	172	((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;
f46dad27 TT	173
	174	switch (bits_per_pixel) {
	175	case 32:
	176	return pixelformat[arch_monitor][0];
	177	case 24:
	178	return pixelformat[arch_monitor][1];
	179	case 16:
	180	return pixelformat[arch_monitor][2];
	181	default:
	182	pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
	183	return 0;
	184	}
6f90a8bd YS	185	}
6f90a8bd YS	186
7653aaab TT	187	void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
7653aaab TT	188	char *gamma_table_base)
6f90a8bd YS	189	{
6f90a8bd YS	190	int i;
7653aaab	191	if (port == FSL_DIU_PORT_DLVDS) {
6f90a8bd YS	192	for (i = 0; i < 256*3; i++)
	193	gamma_table_base[i] = (gamma_table_base[i] << 2) \|
	194	((gamma_table_base[i] >> 6) & 0x03);
	195	}
	196	}
	197
f637ef8e AV	198	#define PX_BRDCFG0_DVISEL (1 << 3)
	199	#define PX_BRDCFG0_DLINK (1 << 4)
	200	#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK)
	201
7653aaab	202	void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
6f90a8bd	203	{
7653aaab TT	204	switch (port) {
7653aaab TT	205	case FSL_DIU_PORT_DVI:
f637ef8e	206	clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
7653aaab TT	207	PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK);
	208	break;
	209	case FSL_DIU_PORT_LVDS:
	210	clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
	211	PX_BRDCFG0_DLINK);
	212	break;
	213	case FSL_DIU_PORT_DLVDS:
	214	clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
	215	break;
	216	}
6f90a8bd YS	217	}
6f90a8bd YS	218
c8bfa77b TT	219	/**
	220	* mpc8610hpcd_set_pixel_clock: program the DIU's clock
	221	*
	222	* @pixclock: the wavelength, in picoseconds, of the clock
	223	*/
6f90a8bd YS	224	void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
6f90a8bd YS	225	{
c8bfa77b	226	struct device_node *guts_np = NULL;
9cb6abcb	227	struct ccsr_guts __iomem *guts;
c8bfa77b TT	228	unsigned long freq;
	229	u64 temp;
	230	u32 pxclk;
	231
	232	/* Map the global utilities registers. */
	233	guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
	234	if (!guts_np) {
b6741bc7	235	pr_err("mpc8610hpcd: missing global utilities device node\n");
6f90a8bd YS	236	return;
	237	}
	238
c8bfa77b TT	239	guts = of_iomap(guts_np, 0);
	240	of_node_put(guts_np);
	241	if (!guts) {
b6741bc7	242	pr_err("mpc8610hpcd: could not map global utilities device\n");
c8bfa77b	243	return;
6f90a8bd YS	244	}
6f90a8bd YS	245
c8bfa77b TT	246	/* Convert pixclock from a wavelength to a frequency */
	247	temp = 1000000000000ULL;
	248	do_div(temp, pixclock);
	249	freq = temp;
	250
	251	/*
	252	* 'pxclk' is the ratio of the platform clock to the pixel clock.
	253	* On the MPC8610, the value programmed into CLKDVDR is the ratio
	254	* minus one. The valid range of values is 2-31.
	255	*/
	256	pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
	257	pxclk = clamp_t(u32, pxclk, 2, 31);
	258
	259	/* Disable the pixel clock, and set it to non-inverted and no delay */
	260	clrbits32(&guts->clkdvdr,
	261	CLKDVDR_PXCKEN \| CLKDVDR_PXCKDLY \| CLKDVDR_PXCLK_MASK);
	262
	263	/* Enable the clock and set the pxclk */
	264	setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN \| (pxclk << 16));
	265
	266	iounmap(guts);
6f90a8bd YS	267	}
6f90a8bd YS	268
7653aaab TT	269	enum fsl_diu_monitor_port
7653aaab TT	270	mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
6f90a8bd	271	{
7653aaab	272	return port;
6f90a8bd YS	273	}
6f90a8bd YS	274
0e65bfe3	275	#endif
6f90a8bd YS	276
	277	static void __init mpc86xx_hpcd_setup_arch(void)
	278	{
	279	struct resource r;
6f90a8bd YS	280	unsigned char *pixis;
6f90a8bd YS	281
0e65bfe3 XX	282	if (ppc_md.progress)
	283	ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
	284
905e75c4 JH	285	fsl_pci_assign_primary();
905e75c4 JH	286
6f90a8bd	287	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
6f90a8bd YS	288	diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
	289	diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
	290	diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
	291	diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
7653aaab	292	diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port;
6f90a8bd YS	293	#endif
6f90a8bd YS	294
8c68e2f7 AV	295	pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	296	if (pixis_node) {
	297	of_address_to_resource(pixis_node, 0, &r);
	298	of_node_put(pixis_node);
6f90a8bd YS	299	pixis = ioremap(r.start, 32);
	300	if (!pixis) {
	301	printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
	302	return;
	303	}
	304	pixis_bdcfg0 = pixis + 8;
	305	pixis_arch = pixis + 1;
	306	} else
	307	printk(KERN_ERR "Err: "
	308	"can't find device node 'fsl,fpga-pixis'\n");
0e65bfe3 XX	309
	310	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
	311	}
	312
	313	/*
	314	* Called very early, device-tree isn't unflattened
	315	*/
	316	static int __init mpc86xx_hpcd_probe(void)
	317	{
56571384	318	if (of_machine_is_compatible("fsl,MPC8610HPCD"))
0e65bfe3 XX	319	return 1; /* Looks good */
	320
	321	return 0;
	322	}
	323
0e65bfe3 XX	324	define_machine(mpc86xx_hpcd) {
	325	.name = "MPC86xx HPCD",
	326	.probe = mpc86xx_hpcd_probe,
	327	.setup_arch = mpc86xx_hpcd_setup_arch,
98384c6c	328	.init_IRQ = mpc86xx_init_irq,
0e65bfe3	329	.get_irq = mpic_get_irq,
0e65bfe3 XX	330	.time_init = mpc86xx_time_init,
	331	.calibrate_decr = generic_calibrate_decr,
	332	.progress = udbg_progress,
b567d1c7	333	#ifdef CONFIG_PCI
0e65bfe3	334	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
b567d1c7	335	#endif
0e65bfe3	336	};