[linux-2.6-block.git] / arch / powerpc / platforms / 86xx / mpc8610_hpcd.c

/*
 * MPC8610 HPCD board specific routines
 *
 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
 * Recode: Jason Jin <jason.jin@freescale.com>
 *         York Sun <yorksun@freescale.com>
 *
 * Rewrite the interrupt routing. remove the 8259PIC support,
 * All the integrated device in ULI use sideband interrupt.
 *
 * Copyright 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/of.h>

#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/mpc86xx.h>
#include <asm/prom.h>
#include <mm/mmu_decl.h>
#include <asm/udbg.h>

#include <asm/mpic.h>

#include <linux/of_platform.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>

static unsigned char *pixis_bdcfg0, *pixis_arch;

static struct of_device_id __initdata mpc8610_ids[] = {
	{ .compatible = "fsl,mpc8610-immr", },
	{ .compatible = "simple-bus", },
	{}
};

static int __init mpc8610_declare_of_platform_devices(void)
{
	/* Without this call, the SSI device driver won't get probed. */
	of_platform_bus_probe(NULL, mpc8610_ids, NULL);

	return 0;
}
machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);

static void __init mpc86xx_hpcd_init_irq(void)
{
	struct mpic *mpic1;
	struct device_node *np;
	struct resource res;

	/* Determine PIC address. */
	np = of_find_node_by_type(NULL, "open-pic");
	if (np == NULL)
		return;
	of_address_to_resource(np, 0, &res);

	/* Alloc mpic structure and per isu has 16 INT entries. */
	mpic1 = mpic_alloc(np, res.start,
			MPIC_PRIMARY | MPIC_WANTS_RESET |
			MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
			0, 256, " MPIC     ");
	BUG_ON(mpic1 == NULL);

	mpic_init(mpic1);
}

#ifdef CONFIG_PCI
static void __devinit quirk_uli1575(struct pci_dev *dev)
{
	u32 temp32;

	/* Disable INTx */
	pci_read_config_dword(dev, 0x48, &temp32);
	pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));

	/* Enable sideband interrupt */
	pci_read_config_dword(dev, 0x90, &temp32);
	pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
}

static void __devinit quirk_uli5288(struct pci_dev *dev)
{
	unsigned char c;
	unsigned short temp;

	/* Interrupt Disable, Needed when SATA disabled */
	pci_read_config_word(dev, PCI_COMMAND, &temp);
	temp |= 1<<10;
	pci_write_config_word(dev, PCI_COMMAND, temp);

	pci_read_config_byte(dev, 0x83, &c);
	c |= 0x80;
	pci_write_config_byte(dev, 0x83, c);

	pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
	pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);

	pci_read_config_byte(dev, 0x83, &c);
	c &= 0x7f;
	pci_write_config_byte(dev, 0x83, c);
}

/*
 * Since 8259PIC was disabled on the board, the IDE device can not
 * use the legacy IRQ, we need to let the IDE device work under
 * native mode and use the interrupt line like other PCI devices.
 * IRQ14 is a sideband interrupt from IDE device to CPU and we use this
 * as the interrupt for IDE device.
 */
static void __devinit quirk_uli5229(struct pci_dev *dev)
{
	unsigned char c;

	pci_read_config_byte(dev, 0x4b, &c);
	c |= 0x10;
	pci_write_config_byte(dev, 0x4b, c);
}

/*
 * SATA interrupt pin bug fix
 * There's a chip bug for 5288, The interrupt pin should be 2,
 * not the read only value 1, So it use INTB#, not INTA# which
 * actually used by the IDE device 5229.
 * As of this bug, during the PCI initialization, 5288 read the
 * irq of IDE device from the device tree, this function fix this
 * bug by re-assigning a correct irq to 5288.
 *
 */
static void __devinit final_uli5288(struct pci_dev *dev)
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct device_node *hosenode = hose ? hose->dn : NULL;
	struct of_irq oirq;
	int virq, pin = 2;
	u32 laddr[3];

	if (!hosenode)
		return;

	laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
	laddr[1] = laddr[2] = 0;
	of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
				     oirq.size);
	dev->irq = virq;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
#endif /* CONFIG_PCI */

#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)

static u32 get_busfreq(void)
{
	struct device_node *node;

	u32 fs_busfreq = 0;
	node = of_find_node_by_type(NULL, "cpu");
	if (node) {
		unsigned int size;
		const unsigned int *prop =
			of_get_property(node, "bus-frequency", &size);
		if (prop)
			fs_busfreq = *prop;
		of_node_put(node);
	};
	return fs_busfreq;
}

unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
						int monitor_port)
{
	static const unsigned long pixelformat[][3] = {
		{0x88882317, 0x88083218, 0x65052119},
		{0x88883316, 0x88082219, 0x65053118},
	};
	unsigned int pix_fmt, arch_monitor;

	arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
		/* DVI port for board version 0x01 */

	if (bits_per_pixel == 32)
		pix_fmt = pixelformat[arch_monitor][0];
	else if (bits_per_pixel == 24)
		pix_fmt = pixelformat[arch_monitor][1];
	else if (bits_per_pixel == 16)
		pix_fmt = pixelformat[arch_monitor][2];
	else
		pix_fmt = pixelformat[1][0];

	return pix_fmt;
}

void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
{
	int i;
	if (monitor_port == 2) {		/* dual link LVDS */
		for (i = 0; i < 256*3; i++)
			gamma_table_base[i] = (gamma_table_base[i] << 2) |
					 ((gamma_table_base[i] >> 6) & 0x03);
	}
}

#define PX_BRDCFG0_DVISEL	(1 << 3)
#define PX_BRDCFG0_DLINK	(1 << 4)
#define PX_BRDCFG0_DIU_MASK	(PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)

void mpc8610hpcd_set_monitor_port(int monitor_port)
{
	static const u8 bdcfg[] = {
		PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
		PX_BRDCFG0_DLINK,
		0,
	};

	if (monitor_port < 3)
		clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
			     bdcfg[monitor_port]);
}

void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
{
	u32 __iomem *clkdvdr;
	u32 temp;
	/* variables for pixel clock calcs */
	ulong  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
	ulong pixval;
	long err;
	int i;

	clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
	if (!clkdvdr) {
		printk(KERN_ERR "Err: can't map clock divider register!\n");
		return;
	}

	/* Pixel Clock configuration */
	pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
	speed_ccb = get_busfreq();

	/* Calculate the pixel clock with the smallest error */
	/* calculate the following in steps to avoid overflow */
	pr_debug("DIU pixclock in ps - %d\n", pixclock);
	temp = 1000000000/pixclock;
	temp *= 1000;
	pixclock = temp;
	pr_debug("DIU pixclock freq - %u\n", pixclock);

	temp = pixclock * 5 / 100;
	pr_debug("deviation = %d\n", temp);
	minpixclock = pixclock - temp;
	maxpixclock = pixclock + temp;
	pr_debug("DIU minpixclock - %lu\n", minpixclock);
	pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
	pixval = speed_ccb/pixclock;
	pr_debug("DIU pixval = %lu\n", pixval);

	err = 100000000;
	bestval = pixval;
	pr_debug("DIU bestval = %lu\n", bestval);

	bestfreq = 0;
	for (i = -1; i <= 1; i++) {
		temp = speed_ccb / ((pixval+i) + 1);
		pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
							i, pixval, temp);
		if ((temp < minpixclock) || (temp > maxpixclock))
			pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
				minpixclock, maxpixclock);
		else if (abs(temp - pixclock) < err) {
		  pr_debug("Entered the else if block %d\n", i);
			err = abs(temp - pixclock);
			bestval = pixval+i;
			bestfreq = temp;
		}
	}

	pr_debug("DIU chose = %lx\n", bestval);
	pr_debug("DIU error = %ld\n NomPixClk ", err);
	pr_debug("DIU: Best Freq = %lx\n", bestfreq);
	/* Modify PXCLK in GUTS CLKDVDR */
	pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
	temp = (*clkdvdr) & 0x2000FFFF;
	*clkdvdr = temp;		/* turn off clock */
	*clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
	pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
	iounmap(clkdvdr);
}

ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
{
	return snprintf(buf, PAGE_SIZE,
			"%c0 - DVI\n"
			"%c1 - Single link LVDS\n"
			"%c2 - Dual link LVDS\n",
			monitor_port == 0 ? '*' : ' ',
			monitor_port == 1 ? '*' : ' ',
			monitor_port == 2 ? '*' : ' ');
}

int mpc8610hpcd_set_sysfs_monitor_port(int val)
{
	return val < 3 ? val : 0;
}

#endif

static void __init mpc86xx_hpcd_setup_arch(void)
{
	struct resource r;
	struct device_node *np;
	unsigned char *pixis;

	if (ppc_md.progress)
		ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8610-pci")
		    || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == 0xa000)
				fsl_add_bridge(np, 1);
			else
				fsl_add_bridge(np, 0);
		}
        }
#endif
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
	preallocate_diu_videomemory();
	diu_ops.get_pixel_format	= mpc8610hpcd_get_pixel_format;
	diu_ops.set_gamma_table		= mpc8610hpcd_set_gamma_table;
	diu_ops.set_monitor_port	= mpc8610hpcd_set_monitor_port;
	diu_ops.set_pixel_clock		= mpc8610hpcd_set_pixel_clock;
	diu_ops.show_monitor_port	= mpc8610hpcd_show_monitor_port;
	diu_ops.set_sysfs_monitor_port	= mpc8610hpcd_set_sysfs_monitor_port;
#endif

	np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	if (np) {
		of_address_to_resource(np, 0, &r);
		of_node_put(np);
		pixis = ioremap(r.start, 32);
		if (!pixis) {
			printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
			return;
		}
		pixis_bdcfg0 = pixis + 8;
		pixis_arch = pixis + 1;
	} else
		printk(KERN_ERR "Err: "
				"can't find device node 'fsl,fpga-pixis'\n");

	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
}

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc86xx_hpcd_probe(void)
{
	unsigned long root = of_get_flat_dt_root();

	if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
		return 1;	/* Looks good */

	return 0;
}

static long __init mpc86xx_time_init(void)
{
	unsigned int temp;

	/* Set the time base to zero */
	mtspr(SPRN_TBWL, 0);
	mtspr(SPRN_TBWU, 0);

	temp = mfspr(SPRN_HID0);
	temp |= HID0_TBEN;
	mtspr(SPRN_HID0, temp);
	asm volatile("isync");

	return 0;
}

define_machine(mpc86xx_hpcd) {
	.name			= "MPC86xx HPCD",
	.probe			= mpc86xx_hpcd_probe,
	.setup_arch		= mpc86xx_hpcd_setup_arch,
	.init_IRQ		= mpc86xx_hpcd_init_irq,
	.get_irq		= mpic_get_irq,
	.restart		= fsl_rstcr_restart,
	.time_init		= mpc86xx_time_init,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
};
Commit	Line	Data
0e65bfe3 XX	1	/*
	2	* MPC8610 HPCD board specific routines
	3	*
	4	* Initial author: Xianghua Xiao <x.xiao@freescale.com>
	5	* Recode: Jason Jin <jason.jin@freescale.com>
6f90a8bd	6	* York Sun <yorksun@freescale.com>
0e65bfe3 XX	7	*
	8	* Rewrite the interrupt routing. remove the 8259PIC support,
	9	* All the integrated device in ULI use sideband interrupt.
	10	*
6f90a8bd	11	* Copyright 2008 Freescale Semiconductor Inc.
0e65bfe3 XX	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*/
	18
	19	#include <linux/stddef.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/kdev_t.h>
	23	#include <linux/delay.h>
	24	#include <linux/seq_file.h>
	25	#include <linux/of.h>
	26
	27	#include <asm/system.h>
	28	#include <asm/time.h>
	29	#include <asm/machdep.h>
	30	#include <asm/pci-bridge.h>
	31	#include <asm/mpc86xx.h>
	32	#include <asm/prom.h>
	33	#include <mm/mmu_decl.h>
	34	#include <asm/udbg.h>
	35
	36	#include <asm/mpic.h>
	37
c7d24a2d	38	#include <linux/of_platform.h>
0e65bfe3 XX	39	#include <sysdev/fsl_pci.h>
	40	#include <sysdev/fsl_soc.h>
	41
6f90a8bd YS	42	static unsigned char pixis_bdcfg0, pixis_arch;
6f90a8bd YS	43
c7d24a2d TT	44	static struct of_device_id __initdata mpc8610_ids[] = {
c7d24a2d TT	45	{ .compatible = "fsl,mpc8610-immr", },
34b4a873	46	{ .compatible = "simple-bus", },
c7d24a2d TT	47	{}
	48	};
	49
	50	static int __init mpc8610_declare_of_platform_devices(void)
	51	{
	52	/* Without this call, the SSI device driver won't get probed. */
	53	of_platform_bus_probe(NULL, mpc8610_ids, NULL);
	54
	55	return 0;
	56	}
	57	machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
	58
6f90a8bd	59	static void __init mpc86xx_hpcd_init_irq(void)
0e65bfe3 XX	60	{
	61	struct mpic *mpic1;
	62	struct device_node *np;
	63	struct resource res;
	64
	65	/* Determine PIC address. */
	66	np = of_find_node_by_type(NULL, "open-pic");
	67	if (np == NULL)
	68	return;
	69	of_address_to_resource(np, 0, &res);
	70
	71	/* Alloc mpic structure and per isu has 16 INT entries. */
	72	mpic1 = mpic_alloc(np, res.start,
0023352f JJ	73	MPIC_PRIMARY \| MPIC_WANTS_RESET \|
0023352f JJ	74	MPIC_BIG_ENDIAN \| MPIC_BROKEN_FRR_NIRQS,
0e65bfe3 XX	75	0, 256, " MPIC ");
	76	BUG_ON(mpic1 == NULL);
	77
	78	mpic_init(mpic1);
	79	}
	80
	81	#ifdef CONFIG_PCI
	82	static void __devinit quirk_uli1575(struct pci_dev *dev)
	83	{
	84	u32 temp32;
	85
	86	/* Disable INTx */
	87	pci_read_config_dword(dev, 0x48, &temp32);
	88	pci_write_config_dword(dev, 0x48, (temp32 \| 1<<26));
	89
	90	/* Enable sideband interrupt */
	91	pci_read_config_dword(dev, 0x90, &temp32);
	92	pci_write_config_dword(dev, 0x90, (temp32 \| 1<<22));
	93	}
	94
	95	static void __devinit quirk_uli5288(struct pci_dev *dev)
	96	{
	97	unsigned char c;
	98	unsigned short temp;
	99
	100	/* Interrupt Disable, Needed when SATA disabled */
	101	pci_read_config_word(dev, PCI_COMMAND, &temp);
	102	temp \|= 1<<10;
	103	pci_write_config_word(dev, PCI_COMMAND, temp);
	104
	105	pci_read_config_byte(dev, 0x83, &c);
	106	c \|= 0x80;
	107	pci_write_config_byte(dev, 0x83, c);
	108
	109	pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
	110	pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
	111
	112	pci_read_config_byte(dev, 0x83, &c);
	113	c &= 0x7f;
	114	pci_write_config_byte(dev, 0x83, c);
	115	}
	116
	117	/*
	118	* Since 8259PIC was disabled on the board, the IDE device can not
	119	* use the legacy IRQ, we need to let the IDE device work under
	120	* native mode and use the interrupt line like other PCI devices.
	121	* IRQ14 is a sideband interrupt from IDE device to CPU and we use this
	122	* as the interrupt for IDE device.
	123	*/
	124	static void __devinit quirk_uli5229(struct pci_dev *dev)
	125	{
	126	unsigned char c;
	127
	128	pci_read_config_byte(dev, 0x4b, &c);
	129	c \|= 0x10;
	130	pci_write_config_byte(dev, 0x4b, c);
	131	}
	132
	133	/*
	134	* SATA interrupt pin bug fix
	135	* There's a chip bug for 5288, The interrupt pin should be 2,
	136	* not the read only value 1, So it use INTB#, not INTA# which
	137	* actually used by the IDE device 5229.
	138	* As of this bug, during the PCI initialization, 5288 read the
139	* irq of IDE device from the device tree, this function fix this
140	* bug by re-assigning a correct irq to 5288.
141	*
142	*/
143	static void __devinit final_uli5288(struct pci_dev *dev)
144	{
145	struct pci_controller *hose = pci_bus_to_host(dev->bus);
44ef3390	146	struct device_node *hosenode = hose ? hose->dn : NULL;
0e65bfe3 XX	147	struct of_irq oirq;
	148	int virq, pin = 2;
	149	u32 laddr[3];
	150
	151	if (!hosenode)
	152	return;
	153
	154	laddr[0] = (hose->first_busno << 16) \| (PCI_DEVFN(31, 0) << 8);
	155	laddr[1] = laddr[2] = 0;
	156	of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
	157	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
	158	oirq.size);
	159	dev->irq = virq;
	160	}
	161
	162	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
	163	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
	164	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
	165	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
	166	#endif /* CONFIG_PCI */
	167
6f90a8bd YS	168	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
	169
	170	static u32 get_busfreq(void)
0e65bfe3	171	{
6f90a8bd YS	172	struct device_node *node;
	173
	174	u32 fs_busfreq = 0;
	175	node = of_find_node_by_type(NULL, "cpu");
	176	if (node) {
	177	unsigned int size;
	178	const unsigned int *prop =
	179	of_get_property(node, "bus-frequency", &size);
	180	if (prop)
	181	fs_busfreq = *prop;
	182	of_node_put(node);
	183	};
	184	return fs_busfreq;
	185	}
	186
	187	unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
	188	int monitor_port)
	189	{
	190	static const unsigned long pixelformat[][3] = {
	191	{0x88882317, 0x88083218, 0x65052119},
	192	{0x88883316, 0x88082219, 0x65053118},
	193	};
	194	unsigned int pix_fmt, arch_monitor;
	195
	196	arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
	197	/* DVI port for board version 0x01 */
	198
	199	if (bits_per_pixel == 32)
	200	pix_fmt = pixelformat[arch_monitor][0];
	201	else if (bits_per_pixel == 24)
	202	pix_fmt = pixelformat[arch_monitor][1];
	203	else if (bits_per_pixel == 16)
	204	pix_fmt = pixelformat[arch_monitor][2];
	205	else
	206	pix_fmt = pixelformat[1][0];
	207
	208	return pix_fmt;
	209	}
	210
	211	void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
	212	{
	213	int i;
	214	if (monitor_port == 2) { /* dual link LVDS */
	215	for (i = 0; i < 256*3; i++)
	216	gamma_table_base[i] = (gamma_table_base[i] << 2) \|
	217	((gamma_table_base[i] >> 6) & 0x03);
	218	}
	219	}
	220
f637ef8e AV	221	#define PX_BRDCFG0_DVISEL (1 << 3)
	222	#define PX_BRDCFG0_DLINK (1 << 4)
	223	#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK)
	224
6f90a8bd YS	225	void mpc8610hpcd_set_monitor_port(int monitor_port)
6f90a8bd YS	226	{
f637ef8e AV	227	static const u8 bdcfg[] = {
	228	PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK,
	229	PX_BRDCFG0_DLINK,
	230	0,
	231	};
	232
6f90a8bd	233	if (monitor_port < 3)
f637ef8e AV	234	clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
f637ef8e AV	235	bdcfg[monitor_port]);
6f90a8bd YS	236	}
	237
	238	void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
	239	{
	240	u32 __iomem *clkdvdr;
	241	u32 temp;
	242	/* variables for pixel clock calcs */
	243	ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
	244	ulong pixval;
	245	long err;
	246	int i;
	247
	248	clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
	249	if (!clkdvdr) {
	250	printk(KERN_ERR "Err: can't map clock divider register!\n");
	251	return;
	252	}
	253
	254	/* Pixel Clock configuration */
	255	pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
	256	speed_ccb = get_busfreq();
	257
	258	/* Calculate the pixel clock with the smallest error */
	259	/* calculate the following in steps to avoid overflow */
	260	pr_debug("DIU pixclock in ps - %d\n", pixclock);
	261	temp = 1000000000/pixclock;
	262	temp *= 1000;
	263	pixclock = temp;
	264	pr_debug("DIU pixclock freq - %u\n", pixclock);
	265
	266	temp = pixclock * 5 / 100;
	267	pr_debug("deviation = %d\n", temp);
	268	minpixclock = pixclock - temp;
	269	maxpixclock = pixclock + temp;
	270	pr_debug("DIU minpixclock - %lu\n", minpixclock);
	271	pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
	272	pixval = speed_ccb/pixclock;
	273	pr_debug("DIU pixval = %lu\n", pixval);
	274
	275	err = 100000000;
	276	bestval = pixval;
	277	pr_debug("DIU bestval = %lu\n", bestval);
	278
	279	bestfreq = 0;
	280	for (i = -1; i <= 1; i++) {
	281	temp = speed_ccb / ((pixval+i) + 1);
	282	pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
	283	i, pixval, temp);
	284	if ((temp < minpixclock) \|\| (temp > maxpixclock))
	285	pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
	286	minpixclock, maxpixclock);
	287	else if (abs(temp - pixclock) < err) {
	288	pr_debug("Entered the else if block %d\n", i);
	289	err = abs(temp - pixclock);
	290	bestval = pixval+i;
	291	bestfreq = temp;
	292	}
	293	}
	294
	295	pr_debug("DIU chose = %lx\n", bestval);
	296	pr_debug("DIU error = %ld\n NomPixClk ", err);
	297	pr_debug("DIU: Best Freq = %lx\n", bestfreq);
	298	/* Modify PXCLK in GUTS CLKDVDR */
	299	pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
300	temp = (*clkdvdr) & 0x2000FFFF;
301	clkdvdr = temp; / turn off clock */
302	*clkdvdr = temp \| 0x80000000 \| (((bestval) & 0x1F) << 16);
303	pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
304	iounmap(clkdvdr);
305	}
306
307	ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
308	{
309	return snprintf(buf, PAGE_SIZE,
310	"%c0 - DVI\n"
311	"%c1 - Single link LVDS\n"
312	"%c2 - Dual link LVDS\n",
313	monitor_port == 0 ? '*' : ' ',
314	monitor_port == 1 ? '*' : ' ',
315	monitor_port == 2 ? '*' : ' ');
316	}
317
318	int mpc8610hpcd_set_sysfs_monitor_port(int val)
319	{
320	return val < 3 ? val : 0;
321	}
322
0e65bfe3	323	#endif
6f90a8bd YS	324
	325	static void __init mpc86xx_hpcd_setup_arch(void)
	326	{
	327	struct resource r;
	328	struct device_node *np;
	329	unsigned char *pixis;
	330
0e65bfe3 XX	331	if (ppc_md.progress)
	332	ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
	333
	334	#ifdef CONFIG_PCI
	335	for_each_node_by_type(np, "pci") {
	336	if (of_device_is_compatible(np, "fsl,mpc8610-pci")
	337	\|\| of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
	338	struct resource rsrc;
	339	of_address_to_resource(np, 0, &rsrc);
	340	if ((rsrc.start & 0xfffff) == 0xa000)
	341	fsl_add_bridge(np, 1);
	342	else
	343	fsl_add_bridge(np, 0);
	344	}
	345	}
	346	#endif
6f90a8bd YS	347	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)
	348	preallocate_diu_videomemory();
	349	diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
	350	diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
	351	diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
	352	diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
	353	diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
	354	diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
	355	#endif
	356
	357	np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
	358	if (np) {
	359	of_address_to_resource(np, 0, &r);
	360	of_node_put(np);
	361	pixis = ioremap(r.start, 32);
	362	if (!pixis) {
	363	printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
	364	return;
	365	}
	366	pixis_bdcfg0 = pixis + 8;
	367	pixis_arch = pixis + 1;
	368	} else
	369	printk(KERN_ERR "Err: "
	370	"can't find device node 'fsl,fpga-pixis'\n");
0e65bfe3 XX	371
	372	printk("MPC86xx HPCD board from Freescale Semiconductor\n");
	373	}
	374
	375	/*
	376	* Called very early, device-tree isn't unflattened
	377	*/
	378	static int __init mpc86xx_hpcd_probe(void)
	379	{
	380	unsigned long root = of_get_flat_dt_root();
	381
	382	if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
	383	return 1; /* Looks good */
	384
	385	return 0;
	386	}
	387
6f90a8bd	388	static long __init mpc86xx_time_init(void)
0e65bfe3 XX	389	{
	390	unsigned int temp;
	391
	392	/* Set the time base to zero */
	393	mtspr(SPRN_TBWL, 0);
	394	mtspr(SPRN_TBWU, 0);
	395
	396	temp = mfspr(SPRN_HID0);
	397	temp \|= HID0_TBEN;
	398	mtspr(SPRN_HID0, temp);
	399	asm volatile("isync");
	400
	401	return 0;
	402	}
	403
	404	define_machine(mpc86xx_hpcd) {
	405	.name = "MPC86xx HPCD",
	406	.probe = mpc86xx_hpcd_probe,
	407	.setup_arch = mpc86xx_hpcd_setup_arch,
	408	.init_IRQ = mpc86xx_hpcd_init_irq,
	409	.get_irq = mpic_get_irq,
e1c1575f	410	.restart = fsl_rstcr_restart,
0e65bfe3 XX	411	.time_init = mpc86xx_time_init,
	412	.calibrate_decr = generic_calibrate_decr,
	413	.progress = udbg_progress,
	414	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
	415	};