projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| d5b26db2 KG |
1 | /* |
| 2 | * Author: Andy Fleming <afleming@freescale.com> | |
| 3 | * Kumar Gala <galak@kernel.crashing.org> | |
| 4 | * | |
| 5 | * Copyright 2006-2008 Freescale Semiconductor Inc. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify it | |
| 8 | * under the terms of the GNU General Public License as published by the | |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 10 | * option) any later version. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/stddef.h> | |
| 14 | #include <linux/kernel.h> | |
| 15 | #include <linux/init.h> | |
| 16 | #include <linux/delay.h> | |
| 17 | #include <linux/of.h> | |
| 18 | ||
| 19 | #include <asm/machdep.h> | |
| 20 | #include <asm/pgtable.h> | |
| 21 | #include <asm/page.h> | |
| 22 | #include <asm/mpic.h> | |
| 23 | #include <asm/cacheflush.h> | |
| 563fdd4a | 24 | #include <asm/dbell.h> |
| d5b26db2 KG |
25 | |
| 26 | #include <sysdev/fsl_soc.h> | |
| 27 | ||
| d5b26db2 KG |
28 | extern void __early_start(void); |
| 29 | ||
| 30 | #define BOOT_ENTRY_ADDR_UPPER 0 | |
| 31 | #define BOOT_ENTRY_ADDR_LOWER 1 | |
| 32 | #define BOOT_ENTRY_R3_UPPER 2 | |
| 33 | #define BOOT_ENTRY_R3_LOWER 3 | |
| 34 | #define BOOT_ENTRY_RESV 4 | |
| 35 | #define BOOT_ENTRY_PIR 5 | |
| 36 | #define BOOT_ENTRY_R6_UPPER 6 | |
| 37 | #define BOOT_ENTRY_R6_LOWER 7 | |
| 38 | #define NUM_BOOT_ENTRY 8 | |
| 39 | #define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32)) | |
| 40 | ||
| 41 | static void __init | |
| 42 | smp_85xx_kick_cpu(int nr) | |
| 43 | { | |
| 44 | unsigned long flags; | |
| 45 | const u64 *cpu_rel_addr; | |
| 46 | __iomem u32 *bptr_vaddr; | |
| 47 | struct device_node *np; | |
| 48 | int n = 0; | |
| 49 | ||
| 50 | WARN_ON (nr < 0 || nr >= NR_CPUS); | |
| 51 | ||
| 52 | pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr); | |
| 53 | ||
| d5b26db2 KG |
54 | np = of_get_cpu_node(nr, NULL); |
| 55 | cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); | |
| 56 | ||
| 57 | if (cpu_rel_addr == NULL) { | |
| 58 | printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); | |
| 59 | return; | |
| 60 | } | |
| 61 | ||
| 62 | /* Map the spin table */ | |
| 63 | bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); | |
| 64 | ||
| cb1ffb62 KG |
65 | local_irq_save(flags); |
| 66 | ||
| d5b26db2 KG |
67 | out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); |
| 68 | out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); | |
| 69 | ||
| 70 | /* Wait a bit for the CPU to ack. */ | |
| 71 | while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) | |
| 72 | mdelay(1); | |
| 73 | ||
| d5b26db2 KG |
74 | local_irq_restore(flags); |
| 75 | ||
| cb1ffb62 KG |
76 | iounmap(bptr_vaddr); |
| 77 | ||
| d5b26db2 KG |
78 | pr_debug("waited %d msecs for CPU #%d.\n", n, nr); |
| 79 | } | |
| 80 | ||
| 81 | static void __init | |
| 563fdd4a | 82 | smp_85xx_basic_setup(int cpu_nr) |
| d5b26db2 | 83 | { |
| d5b26db2 KG |
84 | /* Clear any pending timer interrupts */ |
| 85 | mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); | |
| 86 | ||
| 87 | /* Enable decrementer interrupt */ | |
| 88 | mtspr(SPRN_TCR, TCR_DIE); | |
| 89 | } | |
| 90 | ||
| 563fdd4a KG |
91 | static void __init |
| 92 | smp_85xx_setup_cpu(int cpu_nr) | |
| 93 | { | |
| 94 | mpic_setup_this_cpu(); | |
| 95 | ||
| 96 | smp_85xx_basic_setup(cpu_nr); | |
| 97 | } | |
| 98 | ||
| d5b26db2 | 99 | struct smp_ops_t smp_85xx_ops = { |
| d5b26db2 | 100 | .kick_cpu = smp_85xx_kick_cpu, |
| d5b26db2 KG |
101 | }; |
| 102 | ||
| 563fdd4a | 103 | static int __init smp_dummy_probe(void) |
| d5b26db2 | 104 | { |
| 563fdd4a KG |
105 | return NR_CPUS; |
| 106 | } | |
| 107 | ||
| 108 | void __init mpc85xx_smp_init(void) | |
| 109 | { | |
| 110 | struct device_node *np; | |
| 111 | ||
| 112 | smp_85xx_ops.message_pass = NULL; | |
| 113 | ||
| 114 | np = of_find_node_by_type(NULL, "open-pic"); | |
| 115 | if (np) { | |
| 116 | smp_85xx_ops.probe = smp_mpic_probe; | |
| 117 | smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu; | |
| 118 | smp_85xx_ops.message_pass = smp_mpic_message_pass; | |
| 119 | } else { | |
| 120 | smp_85xx_ops.probe = smp_dummy_probe; | |
| 121 | smp_85xx_ops.setup_cpu = smp_85xx_basic_setup; | |
| 122 | } | |
| 123 | ||
| 124 | if (cpu_has_feature(CPU_FTR_DBELL)) | |
| 125 | smp_85xx_ops.message_pass = smp_dbell_message_pass; | |
| 126 | ||
| 127 | BUG_ON(!smp_85xx_ops.message_pass); | |
| 128 | ||
| d5b26db2 KG |
129 | smp_ops = &smp_85xx_ops; |
| 130 | } |