Commit | Line | Data |
---|---|---|
ab2f4892 KG |
1 | /* |
2 | * Corenet based SoC DS Setup | |
3 | * | |
4 | * Maintained by Kumar Gala (see MAINTAINERS for contact information) | |
5 | * | |
b9a43342 | 6 | * Copyright 2009-2011 Freescale Semiconductor Inc. |
ab2f4892 KG |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/kdev_t.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
ab2f4892 | 19 | |
ab2f4892 KG |
20 | #include <asm/time.h> |
21 | #include <asm/machdep.h> | |
22 | #include <asm/pci-bridge.h> | |
84f44cc5 | 23 | #include <asm/pgtable.h> |
6d251ddf | 24 | #include <asm/ppc-pci.h> |
ab2f4892 KG |
25 | #include <mm/mmu_decl.h> |
26 | #include <asm/prom.h> | |
27 | #include <asm/udbg.h> | |
28 | #include <asm/mpic.h> | |
512e267f | 29 | #include <asm/ehv_pic.h> |
7aa1aa6e | 30 | #include <soc/fsl/qe/qe_ic.h> |
ab2f4892 KG |
31 | |
32 | #include <linux/of_platform.h> | |
33 | #include <sysdev/fsl_soc.h> | |
34 | #include <sysdev/fsl_pci.h> | |
582d3e09 | 35 | #include "smp.h" |
0f5a8696 | 36 | #include "mpc85xx.h" |
ab2f4892 | 37 | |
befe7c12 | 38 | void __init corenet_gen_pic_init(void) |
ab2f4892 KG |
39 | { |
40 | struct mpic *mpic; | |
e55d7f73 KM |
41 | unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | |
42 | MPIC_NO_RESET; | |
ab2f4892 | 43 | |
0f5a8696 ZQ |
44 | struct device_node *np; |
45 | ||
ab2f4892 KG |
46 | if (ppc_md.get_irq == mpic_get_coreint_irq) |
47 | flags |= MPIC_ENABLE_COREINT; | |
48 | ||
b9faa360 | 49 | mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC "); |
ab2f4892 KG |
50 | BUG_ON(mpic == NULL); |
51 | ||
52 | mpic_init(mpic); | |
0f5a8696 ZQ |
53 | |
54 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); | |
55 | if (np) { | |
56 | qe_ic_init(np, 0, qe_ic_cascade_low_mpic, | |
57 | qe_ic_cascade_high_mpic); | |
58 | of_node_put(np); | |
59 | } | |
ab2f4892 KG |
60 | } |
61 | ||
ab2f4892 KG |
62 | /* |
63 | * Setup the architecture | |
64 | */ | |
befe7c12 | 65 | void __init corenet_gen_setup_arch(void) |
ab2f4892 | 66 | { |
ab2f4892 | 67 | mpc85xx_smp_init(); |
ab2f4892 | 68 | |
905e75c4 JH |
69 | swiotlb_detect_4g(); |
70 | ||
84f44cc5 SW |
71 | #if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32) |
72 | /* | |
73 | * Inbound windows don't cover the full lower 4 GiB | |
74 | * due to conflicts with PCICSRBAR and outbound windows, | |
75 | * so limit the DMA32 zone to 2 GiB, to allow consistent | |
76 | * allocations to succeed. | |
77 | */ | |
78 | limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT)); | |
79 | #endif | |
80 | ||
497c8b60 | 81 | pr_info("%s board\n", ppc_md.name); |
0f5a8696 ZQ |
82 | |
83 | mpc85xx_qe_init(); | |
ab2f4892 KG |
84 | } |
85 | ||
cad5cef6 | 86 | static const struct of_device_id of_device_ids[] = { |
ab2f4892 KG |
87 | { |
88 | .compatible = "simple-bus" | |
89 | }, | |
a189243c AF |
90 | { |
91 | .compatible = "mdio-mux-gpio" | |
92 | }, | |
2e6e9966 SK |
93 | { |
94 | .compatible = "fsl,fpga-ngpixis" | |
95 | }, | |
96 | { | |
97 | .compatible = "fsl,fpga-qixis" | |
98 | }, | |
ab2f4892 | 99 | { |
077200cb | 100 | .compatible = "fsl,srio", |
ab2f4892 | 101 | }, |
b9a43342 KG |
102 | { |
103 | .compatible = "fsl,p4080-pcie", | |
104 | }, | |
105 | { | |
106 | .compatible = "fsl,qoriq-pcie-v2.2", | |
107 | }, | |
4c30c143 TT |
108 | { |
109 | .compatible = "fsl,qoriq-pcie-v2.3", | |
110 | }, | |
111 | { | |
112 | .compatible = "fsl,qoriq-pcie-v2.4", | |
113 | }, | |
b9faa360 KG |
114 | { |
115 | .compatible = "fsl,qoriq-pcie-v3.0", | |
116 | }, | |
0f5a8696 ZQ |
117 | { |
118 | .compatible = "fsl,qe", | |
119 | }, | |
7dea9ec5 IL |
120 | { |
121 | .compatible = "fsl,fman", | |
122 | }, | |
3907ab26 TT |
123 | /* The following two are for the Freescale hypervisor */ |
124 | { | |
125 | .name = "hypervisor", | |
126 | }, | |
127 | { | |
128 | .name = "handles", | |
129 | }, | |
ab2f4892 KG |
130 | {} |
131 | }; | |
132 | ||
befe7c12 | 133 | int __init corenet_gen_publish_devices(void) |
ab2f4892 KG |
134 | { |
135 | return of_platform_bus_probe(NULL, of_device_ids, NULL); | |
136 | } | |
512e267f KH |
137 | |
138 | static const char * const boards[] __initconst = { | |
139 | "fsl,P2041RDB", | |
140 | "fsl,P3041DS", | |
2b09c603 | 141 | "fsl,OCA4080", |
512e267f KH |
142 | "fsl,P4080DS", |
143 | "fsl,P5020DS", | |
144 | "fsl,P5040DS", | |
4c18be2b | 145 | "fsl,T2080QDS", |
78eb9094 | 146 | "fsl,T2080RDB", |
4c18be2b | 147 | "fsl,T2081QDS", |
512e267f | 148 | "fsl,T4240QDS", |
36a2a09d | 149 | "fsl,T4240RDB", |
512e267f KH |
150 | "fsl,B4860QDS", |
151 | "fsl,B4420QDS", | |
152 | "fsl,B4220QDS", | |
65bf2a05 | 153 | "fsl,T1023RDB", |
2b6029e2 | 154 | "fsl,T1024QDS", |
5afe13fd | 155 | "fsl,T1024RDB", |
0d748ec5 PJ |
156 | "fsl,T1040D4RDB", |
157 | "fsl,T1042D4RDB", | |
0c0fc4d3 PK |
158 | "fsl,T1040QDS", |
159 | "fsl,T1042QDS", | |
0babcd1c PJ |
160 | "fsl,T1040RDB", |
161 | "fsl,T1042RDB", | |
667680f6 | 162 | "fsl,T1042RDB_PI", |
497c8b60 | 163 | "keymile,kmcoge4", |
c383ee84 | 164 | "varisys,CYRUS", |
512e267f KH |
165 | NULL |
166 | }; | |
167 | ||
512e267f KH |
168 | /* |
169 | * Called very early, device-tree isn't unflattened | |
170 | */ | |
171 | static int __init corenet_generic_probe(void) | |
172 | { | |
173 | unsigned long root = of_get_flat_dt_root(); | |
cd115477 LT |
174 | char hv_compat[24]; |
175 | int i; | |
512e267f KH |
176 | #ifdef CONFIG_SMP |
177 | extern struct smp_ops_t smp_85xx_ops; | |
178 | #endif | |
179 | ||
180 | if (of_flat_dt_match(root, boards)) | |
181 | return 1; | |
182 | ||
183 | /* Check if we're running under the Freescale hypervisor */ | |
cd115477 LT |
184 | for (i = 0; boards[i]; i++) { |
185 | snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]); | |
186 | if (of_flat_dt_is_compatible(root, hv_compat)) { | |
187 | ppc_md.init_IRQ = ehv_pic_init; | |
188 | ||
189 | ppc_md.get_irq = ehv_pic_get_irq; | |
190 | ppc_md.restart = fsl_hv_restart; | |
9178ba29 | 191 | pm_power_off = fsl_hv_halt; |
cd115477 | 192 | ppc_md.halt = fsl_hv_halt; |
512e267f | 193 | #ifdef CONFIG_SMP |
cd115477 LT |
194 | /* |
195 | * Disable the timebase sync operations because we | |
196 | * can't write to the timebase registers under the | |
197 | * hypervisor. | |
198 | */ | |
199 | smp_85xx_ops.give_timebase = NULL; | |
200 | smp_85xx_ops.take_timebase = NULL; | |
512e267f | 201 | #endif |
cd115477 LT |
202 | return 1; |
203 | } | |
512e267f KH |
204 | } |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
209 | define_machine(corenet_generic) { | |
210 | .name = "CoreNet Generic", | |
211 | .probe = corenet_generic_probe, | |
befe7c12 KH |
212 | .setup_arch = corenet_gen_setup_arch, |
213 | .init_IRQ = corenet_gen_pic_init, | |
512e267f KH |
214 | #ifdef CONFIG_PCI |
215 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
48b16180 | 216 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, |
512e267f | 217 | #endif |
881ea7d3 | 218 | /* |
9f640bf5 | 219 | * Core reset may cause issues if using the proxy mode of MPIC. |
881ea7d3 | 220 | * So, use the mixed mode of MPIC if enabling CPU hotplug. |
9f640bf5 SW |
221 | * |
222 | * Likewise, problems have been seen with kexec when coreint is enabled. | |
881ea7d3 | 223 | */ |
9f640bf5 | 224 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC) |
881ea7d3 | 225 | .get_irq = mpic_get_irq, |
226 | #else | |
512e267f | 227 | .get_irq = mpic_get_coreint_irq, |
881ea7d3 | 228 | #endif |
512e267f KH |
229 | .restart = fsl_rstcr_restart, |
230 | .calibrate_decr = generic_calibrate_decr, | |
231 | .progress = udbg_progress, | |
232 | #ifdef CONFIG_PPC64 | |
233 | .power_save = book3e_idle, | |
234 | #else | |
235 | .power_save = e500_idle, | |
236 | #endif | |
237 | }; | |
238 | ||
befe7c12 | 239 | machine_arch_initcall(corenet_generic, corenet_gen_publish_devices); |
512e267f KH |
240 | |
241 | #ifdef CONFIG_SWIOTLB | |
242 | machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier); | |
243 | #endif |