[linux-2.6-block.git] / arch / powerpc / platforms / 82xx / pq2ads-pci-pic.c

/*
 * PQ2 ADS-style PCI interrupt controller
 *
 * Copyright 2007 Freescale Semiconductor, Inc.
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
 * Copyright (c) 2006 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/bootmem.h>
#include <linux/slab.h>

#include <asm/io.h>
#include <asm/prom.h>
#include <asm/cpm2.h>

#include "pq2.h"

static DEFINE_RAW_SPINLOCK(pci_pic_lock);

struct pq2ads_pci_pic {
	struct device_node *node;
	struct irq_domain *host;

	struct {
		u32 stat;
		u32 mask;
	} __iomem *regs;
};

#define NUM_IRQS 32

static void pq2ads_pci_mask_irq(struct irq_data *d)
{
	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;

	if (irq != -1) {
		unsigned long flags;
		raw_spin_lock_irqsave(&pci_pic_lock, flags);

		setbits32(&priv->regs->mask, 1 << irq);
		mb();

		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
	}
}

static void pq2ads_pci_unmask_irq(struct irq_data *d)
{
	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;

	if (irq != -1) {
		unsigned long flags;

		raw_spin_lock_irqsave(&pci_pic_lock, flags);
		clrbits32(&priv->regs->mask, 1 << irq);
		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
	}
}

static struct irq_chip pq2ads_pci_ic = {
	.name = "PQ2 ADS PCI",
	.irq_mask = pq2ads_pci_mask_irq,
	.irq_mask_ack = pq2ads_pci_mask_irq,
	.irq_ack = pq2ads_pci_mask_irq,
	.irq_unmask = pq2ads_pci_unmask_irq,
	.irq_enable = pq2ads_pci_unmask_irq,
	.irq_disable = pq2ads_pci_mask_irq
};

static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
	u32 stat, mask, pend;
	int bit;

	for (;;) {
		stat = in_be32(&priv->regs->stat);
		mask = in_be32(&priv->regs->mask);

		pend = stat & ~mask;

		if (!pend)
			break;

		for (bit = 0; pend != 0; ++bit, pend <<= 1) {
			if (pend & 0x80000000) {
				int virq = irq_linear_revmap(priv->host, bit);
				generic_handle_irq(virq);
			}
		}
	}
}

static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
			    irq_hw_number_t hw)
{
	irq_set_status_flags(virq, IRQ_LEVEL);
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
	return 0;
}

static struct irq_domain_ops pci_pic_host_ops = {
	.map = pci_pic_host_map,
};

int __init pq2ads_pci_init_irq(void)
{
	struct pq2ads_pci_pic *priv;
	struct irq_domain *host;
	struct device_node *np;
	int ret = -ENODEV;
	int irq;

	np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
	if (!np) {
		printk(KERN_ERR "No pci pic node in device tree.\n");
		of_node_put(np);
		goto out;
	}

	irq = irq_of_parse_and_map(np, 0);
	if (irq == NO_IRQ) {
		printk(KERN_ERR "No interrupt in pci pic node.\n");
		of_node_put(np);
		goto out;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		of_node_put(np);
		ret = -ENOMEM;
		goto out_unmap_irq;
	}

	/* PCI interrupt controller registers: status and mask */
	priv->regs = of_iomap(np, 0);
	if (!priv->regs) {
		printk(KERN_ERR "Cannot map PCI PIC registers.\n");
		goto out_free_bootmem;
	}

	/* mask all PCI interrupts */
	out_be32(&priv->regs->mask, ~0);
	mb();

	host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
	if (!host) {
		ret = -ENOMEM;
		goto out_unmap_regs;
	}

	priv->host = host;
	irq_set_handler_data(irq, priv);
	irq_set_chained_handler(irq, pq2ads_pci_irq_demux);

	of_node_put(np);
	return 0;

out_unmap_regs:
	iounmap(priv->regs);
out_free_bootmem:
	free_bootmem((unsigned long)priv,
	             sizeof(struct pq2ads_pci_pic));
	of_node_put(np);
out_unmap_irq:
	irq_dispose_mapping(irq);
out:
	return ret;
}
Commit	Line	Data
e00c5498 SW	1	/*
	2	* PQ2 ADS-style PCI interrupt controller
	3	*
	4	* Copyright 2007 Freescale Semiconductor, Inc.
	5	* Author: Scott Wood <scottwood@freescale.com>
	6	*
	7	* Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
	8	* Copyright (c) 2006 MontaVista Software, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/irq.h>
	18	#include <linux/types.h>
	19	#include <linux/bootmem.h>
5a0e3ad6	20	#include <linux/slab.h>
e00c5498 SW	21
	22	#include <asm/io.h>
	23	#include <asm/prom.h>
	24	#include <asm/cpm2.h>
	25
	26	#include "pq2.h"
	27
0e5d359c	28	static DEFINE_RAW_SPINLOCK(pci_pic_lock);
e00c5498 SW	29
	30	struct pq2ads_pci_pic {
	31	struct device_node *node;
bae1d8f1	32	struct irq_domain *host;
e00c5498 SW	33
	34	struct {
	35	u32 stat;
	36	u32 mask;
	37	} __iomem *regs;
	38	};
	39
	40	#define NUM_IRQS 32
	41
e4891eb0	42	static void pq2ads_pci_mask_irq(struct irq_data *d)
e00c5498	43	{
e4891eb0	44	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
476eb491	45	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
e00c5498 SW	46
	47	if (irq != -1) {
	48	unsigned long flags;
0e5d359c	49	raw_spin_lock_irqsave(&pci_pic_lock, flags);
e00c5498 SW	50
	51	setbits32(&priv->regs->mask, 1 << irq);
	52	mb();
	53
0e5d359c	54	raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
e00c5498 SW	55	}
	56	}
	57
e4891eb0	58	static void pq2ads_pci_unmask_irq(struct irq_data *d)
e00c5498	59	{
e4891eb0	60	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
476eb491	61	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
e00c5498 SW	62
	63	if (irq != -1) {
	64	unsigned long flags;
	65
0e5d359c	66	raw_spin_lock_irqsave(&pci_pic_lock, flags);
e00c5498	67	clrbits32(&priv->regs->mask, 1 << irq);
0e5d359c	68	raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
e00c5498 SW	69	}
	70	}
	71
	72	static struct irq_chip pq2ads_pci_ic = {
e00c5498	73	.name = "PQ2 ADS PCI",
e4891eb0 LB	74	.irq_mask = pq2ads_pci_mask_irq,
	75	.irq_mask_ack = pq2ads_pci_mask_irq,
	76	.irq_ack = pq2ads_pci_mask_irq,
	77	.irq_unmask = pq2ads_pci_unmask_irq,
	78	.irq_enable = pq2ads_pci_unmask_irq,
	79	.irq_disable = pq2ads_pci_mask_irq
e00c5498 SW	80	};
	81
	82	static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
	83	{
ec775d0e	84	struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
e00c5498 SW	85	u32 stat, mask, pend;
	86	int bit;
	87
	88	for (;;) {
	89	stat = in_be32(&priv->regs->stat);
	90	mask = in_be32(&priv->regs->mask);
	91
	92	pend = stat & ~mask;
	93
	94	if (!pend)
	95	break;
	96
	97	for (bit = 0; pend != 0; ++bit, pend <<= 1) {
	98	if (pend & 0x80000000) {
	99	int virq = irq_linear_revmap(priv->host, bit);
	100	generic_handle_irq(virq);
	101	}
	102	}
	103	}
	104	}
	105
bae1d8f1	106	static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
e00c5498 SW	107	irq_hw_number_t hw)
e00c5498 SW	108	{
98488db9	109	irq_set_status_flags(virq, IRQ_LEVEL);
ec775d0e TG	110	irq_set_chip_data(virq, h->host_data);
ec775d0e TG	111	irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
e00c5498 SW	112	return 0;
	113	}
	114
bae1d8f1	115	static struct irq_domain_ops pci_pic_host_ops = {
e00c5498	116	.map = pci_pic_host_map,
e00c5498 SW	117	};
	118
	119	int __init pq2ads_pci_init_irq(void)
	120	{
	121	struct pq2ads_pci_pic *priv;
bae1d8f1	122	struct irq_domain *host;
e00c5498 SW	123	struct device_node *np;
	124	int ret = -ENODEV;
	125	int irq;
	126
	127	np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
	128	if (!np) {
	129	printk(KERN_ERR "No pci pic node in device tree.\n");
	130	of_node_put(np);
	131	goto out;
	132	}
	133
	134	irq = irq_of_parse_and_map(np, 0);
	135	if (irq == NO_IRQ) {
	136	printk(KERN_ERR "No interrupt in pci pic node.\n");
	137	of_node_put(np);
	138	goto out;
	139	}
	140
ea96025a	141	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
e00c5498 SW	142	if (!priv) {
	143	of_node_put(np);
	144	ret = -ENOMEM;
	145	goto out_unmap_irq;
	146	}
	147
	148	/* PCI interrupt controller registers: status and mask */
	149	priv->regs = of_iomap(np, 0);
	150	if (!priv->regs) {
	151	printk(KERN_ERR "Cannot map PCI PIC registers.\n");
	152	goto out_free_bootmem;
	153	}
	154
	155	/* mask all PCI interrupts */
	156	out_be32(&priv->regs->mask, ~0);
	157	mb();
	158
a8db8cf0	159	host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
e00c5498 SW	160	if (!host) {
	161	ret = -ENOMEM;
	162	goto out_unmap_regs;
	163	}
	164
e00c5498	165	priv->host = host;
ec775d0e TG	166	irq_set_handler_data(irq, priv);
ec775d0e TG	167	irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
e00c5498 SW	168
	169	of_node_put(np);
	170	return 0;
	171
	172	out_unmap_regs:
	173	iounmap(priv->regs);
	174	out_free_bootmem:
	175	free_bootmem((unsigned long)priv,
08c6e3a5	176	sizeof(struct pq2ads_pci_pic));
e00c5498 SW	177	of_node_put(np);
	178	out_unmap_irq:
	179	irq_dispose_mapping(irq);
	180	out:
	181	return ret;
	182	}