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0f6c95dc ND |
1 | /* |
2 | * | |
3 | * Programmable Interrupt Controller functions for the Freescale MPC52xx. | |
4 | * | |
bcb73f56 | 5 | * Copyright (C) 2008 Secret Lab Technologies Ltd. |
0f6c95dc | 6 | * Copyright (C) 2006 bplan GmbH |
bcb73f56 GL |
7 | * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> |
8 | * Copyright (C) 2003 Montavista Software, Inc | |
0f6c95dc ND |
9 | * |
10 | * Based on the code from the 2.4 kernel by | |
11 | * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg. | |
12 | * | |
0f6c95dc ND |
13 | * This file is licensed under the terms of the GNU General Public License |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | * | |
17 | */ | |
18 | ||
bcb73f56 GL |
19 | /* |
20 | * This is the device driver for the MPC5200 interrupt controller. | |
21 | * | |
22 | * hardware overview | |
23 | * ----------------- | |
24 | * The MPC5200 interrupt controller groups the all interrupt sources into | |
25 | * three groups called 'critical', 'main', and 'peripheral'. The critical | |
26 | * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep | |
27 | * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC, | |
28 | * gpios, and the general purpose timers. Peripheral group contains the | |
29 | * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet, | |
30 | * USB, DMA, etc). | |
31 | * | |
32 | * virqs | |
33 | * ----- | |
34 | * The Linux IRQ subsystem requires that each irq source be assigned a | |
35 | * system wide unique IRQ number starting at 1 (0 means no irq). Since | |
36 | * systems can have multiple interrupt controllers, the virtual IRQ (virq) | |
37 | * infrastructure lets each interrupt controller to define a local set | |
38 | * of IRQ numbers and the virq infrastructure maps those numbers into | |
39 | * a unique range of the global IRQ# space. | |
40 | * | |
41 | * To define a range of virq numbers for this controller, this driver first | |
42 | * assigns a number to each of the irq groups (called the level 1 or L1 | |
43 | * value). Within each group individual irq sources are also assigned a | |
44 | * number, as defined by the MPC5200 user guide, and refers to it as the | |
45 | * level 2 or L2 value. The virq number is determined by shifting up the | |
46 | * L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value. | |
47 | * | |
48 | * For example, the TMR0 interrupt is irq 9 in the main group. The | |
49 | * virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9). | |
50 | * | |
51 | * The observant reader will also notice that this driver defines a 4th | |
52 | * interrupt group called 'bestcomm'. The bestcomm group isn't physically | |
53 | * part of the MPC5200 interrupt controller, but it is used here to assign | |
54 | * a separate virq number for each bestcomm task (since any of the 16 | |
55 | * bestcomm tasks can cause the bestcomm interrupt to be raised). When a | |
56 | * bestcomm interrupt occurs (peripheral group, irq 0) this driver determines | |
57 | * which task needs servicing and returns the irq number for that task. This | |
58 | * allows drivers which use bestcomm to define their own interrupt handlers. | |
59 | * | |
60 | * irq_chip structures | |
61 | * ------------------- | |
62 | * For actually manipulating IRQs (masking, enabling, clearing, etc) this | |
63 | * driver defines four separate 'irq_chip' structures, one for the main | |
64 | * group, one for the peripherals group, one for the bestcomm group and one | |
65 | * for external interrupts. The irq_chip structures provide the hooks needed | |
66 | * to manipulate each IRQ source, and since each group is has a separate set | |
67 | * of registers for controlling the irq, it makes sense to divide up the | |
68 | * hooks along those lines. | |
69 | * | |
70 | * You'll notice that there is not an irq_chip for the critical group and | |
71 | * you'll also notice that there is an irq_chip defined for external | |
72 | * interrupts even though there is no external interrupt group. The reason | |
73 | * for this is that the four external interrupts are all managed with the same | |
74 | * register even though one of the external IRQs is in the critical group and | |
75 | * the other three are in the main group. For this reason it makes sense for | |
76 | * the 4 external irqs to be managed using a separate set of hooks. The | |
77 | * reason there is no crit irq_chip is that of the 3 irqs in the critical | |
78 | * group, only external interrupt is actually support at this time by this | |
79 | * driver and since external interrupt is the only one used, it can just | |
80 | * be directed to make use of the external irq irq_chip. | |
81 | * | |
82 | * device tree bindings | |
83 | * -------------------- | |
84 | * The device tree bindings for this controller reflect the two level | |
85 | * organization of irqs in the device. #interrupt-cells = <3> where the | |
86 | * first cell is the group number [0..3], the second cell is the irq | |
87 | * number in the group, and the third cell is the sense type (level/edge). | |
88 | * For reference, the following is a list of the interrupt property values | |
89 | * associated with external interrupt sources on the MPC5200 (just because | |
90 | * it is non-obvious to determine what the interrupts property should be | |
91 | * when reading the mpc5200 manual and it is a frequently asked question). | |
92 | * | |
93 | * External interrupts: | |
94 | * <0 0 n> external irq0, n is sense (n=0: level high, | |
95 | * <1 1 n> external irq1, n is sense n=1: edge rising, | |
96 | * <1 2 n> external irq2, n is sense n=2: edge falling, | |
97 | * <1 3 n> external irq3, n is sense n=3: level low) | |
98 | */ | |
0f6c95dc ND |
99 | #undef DEBUG |
100 | ||
f800ab44 | 101 | #include <linux/interrupt.h> |
0f6c95dc | 102 | #include <linux/irq.h> |
9fe2e796 | 103 | #include <linux/of.h> |
0f6c95dc | 104 | #include <asm/io.h> |
0f6c95dc ND |
105 | #include <asm/prom.h> |
106 | #include <asm/mpc52xx.h> | |
107 | ||
bcb73f56 GL |
108 | /* HW IRQ mapping */ |
109 | #define MPC52xx_IRQ_L1_CRIT (0) | |
110 | #define MPC52xx_IRQ_L1_MAIN (1) | |
111 | #define MPC52xx_IRQ_L1_PERP (2) | |
112 | #define MPC52xx_IRQ_L1_SDMA (3) | |
113 | ||
114 | #define MPC52xx_IRQ_L1_OFFSET (6) | |
115 | #define MPC52xx_IRQ_L1_MASK (0x00c0) | |
116 | #define MPC52xx_IRQ_L2_MASK (0x003f) | |
117 | ||
118 | #define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0) | |
119 | ||
0f6c95dc | 120 | |
66ffbe49 GL |
121 | /* MPC5200 device tree match tables */ |
122 | static struct of_device_id mpc52xx_pic_ids[] __initdata = { | |
123 | { .compatible = "fsl,mpc5200-pic", }, | |
124 | { .compatible = "mpc5200-pic", }, | |
125 | {} | |
126 | }; | |
127 | static struct of_device_id mpc52xx_sdma_ids[] __initdata = { | |
128 | { .compatible = "fsl,mpc5200-bestcomm", }, | |
129 | { .compatible = "mpc5200-bestcomm", }, | |
130 | {} | |
131 | }; | |
132 | ||
0f6c95dc ND |
133 | static struct mpc52xx_intr __iomem *intr; |
134 | static struct mpc52xx_sdma __iomem *sdma; | |
135 | static struct irq_host *mpc52xx_irqhost = NULL; | |
136 | ||
137 | static unsigned char mpc52xx_map_senses[4] = { | |
138 | IRQ_TYPE_LEVEL_HIGH, | |
139 | IRQ_TYPE_EDGE_RISING, | |
140 | IRQ_TYPE_EDGE_FALLING, | |
141 | IRQ_TYPE_LEVEL_LOW, | |
142 | }; | |
143 | ||
bcb73f56 | 144 | /* Utility functions */ |
6065170c | 145 | static inline void io_be_setbit(u32 __iomem *addr, int bitno) |
0f6c95dc ND |
146 | { |
147 | out_be32(addr, in_be32(addr) | (1 << bitno)); | |
148 | } | |
149 | ||
6065170c | 150 | static inline void io_be_clrbit(u32 __iomem *addr, int bitno) |
0f6c95dc ND |
151 | { |
152 | out_be32(addr, in_be32(addr) & ~(1 << bitno)); | |
153 | } | |
154 | ||
155 | /* | |
156 | * IRQ[0-3] interrupt irq_chip | |
bcb73f56 | 157 | */ |
0f6c95dc ND |
158 | static void mpc52xx_extirq_mask(unsigned int virq) |
159 | { | |
160 | int irq; | |
161 | int l2irq; | |
162 | ||
163 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 164 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
165 | |
166 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
167 | ||
168 | io_be_clrbit(&intr->ctrl, 11 - l2irq); | |
169 | } | |
170 | ||
171 | static void mpc52xx_extirq_unmask(unsigned int virq) | |
172 | { | |
173 | int irq; | |
174 | int l2irq; | |
175 | ||
176 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 177 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
178 | |
179 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
180 | ||
181 | io_be_setbit(&intr->ctrl, 11 - l2irq); | |
182 | } | |
183 | ||
184 | static void mpc52xx_extirq_ack(unsigned int virq) | |
185 | { | |
186 | int irq; | |
187 | int l2irq; | |
188 | ||
189 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 190 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
191 | |
192 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
193 | ||
6065170c | 194 | io_be_setbit(&intr->ctrl, 27-l2irq); |
0f6c95dc ND |
195 | } |
196 | ||
f800ab44 SH |
197 | static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) |
198 | { | |
199 | u32 ctrl_reg, type; | |
200 | int irq; | |
201 | int l2irq; | |
202 | ||
203 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 204 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
f800ab44 SH |
205 | |
206 | pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type); | |
207 | ||
208 | switch (flow_type) { | |
209 | case IRQF_TRIGGER_HIGH: | |
210 | type = 0; | |
211 | break; | |
212 | case IRQF_TRIGGER_RISING: | |
213 | type = 1; | |
214 | break; | |
215 | case IRQF_TRIGGER_FALLING: | |
216 | type = 2; | |
217 | break; | |
218 | case IRQF_TRIGGER_LOW: | |
219 | type = 3; | |
220 | break; | |
221 | default: | |
222 | type = 0; | |
223 | } | |
224 | ||
225 | ctrl_reg = in_be32(&intr->ctrl); | |
226 | ctrl_reg &= ~(0x3 << (22 - (l2irq * 2))); | |
227 | ctrl_reg |= (type << (22 - (l2irq * 2))); | |
228 | out_be32(&intr->ctrl, ctrl_reg); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
0f6c95dc ND |
233 | static struct irq_chip mpc52xx_extirq_irqchip = { |
234 | .typename = " MPC52xx IRQ[0-3] ", | |
235 | .mask = mpc52xx_extirq_mask, | |
236 | .unmask = mpc52xx_extirq_unmask, | |
237 | .ack = mpc52xx_extirq_ack, | |
f800ab44 | 238 | .set_type = mpc52xx_extirq_set_type, |
0f6c95dc ND |
239 | }; |
240 | ||
241 | /* | |
242 | * Main interrupt irq_chip | |
bcb73f56 | 243 | */ |
0f6c95dc ND |
244 | static void mpc52xx_main_mask(unsigned int virq) |
245 | { | |
246 | int irq; | |
247 | int l2irq; | |
248 | ||
249 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 250 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
251 | |
252 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
253 | ||
22132178 | 254 | io_be_setbit(&intr->main_mask, 16 - l2irq); |
0f6c95dc ND |
255 | } |
256 | ||
257 | static void mpc52xx_main_unmask(unsigned int virq) | |
258 | { | |
259 | int irq; | |
260 | int l2irq; | |
261 | ||
262 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 263 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
264 | |
265 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
266 | ||
22132178 | 267 | io_be_clrbit(&intr->main_mask, 16 - l2irq); |
0f6c95dc ND |
268 | } |
269 | ||
270 | static struct irq_chip mpc52xx_main_irqchip = { | |
271 | .typename = "MPC52xx Main", | |
272 | .mask = mpc52xx_main_mask, | |
273 | .mask_ack = mpc52xx_main_mask, | |
274 | .unmask = mpc52xx_main_unmask, | |
275 | }; | |
276 | ||
277 | /* | |
278 | * Peripherals interrupt irq_chip | |
bcb73f56 | 279 | */ |
0f6c95dc ND |
280 | static void mpc52xx_periph_mask(unsigned int virq) |
281 | { | |
282 | int irq; | |
283 | int l2irq; | |
284 | ||
285 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 286 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
287 | |
288 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
289 | ||
290 | io_be_setbit(&intr->per_mask, 31 - l2irq); | |
291 | } | |
292 | ||
293 | static void mpc52xx_periph_unmask(unsigned int virq) | |
294 | { | |
295 | int irq; | |
296 | int l2irq; | |
297 | ||
298 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 299 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
300 | |
301 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
302 | ||
303 | io_be_clrbit(&intr->per_mask, 31 - l2irq); | |
304 | } | |
305 | ||
306 | static struct irq_chip mpc52xx_periph_irqchip = { | |
307 | .typename = "MPC52xx Peripherals", | |
308 | .mask = mpc52xx_periph_mask, | |
309 | .mask_ack = mpc52xx_periph_mask, | |
310 | .unmask = mpc52xx_periph_unmask, | |
311 | }; | |
312 | ||
313 | /* | |
314 | * SDMA interrupt irq_chip | |
bcb73f56 | 315 | */ |
0f6c95dc ND |
316 | static void mpc52xx_sdma_mask(unsigned int virq) |
317 | { | |
318 | int irq; | |
319 | int l2irq; | |
320 | ||
321 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 322 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
323 | |
324 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
325 | ||
326 | io_be_setbit(&sdma->IntMask, l2irq); | |
327 | } | |
328 | ||
329 | static void mpc52xx_sdma_unmask(unsigned int virq) | |
330 | { | |
331 | int irq; | |
332 | int l2irq; | |
333 | ||
334 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 335 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
336 | |
337 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
338 | ||
339 | io_be_clrbit(&sdma->IntMask, l2irq); | |
340 | } | |
341 | ||
342 | static void mpc52xx_sdma_ack(unsigned int virq) | |
343 | { | |
344 | int irq; | |
345 | int l2irq; | |
346 | ||
347 | irq = irq_map[virq].hwirq; | |
bcb73f56 | 348 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
349 | |
350 | pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq); | |
351 | ||
352 | out_be32(&sdma->IntPend, 1 << l2irq); | |
353 | } | |
354 | ||
355 | static struct irq_chip mpc52xx_sdma_irqchip = { | |
356 | .typename = "MPC52xx SDMA", | |
357 | .mask = mpc52xx_sdma_mask, | |
358 | .unmask = mpc52xx_sdma_unmask, | |
359 | .ack = mpc52xx_sdma_ack, | |
360 | }; | |
361 | ||
bcb73f56 GL |
362 | /** |
363 | * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property | |
364 | */ | |
0f6c95dc | 365 | static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, |
bcb73f56 GL |
366 | u32 *intspec, unsigned int intsize, |
367 | irq_hw_number_t *out_hwirq, | |
0f6c95dc ND |
368 | unsigned int *out_flags) |
369 | { | |
370 | int intrvect_l1; | |
371 | int intrvect_l2; | |
372 | int intrvect_type; | |
373 | int intrvect_linux; | |
374 | ||
375 | if (intsize != 3) | |
376 | return -1; | |
377 | ||
378 | intrvect_l1 = (int)intspec[0]; | |
379 | intrvect_l2 = (int)intspec[1]; | |
380 | intrvect_type = (int)intspec[2]; | |
381 | ||
bcb73f56 GL |
382 | intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & |
383 | MPC52xx_IRQ_L1_MASK; | |
384 | intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK; | |
0f6c95dc ND |
385 | |
386 | pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1, | |
387 | intrvect_l2); | |
388 | ||
389 | *out_hwirq = intrvect_linux; | |
390 | *out_flags = mpc52xx_map_senses[intrvect_type]; | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
bcb73f56 GL |
395 | /** |
396 | * mpc52xx_irqx_gettype - determine the IRQ sense type (level/edge) | |
397 | * | |
398 | * Only external IRQs need this. | |
399 | */ | |
0f6c95dc ND |
400 | static int mpc52xx_irqx_gettype(int irq) |
401 | { | |
402 | int type; | |
403 | u32 ctrl_reg; | |
404 | ||
405 | ctrl_reg = in_be32(&intr->ctrl); | |
406 | type = (ctrl_reg >> (22 - irq * 2)) & 0x3; | |
407 | ||
408 | return mpc52xx_map_senses[type]; | |
409 | } | |
410 | ||
bcb73f56 GL |
411 | /** |
412 | * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure | |
413 | */ | |
0f6c95dc ND |
414 | static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, |
415 | irq_hw_number_t irq) | |
416 | { | |
417 | int l1irq; | |
418 | int l2irq; | |
419 | struct irq_chip *good_irqchip; | |
420 | void *good_handle; | |
421 | int type; | |
422 | ||
423 | l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET; | |
bcb73f56 | 424 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
0f6c95dc ND |
425 | |
426 | /* | |
427 | * Most of ours IRQs will be level low | |
428 | * Only external IRQs on some platform may be others | |
429 | */ | |
430 | type = IRQ_TYPE_LEVEL_LOW; | |
431 | ||
432 | switch (l1irq) { | |
433 | case MPC52xx_IRQ_L1_CRIT: | |
434 | pr_debug("%s: Critical. l2=%x\n", __func__, l2irq); | |
435 | ||
436 | BUG_ON(l2irq != 0); | |
437 | ||
438 | type = mpc52xx_irqx_gettype(l2irq); | |
439 | good_irqchip = &mpc52xx_extirq_irqchip; | |
440 | break; | |
441 | ||
442 | case MPC52xx_IRQ_L1_MAIN: | |
443 | pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq); | |
444 | ||
445 | if ((l2irq >= 1) && (l2irq <= 3)) { | |
446 | type = mpc52xx_irqx_gettype(l2irq); | |
447 | good_irqchip = &mpc52xx_extirq_irqchip; | |
448 | } else { | |
449 | good_irqchip = &mpc52xx_main_irqchip; | |
450 | } | |
451 | break; | |
452 | ||
453 | case MPC52xx_IRQ_L1_PERP: | |
454 | pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq); | |
455 | good_irqchip = &mpc52xx_periph_irqchip; | |
456 | break; | |
457 | ||
458 | case MPC52xx_IRQ_L1_SDMA: | |
459 | pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq); | |
460 | good_irqchip = &mpc52xx_sdma_irqchip; | |
461 | break; | |
462 | ||
463 | default: | |
bcb73f56 | 464 | pr_err("%s: invalid virq requested (0x%x)\n", __func__, virq); |
0f6c95dc ND |
465 | return -EINVAL; |
466 | } | |
467 | ||
468 | switch (type) { | |
469 | case IRQ_TYPE_EDGE_FALLING: | |
470 | case IRQ_TYPE_EDGE_RISING: | |
471 | good_handle = handle_edge_irq; | |
472 | break; | |
473 | default: | |
474 | good_handle = handle_level_irq; | |
475 | } | |
476 | ||
477 | set_irq_chip_and_handler(virq, good_irqchip, good_handle); | |
478 | ||
479 | pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq, | |
480 | (int)irq, type); | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static struct irq_host_ops mpc52xx_irqhost_ops = { | |
0f6c95dc ND |
486 | .xlate = mpc52xx_irqhost_xlate, |
487 | .map = mpc52xx_irqhost_map, | |
488 | }; | |
489 | ||
bcb73f56 GL |
490 | /** |
491 | * mpc52xx_init_irq - Initialize and register with the virq subsystem | |
492 | * | |
493 | * Hook for setting up IRQs on an mpc5200 system. A pointer to this function | |
494 | * is to be put into the machine definition structure. | |
495 | * | |
496 | * This function searches the device tree for an MPC5200 interrupt controller, | |
497 | * initializes it, and registers it with the virq subsystem. | |
498 | */ | |
0f6c95dc ND |
499 | void __init mpc52xx_init_irq(void) |
500 | { | |
0f6c95dc | 501 | u32 intr_ctrl; |
6065170c | 502 | struct device_node *picnode; |
75ca399e | 503 | struct device_node *np; |
0f6c95dc ND |
504 | |
505 | /* Remap the necessary zones */ | |
66ffbe49 | 506 | picnode = of_find_matching_node(NULL, mpc52xx_pic_ids); |
75ca399e | 507 | intr = of_iomap(picnode, 0); |
6065170c | 508 | if (!intr) |
e3aba81d | 509 | panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. " |
6065170c | 510 | "Check node !"); |
0f6c95dc | 511 | |
66ffbe49 | 512 | np = of_find_matching_node(NULL, mpc52xx_sdma_ids); |
75ca399e GL |
513 | sdma = of_iomap(np, 0); |
514 | of_node_put(np); | |
6065170c | 515 | if (!sdma) |
e3aba81d | 516 | panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. " |
6065170c | 517 | "Check node !"); |
0f6c95dc ND |
518 | |
519 | /* Disable all interrupt sources. */ | |
520 | out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ | |
521 | out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ | |
522 | out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ | |
523 | out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ | |
524 | intr_ctrl = in_be32(&intr->ctrl); | |
525 | intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */ | |
526 | intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */ | |
527 | 0x00001000 | /* MEE master external enable */ | |
528 | 0x00000000 | /* 0 means disable IRQ 0-3 */ | |
529 | 0x00000001; /* CEb route critical normally */ | |
530 | out_be32(&intr->ctrl, intr_ctrl); | |
531 | ||
532 | /* Zero a bunch of the priority settings. */ | |
533 | out_be32(&intr->per_pri1, 0); | |
534 | out_be32(&intr->per_pri2, 0); | |
535 | out_be32(&intr->per_pri3, 0); | |
536 | out_be32(&intr->main_pri1, 0); | |
537 | out_be32(&intr->main_pri2, 0); | |
538 | ||
539 | /* | |
540 | * As last step, add an irq host to translate the real | |
541 | * hw irq information provided by the ofw to linux virq | |
542 | */ | |
52964f87 | 543 | mpc52xx_irqhost = irq_alloc_host(picnode, IRQ_HOST_MAP_LINEAR, |
6065170c GL |
544 | MPC52xx_IRQ_HIGHTESTHWIRQ, |
545 | &mpc52xx_irqhost_ops, -1); | |
0f6c95dc | 546 | |
6065170c GL |
547 | if (!mpc52xx_irqhost) |
548 | panic(__FILE__ ": Cannot allocate the IRQ host\n"); | |
0f6c95dc | 549 | |
bcb73f56 | 550 | pr_info("MPC52xx PIC is up and running!\n"); |
0f6c95dc ND |
551 | } |
552 | ||
bcb73f56 GL |
553 | /** |
554 | * mpc52xx_get_irq - Get pending interrupt number hook function | |
555 | * | |
556 | * Called by the interupt handler to determine what IRQ handler needs to be | |
557 | * executed. | |
558 | * | |
559 | * Status of pending interrupts is determined by reading the encoded status | |
560 | * register. The encoded status register has three fields; one for each of the | |
561 | * types of interrupts defined by the controller - 'critical', 'main' and | |
562 | * 'peripheral'. This function reads the status register and returns the IRQ | |
563 | * number associated with the highest priority pending interrupt. 'Critical' | |
564 | * interrupts have the highest priority, followed by 'main' interrupts, and | |
565 | * then 'peripheral'. | |
566 | * | |
567 | * The mpc5200 interrupt controller can be configured to boost the priority | |
568 | * of individual 'peripheral' interrupts. If this is the case then a special | |
569 | * value will appear in either the crit or main fields indicating a high | |
570 | * or medium priority peripheral irq has occurred. | |
571 | * | |
572 | * This function checks each of the 3 irq request fields and returns the | |
573 | * first pending interrupt that it finds. | |
574 | * | |
575 | * This function also identifies a 4th type of interrupt; 'bestcomm'. Each | |
576 | * bestcomm DMA task can raise the bestcomm peripheral interrupt. When this | |
577 | * occurs at task-specific IRQ# is decoded so that each task can have its | |
578 | * own IRQ handler. | |
579 | */ | |
0f6c95dc ND |
580 | unsigned int mpc52xx_get_irq(void) |
581 | { | |
582 | u32 status; | |
583 | int irq = NO_IRQ_IGNORE; | |
584 | ||
585 | status = in_be32(&intr->enc_status); | |
586 | if (status & 0x00000400) { /* critical */ | |
587 | irq = (status >> 8) & 0x3; | |
588 | if (irq == 2) /* high priority peripheral */ | |
589 | goto peripheral; | |
bcb73f56 | 590 | irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET); |
0f6c95dc ND |
591 | } else if (status & 0x00200000) { /* main */ |
592 | irq = (status >> 16) & 0x1f; | |
593 | if (irq == 4) /* low priority peripheral */ | |
594 | goto peripheral; | |
bcb73f56 | 595 | irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET); |
0f6c95dc ND |
596 | } else if (status & 0x20000000) { /* peripheral */ |
597 | peripheral: | |
598 | irq = (status >> 24) & 0x1f; | |
599 | if (irq == 0) { /* bestcomm */ | |
600 | status = in_be32(&sdma->IntPend); | |
601 | irq = ffs(status) - 1; | |
bcb73f56 | 602 | irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET); |
6065170c | 603 | } else { |
bcb73f56 | 604 | irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET); |
6065170c | 605 | } |
0f6c95dc ND |
606 | } |
607 | ||
608 | pr_debug("%s: irq=%x. virq=%d\n", __func__, irq, | |
609 | irq_linear_revmap(mpc52xx_irqhost, irq)); | |
610 | ||
611 | return irq_linear_revmap(mpc52xx_irqhost, irq); | |
612 | } |