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Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / arch / powerpc / platforms / 512x / clock-commonclk.c
CommitLineData
6d8cdb68
GS		 1/*
2 * Copyright (C) 2013 DENX Software Engineering
3 *
4 * Gerhard Sittig, <gsi@denx.de>
5 *
6 * common clock driver support for the MPC512x platform
7 *
8 * This is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
01f25c37 14#include <linux/bitops.h>
d5fb48a3 15#include <linux/clk.h>
6d8cdb68
GS		 16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/device.h>
19#include <linux/errno.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23
24#include <asm/mpc5121.h>
25#include <dt-bindings/clock/mpc512x-clock.h>
26
27#include "mpc512x.h" /* our public mpc5121_clk_init() API */
28
29/* helpers to keep the MCLK intermediates "somewhere" in our table */
30enum {
31 MCLK_IDX_MUX0,
32 MCLK_IDX_EN0,
33 MCLK_IDX_DIV0,
34 MCLK_MAX_IDX,
35};
36
37#define NR_PSCS 12
38#define NR_MSCANS 4
39#define NR_SPDIFS 1
319bbe0e
GS		 40#define NR_OUTCLK 4
41#define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS + NR_OUTCLK)
6d8cdb68
GS		 42
43/* extend the public set of clocks by adding internal slots for management */
44enum {
45 /* arrange for adjacent numbers after the public set */
46 MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC,
47 /* clocks which aren't announced to the public */
48 MPC512x_CLK_DDR,
49 MPC512x_CLK_MEM,
50 MPC512x_CLK_IIM,
6d8cdb68
GS		 51 /* intermediates in div+gate combos or fractional dividers */
52 MPC512x_CLK_DDR_UG,
53 MPC512x_CLK_SDHC_x4,
54 MPC512x_CLK_SDHC_UG,
319bbe0e 55 MPC512x_CLK_SDHC2_UG,
6d8cdb68
GS		 56 MPC512x_CLK_DIU_x4,
57 MPC512x_CLK_DIU_UG,
58 MPC512x_CLK_MBX_BUS_UG,
59 MPC512x_CLK_MBX_UG,
60 MPC512x_CLK_MBX_3D_UG,
61 MPC512x_CLK_PCI_UG,
62 MPC512x_CLK_NFC_UG,
63 MPC512x_CLK_LPC_UG,
64 MPC512x_CLK_SPDIF_TX_IN,
65 /* intermediates for the mux+gate+div+mux MCLK generation */
66 MPC512x_CLK_MCLKS_FIRST,
67 MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST
68 + NR_MCLKS * MCLK_MAX_IDX,
69 /* internal, symbolic spec for the number of slots */
70 MPC512x_CLK_LAST_PRIVATE,
71};
72
73/* data required for the OF clock provider registration */
74static struct clk *clks[MPC512x_CLK_LAST_PRIVATE];
75static struct clk_onecell_data clk_data;
76
77/* CCM register access */
78static struct mpc512x_ccm __iomem *clkregs;
79static DEFINE_SPINLOCK(clklock);
80
319bbe0e
GS		 81/* SoC variants {{{ */
82
83/*
84 * tell SoC variants apart as they are rather similar yet not identical,
85 * cache the result in an enum to not repeatedly run the expensive OF test
86 *
87 * MPC5123 is an MPC5121 without the MBX graphics accelerator
88 *
89 * MPC5125 has many more differences: no MBX, no AXE, no VIU, no SPDIF,
90 * no PATA, no SATA, no PCI, two FECs (of different compatibility name),
91 * only 10 PSCs (of different compatibility name), two SDHCs, different
92 * NFC IP block, output clocks, system PLL status query, different CPMF
93 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
94 * those differences can get folded into this clock provider support
95 * code and don't warrant a separate highly redundant implementation
96 */
97
98static enum soc_type {
99 MPC512x_SOC_MPC5121,
100 MPC512x_SOC_MPC5123,
101 MPC512x_SOC_MPC5125,
102} soc;
103
104static void mpc512x_clk_determine_soc(void)
105{
106 if (of_machine_is_compatible("fsl,mpc5121")) {
107 soc = MPC512x_SOC_MPC5121;
108 return;
109 }
110 if (of_machine_is_compatible("fsl,mpc5123")) {
111 soc = MPC512x_SOC_MPC5123;
112 return;
113 }
114 if (of_machine_is_compatible("fsl,mpc5125")) {
115 soc = MPC512x_SOC_MPC5125;
116 return;
117 }
118}
119
120static bool soc_has_mbx(void)
121{
122 if (soc == MPC512x_SOC_MPC5121)
123 return true;
124 return false;
125}
126
127static bool soc_has_axe(void)
128{
129 if (soc == MPC512x_SOC_MPC5125)
130 return false;
131 return true;
132}
133
134static bool soc_has_viu(void)
135{
136 if (soc == MPC512x_SOC_MPC5125)
137 return false;
138 return true;
139}
140
141static bool soc_has_spdif(void)
142{
143 if (soc == MPC512x_SOC_MPC5125)
144 return false;
145 return true;
146}
147
148static bool soc_has_pata(void)
149{
150 if (soc == MPC512x_SOC_MPC5125)
151 return false;
152 return true;
153}
154
155static bool soc_has_sata(void)
156{
157 if (soc == MPC512x_SOC_MPC5125)
158 return false;
159 return true;
160}
161
162static bool soc_has_pci(void)
163{
164 if (soc == MPC512x_SOC_MPC5125)
165 return false;
166 return true;
167}
168
169static bool soc_has_fec2(void)
170{
171 if (soc == MPC512x_SOC_MPC5125)
172 return true;
173 return false;
174}
175
176static int soc_max_pscnum(void)
177{
178 if (soc == MPC512x_SOC_MPC5125)
179 return 10;
180 return 12;
181}
182
183static bool soc_has_sdhc2(void)
184{
185 if (soc == MPC512x_SOC_MPC5125)
186 return true;
187 return false;
188}
189
190static bool soc_has_nfc_5125(void)
191{
192 if (soc == MPC512x_SOC_MPC5125)
193 return true;
194 return false;
195}
196
197static bool soc_has_outclk(void)
198{
199 if (soc == MPC512x_SOC_MPC5125)
200 return true;
201 return false;
202}
203
204static bool soc_has_cpmf_0_bypass(void)
205{
206 if (soc == MPC512x_SOC_MPC5125)
207 return true;
208 return false;
209}
210
211static bool soc_has_mclk_mux0_canin(void)
212{
213 if (soc == MPC512x_SOC_MPC5125)
214 return true;
215 return false;
216}
217
218/* }}} SoC variants */
2a2b9ff8
GS		 219/* common clk API wrappers {{{ */
220
6d8cdb68
GS		 221/* convenience wrappers around the common clk API */
222static inline struct clk *mpc512x_clk_fixed(const char *name, int rate)
223{
3fb9c412 224 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
6d8cdb68
GS		 225}
226
227static inline struct clk *mpc512x_clk_factor(
228 const char *name, const char *parent_name,
229 int mul, int div)
230{
231 int clkflags;
232
233 clkflags = CLK_SET_RATE_PARENT;
234 return clk_register_fixed_factor(NULL, name, parent_name, clkflags,
235 mul, div);
236}
237
238static inline struct clk *mpc512x_clk_divider(
239 const char *name, const char *parent_name, u8 clkflags,
240 u32 __iomem *reg, u8 pos, u8 len, int divflags)
241{
242 return clk_register_divider(NULL, name, parent_name, clkflags,
243 reg, pos, len, divflags, &clklock);
244}
245
246static inline struct clk *mpc512x_clk_divtable(
247 const char *name, const char *parent_name,
248 u32 __iomem *reg, u8 pos, u8 len,
249 const struct clk_div_table *divtab)
250{
251 u8 divflags;
252
253 divflags = 0;
254 return clk_register_divider_table(NULL, name, parent_name, 0,
255 reg, pos, len, divflags,
256 divtab, &clklock);
257}
258
259static inline struct clk *mpc512x_clk_gated(
260 const char *name, const char *parent_name,
261 u32 __iomem *reg, u8 pos)
262{
263 int clkflags;
264
265 clkflags = CLK_SET_RATE_PARENT;
266 return clk_register_gate(NULL, name, parent_name, clkflags,
267 reg, pos, 0, &clklock);
268}
269
270static inline struct clk *mpc512x_clk_muxed(const char *name,
271 const char **parent_names, int parent_count,
272 u32 __iomem *reg, u8 pos, u8 len)
273{
274 int clkflags;
275 u8 muxflags;
276
277 clkflags = CLK_SET_RATE_PARENT;
278 muxflags = 0;
279 return clk_register_mux(NULL, name,
280 parent_names, parent_count, clkflags,
281 reg, pos, len, muxflags, &clklock);
282}
283
2a2b9ff8
GS		 284/* }}} common clk API wrappers */
285
6d8cdb68
GS		 286/* helper to isolate a bit field from a register */
287static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len)
288{
289 uint32_t val;
290
291 val = in_be32(reg);
292 val >>= pos;
293 val &= (1 << len) - 1;
294 return val;
295}
296
297/* get the SPMF and translate it into the "sys pll" multiplier */
298static int get_spmf_mult(void)
299{
300 static int spmf_to_mult[] = {
301 68, 1, 12, 16, 20, 24, 28, 32,
302 36, 40, 44, 48, 52, 56, 60, 64,
303 };
304 int spmf;
305
306 spmf = get_bit_field(&clkregs->spmr, 24, 4);
307 return spmf_to_mult[spmf];
308}
309
310/*
311 * get the SYS_DIV value and translate it into a divide factor
312 *
313 * values returned from here are a multiple of the real factor since the
314 * divide ratio is fractional
315 */
316static int get_sys_div_x2(void)
317{
318 static int sysdiv_code_to_x2[] = {
319 4, 5, 6, 7, 8, 9, 10, 14,
320 12, 16, 18, 22, 20, 24, 26, 30,
321 28, 32, 34, 38, 36, 40, 42, 46,
322 44, 48, 50, 54, 52, 56, 58, 62,
323 60, 64, 66,
324 };
325 int divcode;
326
327 divcode = get_bit_field(&clkregs->scfr2, 26, 6);
328 return sysdiv_code_to_x2[divcode];
329}
330
331/*
332 * get the CPMF value and translate it into a multiplier factor
333 *
334 * values returned from here are a multiple of the real factor since the
335 * multiplier ratio is fractional
336 */
337static int get_cpmf_mult_x2(void)
338{
319bbe0e
GS		 339 static int cpmf_to_mult_x36[] = {
340 /* 0b000 is "times 36" */
6d8cdb68
GS		 341 72, 2, 2, 3, 4, 5, 6, 7,
342 };
319bbe0e
GS		 343 static int cpmf_to_mult_0by[] = {
344 /* 0b000 is "bypass" */
345 2, 2, 2, 3, 4, 5, 6, 7,
346 };
347
348 int *cpmf_to_mult;
6d8cdb68
GS		 349 int cpmf;
350
351 cpmf = get_bit_field(&clkregs->spmr, 16, 4);
319bbe0e
GS		 352 if (soc_has_cpmf_0_bypass())
353 cpmf_to_mult = cpmf_to_mult_0by;
354 else
355 cpmf_to_mult = cpmf_to_mult_x36;
6d8cdb68
GS		 356 return cpmf_to_mult[cpmf];
357}
358
359/*
360 * some of the clock dividers do scale in a linear way, yet not all of
361 * their bit combinations are legal; use a divider table to get a
362 * resulting set of applicable divider values
363 */
364
365/* applies to the IPS_DIV, and PCI_DIV values */
366static struct clk_div_table divtab_2346[] = {
367 { .val = 2, .div = 2, },
368 { .val = 3, .div = 3, },
369 { .val = 4, .div = 4, },
370 { .val = 6, .div = 6, },
371 { .div = 0, },
372};
373
374/* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */
375static struct clk_div_table divtab_1234[] = {
376 { .val = 1, .div = 1, },
377 { .val = 2, .div = 2, },
378 { .val = 3, .div = 3, },
379 { .val = 4, .div = 4, },
380 { .div = 0, },
381};
382
383static int get_freq_from_dt(char *propname)
384{
385 struct device_node *np;
386 const unsigned int *prop;
387 int val;
388
389 val = 0;
390 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
391 if (np) {
392 prop = of_get_property(np, propname, NULL);
393 if (prop)
394 val = *prop;
395 of_node_put(np);
396 }
397 return val;
398}
399
400static void mpc512x_clk_preset_data(void)
401{
402 size_t i;
403
404 for (i = 0; i < ARRAY_SIZE(clks); i++)
405 clks[i] = ERR_PTR(-ENODEV);
406}
407
408/*
409 * - receives the "bus frequency" from the caller (that's the IPS clock
410 * rate, the historical source of clock information)
411 * - fetches the system PLL multiplier and divider values as well as the
412 * IPS divider value from hardware
413 * - determines the REF clock rate either from the XTAL/OSC spec (if
414 * there is a device tree node describing the oscillator) or from the
415 * IPS bus clock (supported for backwards compatibility, such that
416 * setups without XTAL/OSC specs keep working)
417 * - creates the "ref" clock item in the clock tree, such that
418 * subsequent code can create the remainder of the hierarchy (REF ->
419 * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
420 * values
421 */
422static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq,
423 int *sys_mul, int *sys_div,
424 int *ips_div)
425{
426 struct clk *osc_clk;
427 int calc_freq;
428
429 /* fetch mul/div factors from the hardware */
430 *sys_mul = get_spmf_mult();
431 *sys_mul *= 2; /* compensate for the fractional divider */
432 *sys_div = get_sys_div_x2();
433 *ips_div = get_bit_field(&clkregs->scfr1, 23, 3);
434
435 /* lookup the oscillator clock for its rate */
436 osc_clk = of_clk_get_by_name(np, "osc");
437
438 /*
439 * either descend from OSC to REF (and in bypassing verify the
440 * IPS rate), or backtrack from IPS and multiplier values that
441 * were fetched from hardware to REF and thus to the OSC value
442 *
443 * in either case the REF clock gets created here and the
444 * remainder of the clock tree can get spanned from there
445 */
446 if (!IS_ERR(osc_clk)) {
447 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
448 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
449 calc_freq *= *sys_mul;
450 calc_freq /= *sys_div;
451 calc_freq /= 2;
452 calc_freq /= *ips_div;
453 if (bus_freq && calc_freq != bus_freq)
454 pr_warn("calc rate %d != OF spec %d\n",
455 calc_freq, bus_freq);
456 } else {
457 calc_freq = bus_freq; /* start with IPS */
458 calc_freq *= *ips_div; /* IPS -> CSB */
459 calc_freq *= 2; /* CSB -> SYS */
460 calc_freq *= *sys_div; /* SYS -> PLL out */
461 calc_freq /= *sys_mul; /* PLL out -> REF == OSC */
462 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
463 }
464}
465
2a2b9ff8
GS		 466/* MCLK helpers {{{ */
467
6d8cdb68
GS		 468/*
469 * helper code for the MCLK subtree setup
470 *
471 * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4
472 * suggests that all instances of the "PSC clock generation" are equal,
473 * and that one might re-use the PSC setup for MSCAN clock generation
474 * (section 5.2.5) as well, at least the logic if not the data for
475 * description
476 *
477 * the details (starting at page 5-20) show differences in the specific
478 * inputs of the first mux stage ("can clk in", "spdif tx"), and the
479 * factual non-availability of the second mux stage (it's present yet
480 * only one input is valid)
481 *
482 * the MSCAN clock related registers (starting at page 5-35) all
483 * reference "spdif clk" at the first mux stage and don't mention any
484 * "can clk" at all, which somehow is unexpected
485 *
486 * TODO re-check the document, and clarify whether the RM is correct in
487 * the overview or in the details, and whether the difference is a
488 * clipboard induced error or results from chip revisions
489 *
490 * it turns out that the RM rev4 as of 2012-06 talks about "can" for the
491 * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that
492 * first a doc update is required which better reflects reality in the
493 * SoC before the implementation should follow while no questions remain
494 */
495
496/*
497 * note that this declaration raises a checkpatch warning, but
2a2b9ff8
GS		 498 * it's the very data type dictated by <linux/clk-provider.h>,
499 * "fixing" this warning will break compilation
6d8cdb68 500 */
319bbe0e 501static const char *parent_names_mux0_spdif[] = {
6d8cdb68
GS		 502 "sys", "ref", "psc-mclk-in", "spdif-tx",
503};
504
319bbe0e
GS		 505static const char *parent_names_mux0_canin[] = {
506 "sys", "ref", "psc-mclk-in", "can-clk-in",
507};
508
6d8cdb68
GS		 509enum mclk_type {
510 MCLK_TYPE_PSC,
511 MCLK_TYPE_MSCAN,
512 MCLK_TYPE_SPDIF,
319bbe0e 513 MCLK_TYPE_OUTCLK,
6d8cdb68
GS		 514};
515
516struct mclk_setup_data {
517 enum mclk_type type;
518 bool has_mclk1;
519 const char *name_mux0;
520 const char *name_en0;
521 const char *name_div0;
522 const char *parent_names_mux1[2];
523 const char *name_mclk;
524};
525
526#define MCLK_SETUP_DATA_PSC(id) { \
527 MCLK_TYPE_PSC, 0, \
528 "psc" #id "-mux0", \
529 "psc" #id "-en0", \
530 "psc" #id "_mclk_div", \
531 { "psc" #id "_mclk_div", "dummy", }, \
532 "psc" #id "_mclk", \
533}
534
535#define MCLK_SETUP_DATA_MSCAN(id) { \
536 MCLK_TYPE_MSCAN, 0, \
537 "mscan" #id "-mux0", \
538 "mscan" #id "-en0", \
539 "mscan" #id "_mclk_div", \
540 { "mscan" #id "_mclk_div", "dummy", }, \
541 "mscan" #id "_mclk", \
542}
543
544#define MCLK_SETUP_DATA_SPDIF { \
545 MCLK_TYPE_SPDIF, 1, \
546 "spdif-mux0", \
547 "spdif-en0", \
548 "spdif_mclk_div", \
549 { "spdif_mclk_div", "spdif-rx", }, \
550 "spdif_mclk", \
551}
552
319bbe0e
GS		 553#define MCLK_SETUP_DATA_OUTCLK(id) { \
554 MCLK_TYPE_OUTCLK, 0, \
555 "out" #id "-mux0", \
556 "out" #id "-en0", \
557 "out" #id "_mclk_div", \
558 { "out" #id "_mclk_div", "dummy", }, \
559 "out" #id "_clk", \
560}
561
6d8cdb68
GS		 562static struct mclk_setup_data mclk_psc_data[] = {
563 MCLK_SETUP_DATA_PSC(0),
564 MCLK_SETUP_DATA_PSC(1),
565 MCLK_SETUP_DATA_PSC(2),
566 MCLK_SETUP_DATA_PSC(3),
567 MCLK_SETUP_DATA_PSC(4),
568 MCLK_SETUP_DATA_PSC(5),
569 MCLK_SETUP_DATA_PSC(6),
570 MCLK_SETUP_DATA_PSC(7),
571 MCLK_SETUP_DATA_PSC(8),
572 MCLK_SETUP_DATA_PSC(9),
573 MCLK_SETUP_DATA_PSC(10),
574 MCLK_SETUP_DATA_PSC(11),
575};
576
577static struct mclk_setup_data mclk_mscan_data[] = {
578 MCLK_SETUP_DATA_MSCAN(0),
579 MCLK_SETUP_DATA_MSCAN(1),
580 MCLK_SETUP_DATA_MSCAN(2),
581 MCLK_SETUP_DATA_MSCAN(3),
582};
583
584static struct mclk_setup_data mclk_spdif_data[] = {
585 MCLK_SETUP_DATA_SPDIF,
586};
587
319bbe0e
GS		 588static struct mclk_setup_data mclk_outclk_data[] = {
589 MCLK_SETUP_DATA_OUTCLK(0),
590 MCLK_SETUP_DATA_OUTCLK(1),
591 MCLK_SETUP_DATA_OUTCLK(2),
592 MCLK_SETUP_DATA_OUTCLK(3),
593};
594
6d8cdb68
GS		 595/* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
596static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx)
597{
598 size_t clks_idx_pub, clks_idx_int;
599 u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */
600 int div;
601
602 /* derive a few parameters from the component type and index */
603 switch (entry->type) {
604 case MCLK_TYPE_PSC:
605 clks_idx_pub = MPC512x_CLK_PSC0_MCLK + idx;
606 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
607 + (idx) * MCLK_MAX_IDX;
608 mccr_reg = &clkregs->psc_ccr[idx];
609 break;
610 case MCLK_TYPE_MSCAN:
611 clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + idx;
612 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
613 + (NR_PSCS + idx) * MCLK_MAX_IDX;
614 mccr_reg = &clkregs->mscan_ccr[idx];
615 break;
616 case MCLK_TYPE_SPDIF:
617 clks_idx_pub = MPC512x_CLK_SPDIF_MCLK;
618 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
619 + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX;
620 mccr_reg = &clkregs->spccr;
621 break;
319bbe0e
GS		 622 case MCLK_TYPE_OUTCLK:
623 clks_idx_pub = MPC512x_CLK_OUT0_CLK + idx;
624 clks_idx_int = MPC512x_CLK_MCLKS_FIRST
625 + (NR_PSCS + NR_MSCANS + NR_SPDIFS + idx)
626 * MCLK_MAX_IDX;
627 mccr_reg = &clkregs->out_ccr[idx];
628 break;
6d8cdb68
GS		 629 default:
630 return;
631 }
632
633 /*
634 * this was grabbed from the PPC_CLOCK implementation, which
635 * enforced a specific MCLK divider while the clock was gated
636 * during setup (that's a documented hardware requirement)
637 *
638 * the PPC_CLOCK implementation might even have violated the
639 * "MCLK <= IPS" constraint, the fixed divider value of 1
640 * results in a divider of 2 and thus MCLK = SYS/2 which equals
641 * CSB which is greater than IPS; the serial port setup may have
642 * adjusted the divider which the clock setup might have left in
643 * an undesirable state
644 *
645 * initial setup is:
646 * - MCLK 0 from SYS
647 * - MCLK DIV such to not exceed the IPS clock
648 * - MCLK 0 enabled
649 * - MCLK 1 from MCLK DIV
650 */
651 div = clk_get_rate(clks[MPC512x_CLK_SYS]);
652 div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
653 out_be32(mccr_reg, (0 << 16));
654 out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17));
655 out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17));
656
657 /*
658 * create the 'struct clk' items of the MCLK's clock subtree
659 *
660 * note that by design we always create all nodes and won't take
661 * shortcuts here, because
662 * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are
663 * selectable inputs to the CFM while those who "actually use"
664 * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
665 * for their bitrate
666 * - in the absence of "aliases" for clocks we need to create
667 * individial 'struct clk' items for whatever might get
668 * referenced or looked up, even if several of those items are
669 * identical from the logical POV (their rate value)
670 * - for easier future maintenance and for better reflection of
671 * the SoC's documentation, it appears appropriate to generate
672 * clock items even for those muxers which actually are NOPs
673 * (those with two inputs of which one is reserved)
674 */
675 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
676 entry->name_mux0,
319bbe0e
GS		 677 soc_has_mclk_mux0_canin()
678 ? &parent_names_mux0_canin[0]
679 : &parent_names_mux0_spdif[0],
680 ARRAY_SIZE(parent_names_mux0_spdif),
6d8cdb68
GS		 681 mccr_reg, 14, 2);
682 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated(
683 entry->name_en0, entry->name_mux0,
684 mccr_reg, 16);
685 clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider(
686 entry->name_div0,
687 entry->name_en0, CLK_SET_RATE_GATE,
688 mccr_reg, 17, 15, 0);
689 if (entry->has_mclk1) {
690 clks[clks_idx_pub] = mpc512x_clk_muxed(
691 entry->name_mclk,
692 &entry->parent_names_mux1[0],
693 ARRAY_SIZE(entry->parent_names_mux1),
694 mccr_reg, 7, 1);
695 } else {
696 clks[clks_idx_pub] = mpc512x_clk_factor(
697 entry->name_mclk,
698 entry->parent_names_mux1[0],
699 1, 1);
700 }
701}
702
2a2b9ff8
GS		 703/* }}} MCLK helpers */
704
6d8cdb68
GS		 705static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq)
706{
707 int sys_mul, sys_div, ips_div;
708 int mul, div;
709 size_t mclk_idx;
710 int freq;
711
712 /*
713 * developer's notes:
714 * - consider whether to handle clocks which have both gates and
715 * dividers via intermediates or by means of composites
716 * - fractional dividers appear to not map well to composites
717 * since they can be seen as a fixed multiplier and an
718 * adjustable divider, while composites can only combine at
719 * most one of a mux, div, and gate each into one 'struct clk'
720 * item
721 * - PSC/MSCAN/SPDIF clock generation OTOH already is very
722 * specific and cannot get mapped to componsites (at least not
723 * a single one, maybe two of them, but then some of these
724 * intermediate clock signals get referenced elsewhere (e.g.
725 * in the clock frequency measurement, CFM) and thus need
726 * publicly available names
727 * - the current source layout appropriately reflects the
728 * hardware setup, and it works, so it's questionable whether
729 * further changes will result in big enough a benefit
730 */
731
732 /* regardless of whether XTAL/OSC exists, have REF created */
733 mpc512x_clk_setup_ref_clock(np, busfreq, &sys_mul, &sys_div, &ips_div);
734
735 /* now setup the REF -> SYS -> CSB -> IPS hierarchy */
736 clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref",
737 sys_mul, sys_div);
738 clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2);
739 clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",
740 &clkregs->scfr1, 23, 3,
741 divtab_2346);
6d8cdb68 742 /* now setup anything below SYS and CSB and IPS */
2a2b9ff8 743
6d8cdb68 744 clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2);
76922ebb
GS		 745
746 /*
747 * the Reference Manual discusses that for SDHC only even divide
748 * ratios are supported because clock domain synchronization
749 * between 'per' and 'ipg' is broken;
750 * keep the divider's bit 0 cleared (per reset value), and only
751 * allow to setup the divider's bits 7:1, which results in that
752 * only even divide ratios can get configured upon rate changes;
753 * keep the "x4" name because this bit shift hack is an internal
754 * implementation detail, the "fractional divider with quarters"
755 * semantics remains
756 */
757 clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 2, 1);
6d8cdb68 758 clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0,
76922ebb 759 &clkregs->scfr2, 1, 7,
6d8cdb68 760 CLK_DIVIDER_ONE_BASED);
319bbe0e
GS		 761 if (soc_has_sdhc2()) {
762 clks[MPC512x_CLK_SDHC2_UG] = mpc512x_clk_divider(
763 "sdhc2-ug", "sdhc-x4", 0, &clkregs->scfr2,
764 9, 7, CLK_DIVIDER_ONE_BASED);
765 }
766
6d8cdb68
GS		 767 clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1);
768 clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0,
769 &clkregs->scfr1, 0, 8,
770 CLK_DIVIDER_ONE_BASED);
771
772 /*
773 * the "power architecture PLL" was setup from data which was
774 * sampled from the reset config word, at this point in time the
775 * configuration can be considered fixed and read only (i.e. no
776 * longer adjustable, or no longer in need of adjustment), which
777 * is why we don't register a PLL here but assume fixed factors
778 */
779 mul = get_cpmf_mult_x2();
780 div = 2; /* compensate for the fractional factor */
781 clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div);
782
319bbe0e
GS		 783 if (soc_has_mbx()) {
784 clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor(
785 "mbx-bus-ug", "csb", 1, 2);
786 clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable(
787 "mbx-ug", "mbx-bus-ug", &clkregs->scfr1,
788 14, 3, divtab_1234);
789 clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor(
790 "mbx-3d-ug", "mbx-ug", 1, 1);
791 }
792 if (soc_has_pci()) {
793 clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable(
794 "pci-ug", "csb", &clkregs->scfr1,
795 20, 3, divtab_2346);
796 }
797 if (soc_has_nfc_5125()) {
798 /*
799 * XXX TODO implement 5125 NFC clock setup logic,
800 * with high/low period counters in clkregs->scfr3,
801 * currently there are no users so it's ENOIMPL
802 */
803 clks[MPC512x_CLK_NFC_UG] = ERR_PTR(-ENOTSUPP);
804 } else {
805 clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable(
806 "nfc-ug", "ips", &clkregs->scfr1,
807 8, 3, divtab_1234);
808 }
6d8cdb68
GS		 809 clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",
810 &clkregs->scfr1, 11, 3,
811 divtab_1234);
812
813 clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug",
814 &clkregs->sccr1, 30);
815 clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug",
816 &clkregs->sccr1, 29);
319bbe0e
GS		 817 if (soc_has_pata()) {
818 clks[MPC512x_CLK_PATA] = mpc512x_clk_gated(
819 "pata", "ips", &clkregs->sccr1, 28);
820 }
6d8cdb68 821 /* for PSCs there is a "registers" gate and a bitrate MCLK subtree */
319bbe0e 822 for (mclk_idx = 0; mclk_idx < soc_max_pscnum(); mclk_idx++) {
6d8cdb68
GS		 823 char name[12];
824 snprintf(name, sizeof(name), "psc%d", mclk_idx);
825 clks[MPC512x_CLK_PSC0 + mclk_idx] = mpc512x_clk_gated(
826 name, "ips", &clkregs->sccr1, 27 - mclk_idx);
827 mpc512x_clk_setup_mclk(&mclk_psc_data[mclk_idx], mclk_idx);
828 }
829 clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",
830 &clkregs->sccr1, 15);
319bbe0e
GS		 831 if (soc_has_sata()) {
832 clks[MPC512x_CLK_SATA] = mpc512x_clk_gated(
833 "sata", "ips", &clkregs->sccr1, 14);
834 }
6d8cdb68
GS		 835 clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",
836 &clkregs->sccr1, 13);
319bbe0e
GS		 837 if (soc_has_pci()) {
838 clks[MPC512x_CLK_PCI] = mpc512x_clk_gated(
839 "pci", "pci-ug", &clkregs->sccr1, 11);
840 }
6d8cdb68
GS		 841 clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug",
842 &clkregs->sccr1, 10);
319bbe0e
GS		 843 if (soc_has_fec2()) {
844 clks[MPC512x_CLK_FEC2] = mpc512x_clk_gated(
845 "fec2", "ips", &clkregs->sccr1, 9);
846 }
6d8cdb68
GS		 847
848 clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug",
849 &clkregs->sccr2, 31);
319bbe0e
GS		 850 if (soc_has_axe()) {
851 clks[MPC512x_CLK_AXE] = mpc512x_clk_gated(
852 "axe", "csb", &clkregs->sccr2, 30);
853 }
6d8cdb68
GS		 854 clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",
855 &clkregs->sccr2, 29);
856 clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb",
857 &clkregs->sccr2, 28);
858 clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb",
859 &clkregs->sccr2, 27);
860 clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",
861 &clkregs->sccr2, 26);
862 /* MSCAN differs from PSC with just one gate for multiple components */
863 clks[MPC512x_CLK_BDLC] = mpc512x_clk_gated("bdlc", "ips",
864 &clkregs->sccr2, 25);
865 for (mclk_idx = 0; mclk_idx < ARRAY_SIZE(mclk_mscan_data); mclk_idx++)
866 mpc512x_clk_setup_mclk(&mclk_mscan_data[mclk_idx], mclk_idx);
867 clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug",
868 &clkregs->sccr2, 24);
869 /* there is only one SPDIF component, which shares MCLK support code */
319bbe0e
GS		 870 if (soc_has_spdif()) {
871 clks[MPC512x_CLK_SPDIF] = mpc512x_clk_gated(
872 "spdif", "ips", &clkregs->sccr2, 23);
873 mpc512x_clk_setup_mclk(&mclk_spdif_data[0], 0);
874 }
875 if (soc_has_mbx()) {
876 clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated(
877 "mbx-bus", "mbx-bus-ug", &clkregs->sccr2, 22);
878 clks[MPC512x_CLK_MBX] = mpc512x_clk_gated(
879 "mbx", "mbx-ug", &clkregs->sccr2, 21);
880 clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated(
881 "mbx-3d", "mbx-3d-ug", &clkregs->sccr2, 20);
882 }
6d8cdb68
GS		 883 clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb",
884 &clkregs->sccr2, 19);
319bbe0e
GS		 885 if (soc_has_viu()) {
886 clks[MPC512x_CLK_VIU] = mpc512x_clk_gated(
887 "viu", "csb", &clkregs->sccr2, 18);
888 }
889 if (soc_has_sdhc2()) {
890 clks[MPC512x_CLK_SDHC2] = mpc512x_clk_gated(
891 "sdhc-2", "sdhc2-ug", &clkregs->sccr2, 17);
892 }
893
894 if (soc_has_outclk()) {
895 size_t idx; /* used as mclk_idx, just to trim line length */
896 for (idx = 0; idx < ARRAY_SIZE(mclk_outclk_data); idx++)
897 mpc512x_clk_setup_mclk(&mclk_outclk_data[idx], idx);
898 }
6d8cdb68
GS		 899
900 /*
901 * externally provided clocks (when implemented in hardware,
902 * device tree may specify values which otherwise were unknown)
903 */
904 freq = get_freq_from_dt("psc_mclk_in");
905 if (!freq)
906 freq = 25000000;
907 clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq);
319bbe0e
GS		 908 if (soc_has_mclk_mux0_canin()) {
909 freq = get_freq_from_dt("can_clk_in");
910 clks[MPC512x_CLK_CAN_CLK_IN] = mpc512x_clk_fixed(
911 "can_clk_in", freq);
912 } else {
913 freq = get_freq_from_dt("spdif_tx_in");
914 clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed(
915 "spdif_tx_in", freq);
916 freq = get_freq_from_dt("spdif_rx_in");
917 clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed(
918 "spdif_rx_in", freq);
919 }
6d8cdb68
GS		 920
921 /* fixed frequency for AC97, always 24.567MHz */
922 clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000);
923
924 /*
925 * pre-enable those "internal" clock items which never get
926 * claimed by any peripheral driver, to not have the clock
927 * subsystem disable them late at startup
928 */
929 clk_prepare_enable(clks[MPC512x_CLK_DUMMY]);
930 clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */
931 clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */
932 clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */
933 clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */
934 clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */
935}
936
937/*
938 * registers the set of public clocks (those listed in the dt-bindings/
939 * header file) for OF lookups, keeps the intermediates private to us
940 */
941static void mpc5121_clk_register_of_provider(struct device_node *np)
942{
943 clk_data.clks = clks;
944 clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */
945 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
946}
947
948/*
949 * temporary support for the period of time between introduction of CCF
950 * support and the adjustment of peripheral drivers to OF based lookups
951 */
952static void mpc5121_clk_provide_migration_support(void)
953{
6d8cdb68
GS		 954
955 /*
956 * pre-enable those clock items which are not yet appropriately
957 * acquired by their peripheral driver
20755f85
GS		 958 *
959 * the PCI clock cannot get acquired by its peripheral driver,
960 * because for this platform the driver won't probe(), instead
961 * initialization is done from within the .setup_arch() routine
962 * at a point in time where the clock provider has not been
963 * setup yet and thus isn't available yet
964 *
965 * so we "pre-enable" the clock here, to not have the clock
966 * subsystem automatically disable this item in a late init call
967 *
968 * this PCI clock pre-enable workaround only applies when there
969 * are device tree nodes for PCI and thus the peripheral driver
970 * has attached to bridges, otherwise the PCI clock remains
971 * unused and so it gets disabled
6d8cdb68 972 */
6d8cdb68 973 clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */
20755f85
GS		 974 if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci"))
975 clk_prepare_enable(clks[MPC512x_CLK_PCI]);
6d8cdb68
GS		 976}
977
01f25c37
GS		 978/*
979 * those macros are not exactly pretty, but they encapsulate a lot
980 * of copy'n'paste heavy code which is even more ugly, and reduce
981 * the potential for inconsistencies in those many code copies
982 */
983#define FOR_NODES(compatname) \
984 for_each_compatible_node(np, NULL, compatname)
985
986#define NODE_PREP do { \
987 of_address_to_resource(np, 0, &res); \
988 snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \
989} while (0)
990
991#define NODE_CHK(clkname, clkitem, regnode, regflag) do { \
992 struct clk *clk; \
993 clk = of_clk_get_by_name(np, clkname); \
994 if (IS_ERR(clk)) { \
995 clk = clkitem; \
996 clk_register_clkdev(clk, clkname, devname); \
997 if (regnode) \
998 clk_register_clkdev(clk, clkname, np->name); \
999 did_register |= DID_REG_ ## regflag; \
1000 pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \
1001 clkname, devname, clk); \
1002 } else { \
1003 clk_put(clk); \
1004 } \
1005} while (0)
1006
6d8cdb68
GS		 1007/*
1008 * register source code provided fallback results for clock lookups,
1009 * these get consulted when OF based clock lookup fails (that is in the
1010 * case of not yet adjusted device tree data, where clock related specs
1011 * are missing)
1012 */
1013static void mpc5121_clk_provide_backwards_compat(void)
1014{
01f25c37
GS		 1015 enum did_reg_flags {
1016 DID_REG_PSC = BIT(0),
1017 DID_REG_PSCFIFO = BIT(1),
1018 DID_REG_NFC = BIT(2),
1019 DID_REG_CAN = BIT(3),
1020 DID_REG_I2C = BIT(4),
1021 DID_REG_DIU = BIT(5),
1022 DID_REG_VIU = BIT(6),
1023 DID_REG_FEC = BIT(7),
1024 DID_REG_USB = BIT(8),
1025 DID_REG_PATA = BIT(9),
1026 };
1027
1028 int did_register;
1029 struct device_node *np;
1030 struct resource res;
1031 int idx;
1032 char devname[32];
1033
1034 did_register = 0;
1035
1036 FOR_NODES(mpc512x_select_psc_compat()) {
1037 NODE_PREP;
1038 idx = (res.start >> 8) & 0xf;
1039 NODE_CHK("ipg", clks[MPC512x_CLK_PSC0 + idx], 0, PSC);
1040 NODE_CHK("mclk", clks[MPC512x_CLK_PSC0_MCLK + idx], 0, PSC);
1041 }
1042
1043 FOR_NODES("fsl,mpc5121-psc-fifo") {
1044 NODE_PREP;
1045 NODE_CHK("ipg", clks[MPC512x_CLK_PSC_FIFO], 1, PSCFIFO);
1046 }
1047
1048 FOR_NODES("fsl,mpc5121-nfc") {
1049 NODE_PREP;
1050 NODE_CHK("ipg", clks[MPC512x_CLK_NFC], 0, NFC);
1051 }
1052
1053 FOR_NODES("fsl,mpc5121-mscan") {
1054 NODE_PREP;
1055 idx = 0;
1056 idx += (res.start & 0x2000) ? 2 : 0;
1057 idx += (res.start & 0x0080) ? 1 : 0;
1058 NODE_CHK("ipg", clks[MPC512x_CLK_BDLC], 0, CAN);
1059 NODE_CHK("mclk", clks[MPC512x_CLK_MSCAN0_MCLK + idx], 0, CAN);
1060 }
1061
1062 /*
1063 * do register the 'ips', 'sys', and 'ref' names globally
1064 * instead of inside each individual CAN node, as there is no
1065 * potential for a name conflict (in contrast to 'ipg' and 'mclk')
1066 */
1067 if (did_register & DID_REG_CAN) {
1068 clk_register_clkdev(clks[MPC512x_CLK_IPS], "ips", NULL);
1069 clk_register_clkdev(clks[MPC512x_CLK_SYS], "sys", NULL);
1070 clk_register_clkdev(clks[MPC512x_CLK_REF], "ref", NULL);
1071 }
1072
1073 FOR_NODES("fsl,mpc5121-i2c") {
1074 NODE_PREP;
1075 NODE_CHK("ipg", clks[MPC512x_CLK_I2C], 0, I2C);
1076 }
1077
1078 /*
1079 * workaround for the fact that the I2C driver does an "anonymous"
1080 * lookup (NULL name spec, which yields the first clock spec) for
1081 * which we cannot register an alias -- a _global_ 'ipg' alias that
1082 * is not bound to any device name and returns the I2C clock item
1083 * is not a good idea
1084 *
1085 * so we have the lookup in the peripheral driver fail, which is
1086 * silent and non-fatal, and pre-enable the clock item here such
1087 * that register access is possible
1088 *
1089 * see commit b3bfce2b "i2c: mpc: cleanup clock API use" for
1090 * details, adjusting s/NULL/"ipg"/ in i2c-mpc.c would make this
1091 * workaround obsolete
1092 */
1093 if (did_register & DID_REG_I2C)
1094 clk_prepare_enable(clks[MPC512x_CLK_I2C]);
1095
1096 FOR_NODES("fsl,mpc5121-diu") {
1097 NODE_PREP;
1098 NODE_CHK("ipg", clks[MPC512x_CLK_DIU], 1, DIU);
1099 }
1100
1101 FOR_NODES("fsl,mpc5121-viu") {
1102 NODE_PREP;
1103 NODE_CHK("ipg", clks[MPC512x_CLK_VIU], 0, VIU);
1104 }
1105
1106 /*
1107 * note that 2771399a "fs_enet: cleanup clock API use" did use the
1108 * "per" string for the clock lookup in contrast to the "ipg" name
1109 * which most other nodes are using -- this is not a fatal thing
1110 * but just something to keep in mind when doing compatibility
1111 * registration, it's a non-issue with up-to-date device tree data
1112 */
1113 FOR_NODES("fsl,mpc5121-fec") {
1114 NODE_PREP;
1115 NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC);
1116 }
1117 FOR_NODES("fsl,mpc5121-fec-mdio") {
1118 NODE_PREP;
1119 NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC);
1120 }
319bbe0e
GS		 1121 /*
1122 * MPC5125 has two FECs: FEC1 at 0x2800, FEC2 at 0x4800;
1123 * the clock items don't "form an array" since FEC2 was
1124 * added only later and was not allowed to shift all other
1125 * clock item indices, so the numbers aren't adjacent
1126 */
1127 FOR_NODES("fsl,mpc5125-fec") {
1128 NODE_PREP;
1129 if (res.start & 0x4000)
1130 idx = MPC512x_CLK_FEC2;
1131 else
1132 idx = MPC512x_CLK_FEC;
1133 NODE_CHK("per", clks[idx], 0, FEC);
1134 }
01f25c37
GS		 1135
1136 FOR_NODES("fsl,mpc5121-usb2-dr") {
1137 NODE_PREP;
1138 idx = (res.start & 0x4000) ? 1 : 0;
1139 NODE_CHK("ipg", clks[MPC512x_CLK_USB1 + idx], 0, USB);
1140 }
1141
1142 FOR_NODES("fsl,mpc5121-pata") {
1143 NODE_PREP;
1144 NODE_CHK("ipg", clks[MPC512x_CLK_PATA], 0, PATA);
1145 }
1146
1147 /*
1148 * try to collapse diagnostics into a single line of output yet
1149 * provide a full list of what is missing, to avoid noise in the
1150 * absence of up-to-date device tree data -- backwards
1151 * compatibility to old DTBs is a requirement, updates may be
1152 * desirable or preferrable but are not at all mandatory
1153 */
1154 if (did_register) {
1155 pr_notice("device tree lacks clock specs, adding fallbacks (0x%x,%s%s%s%s%s%s%s%s%s%s)\n",
1156 did_register,
1157 (did_register & DID_REG_PSC) ? " PSC" : "",
1158 (did_register & DID_REG_PSCFIFO) ? " PSCFIFO" : "",
1159 (did_register & DID_REG_NFC) ? " NFC" : "",
1160 (did_register & DID_REG_CAN) ? " CAN" : "",
1161 (did_register & DID_REG_I2C) ? " I2C" : "",
1162 (did_register & DID_REG_DIU) ? " DIU" : "",
1163 (did_register & DID_REG_VIU) ? " VIU" : "",
1164 (did_register & DID_REG_FEC) ? " FEC" : "",
1165 (did_register & DID_REG_USB) ? " USB" : "",
1166 (did_register & DID_REG_PATA) ? " PATA" : "");
1167 } else {
1168 pr_debug("device tree has clock specs, no fallbacks added\n");
1169 }
6d8cdb68
GS		 1170}
1171
f0d37300
KH		 1172/*
1173 * The "fixed-clock" nodes (which includes the oscillator node if the board's
1174 * DT provides one) has already been scanned by the of_clk_init() in
1175 * time_init().
1176 */
6d8cdb68
GS		 1177int __init mpc5121_clk_init(void)
1178{
1179 struct device_node *clk_np;
1180 int busfreq;
1181
1182 /* map the clock control registers */
1183 clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
1184 if (!clk_np)
1185 return -ENODEV;
1186 clkregs = of_iomap(clk_np, 0);
1187 WARN_ON(!clkregs);
1188
319bbe0e
GS		 1189 /* determine the SoC variant we run on */
1190 mpc512x_clk_determine_soc();
1191
6d8cdb68
GS		 1192 /* invalidate all not yet registered clock slots */
1193 mpc512x_clk_preset_data();
1194
6d8cdb68
GS		 1195 /*
1196 * add a dummy clock for those situations where a clock spec is
1197 * required yet no real clock is involved
1198 */
1199 clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0);
1200
1201 /*
1202 * have all the real nodes in the clock tree populated from REF
1203 * down to all leaves, either starting from the OSC node or from
1204 * a REF root that was created from the IPS bus clock input
1205 */
1206 busfreq = get_freq_from_dt("bus-frequency");
1207 mpc512x_clk_setup_clock_tree(clk_np, busfreq);
1208
1209 /* register as an OF clock provider */
1210 mpc5121_clk_register_of_provider(clk_np);
1211
1212 /*
1213 * unbreak not yet adjusted peripheral drivers during migration
1214 * towards fully operational common clock support, and allow
1215 * operation in the absence of clock related device tree specs
1216 */
1217 mpc5121_clk_provide_migration_support();
1218 mpc5121_clk_provide_backwards_compat();
1219
1220 return 0;
1221}
Linux 6.x block layer and io_uring tree(s)