[linux-2.6-block.git] / arch / powerpc / perf / power6-pmu.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Performance counter support for POWER6 processors.
 *
 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
 */
#include <linux/kernel.h>
#include <linux/perf_event.h>
#include <linux/string.h>
#include <asm/reg.h>
#include <asm/cputable.h>

/*
 * Bits in event code for POWER6
 */
#define PM_PMC_SH	20	/* PMC number (1-based) for direct events */
#define PM_PMC_MSK	0x7
#define PM_PMC_MSKS	(PM_PMC_MSK << PM_PMC_SH)
#define PM_UNIT_SH	16	/* Unit event comes (TTMxSEL encoding) */
#define PM_UNIT_MSK	0xf
#define PM_UNIT_MSKS	(PM_UNIT_MSK << PM_UNIT_SH)
#define PM_LLAV		0x8000	/* Load lookahead match value */
#define PM_LLA		0x4000	/* Load lookahead match enable */
#define PM_BYTE_SH	12	/* Byte of event bus to use */
#define PM_BYTE_MSK	3
#define PM_SUBUNIT_SH	8	/* Subunit event comes from (NEST_SEL enc.) */
#define PM_SUBUNIT_MSK	7
#define PM_SUBUNIT_MSKS	(PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
#define PM_PMCSEL_MSK	0xff	/* PMCxSEL value */
#define PM_BUSEVENT_MSK	0xf3700

/*
 * Bits in MMCR1 for POWER6
 */
#define MMCR1_TTM0SEL_SH	60
#define MMCR1_TTMSEL_SH(n)	(MMCR1_TTM0SEL_SH - (n) * 4)
#define MMCR1_TTMSEL_MSK	0xf
#define MMCR1_TTMSEL(m, n)	(((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
#define MMCR1_NESTSEL_SH	45
#define MMCR1_NESTSEL_MSK	0x7
#define MMCR1_NESTSEL(m)	(((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
#define MMCR1_PMC1_LLA		(1ul << 44)
#define MMCR1_PMC1_LLA_VALUE	(1ul << 39)
#define MMCR1_PMC1_ADDR_SEL	(1ul << 35)
#define MMCR1_PMC1SEL_SH	24
#define MMCR1_PMCSEL_SH(n)	(MMCR1_PMC1SEL_SH - (n) * 8)
#define MMCR1_PMCSEL_MSK	0xff

/*
 * Map of which direct events on which PMCs are marked instruction events.
 * Indexed by PMCSEL value >> 1.
 * Bottom 4 bits are a map of which PMCs are interesting,
 * top 4 bits say what sort of event:
 *   0 = direct marked event,
 *   1 = byte decode event,
 *   4 = add/and event (PMC1 -> bits 0 & 4),
 *   5 = add/and event (PMC1 -> bits 1 & 5),
 *   6 = add/and event (PMC1 -> bits 2 & 6),
 *   7 = add/and event (PMC1 -> bits 3 & 7).
 */
static unsigned char direct_event_is_marked[0x60 >> 1] = {
	0,	/* 00 */
	0,	/* 02 */
	0,	/* 04 */
	0x07,	/* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
	0x04,	/* 08 PM_MRK_DFU_FIN */
	0x06,	/* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
	0,	/* 0c */
	0,	/* 0e */
	0x02,	/* 10 PM_MRK_INST_DISP */
	0x08,	/* 12 PM_MRK_LSU_DERAT_MISS */
	0,	/* 14 */
	0,	/* 16 */
	0x0c,	/* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
	0x0f,	/* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
	0x01,	/* 1c PM_MRK_INST_ISSUED */
	0,	/* 1e */
	0,	/* 20 */
	0,	/* 22 */
	0,	/* 24 */
	0,	/* 26 */
	0x15,	/* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
	0,	/* 2a */
	0,	/* 2c */
	0,	/* 2e */
	0x4f,	/* 30 */
	0x7f,	/* 32 */
	0x4f,	/* 34 */
	0x5f,	/* 36 */
	0x6f,	/* 38 */
	0x4f,	/* 3a */
	0,	/* 3c */
	0x08,	/* 3e PM_MRK_INST_TIMEO */
	0x1f,	/* 40 */
	0x1f,	/* 42 */
	0x1f,	/* 44 */
	0x1f,	/* 46 */
	0x1f,	/* 48 */
	0x1f,	/* 4a */
	0x1f,	/* 4c */
	0x1f,	/* 4e */
	0,	/* 50 */
	0x05,	/* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
	0x1c,	/* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
	0x02,	/* 56 PM_MRK_LD_MISS_L1 */
	0,	/* 58 */
	0,	/* 5a */
	0,	/* 5c */
	0,	/* 5e */
};

/*
 * Masks showing for each unit which bits are marked events.
 * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
 */
static u32 marked_bus_events[16] = {
	0x01000000,	/* direct events set 1: byte 3 bit 0 */
	0x00010000,	/* direct events set 2: byte 2 bit 0 */
	0, 0, 0, 0,	/* IDU, IFU, nest: nothing */
	0x00000088,	/* VMX set 1: byte 0 bits 3, 7 */
	0x000000c0,	/* VMX set 2: byte 0 bits 4-7 */
	0x04010000,	/* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
	0xff010000u,	/* LSU set 2: byte 2 bit 0, all of byte 3 */
	0,		/* LSU set 3 */
	0x00000010,	/* VMX set 3: byte 0 bit 4 */
	0,		/* BFP set 1 */
	0x00000022,	/* BFP set 2: byte 0 bits 1, 5 */
	0, 0
};

/*
 * Returns 1 if event counts things relating to marked instructions
 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 */
static int power6_marked_instr_event(u64 event)
{
	int pmc, psel, ptype;
	int bit, byte, unit;
	u32 mask;

	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	psel = (event & PM_PMCSEL_MSK) >> 1;	/* drop edge/level bit */
	if (pmc >= 5)
		return 0;

	bit = -1;
	if (psel < sizeof(direct_event_is_marked)) {
		ptype = direct_event_is_marked[psel];
		if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
			return 0;
		ptype >>= 4;
		if (ptype == 0)
			return 1;
		if (ptype == 1)
			bit = 0;
		else
			bit = ptype ^ (pmc - 1);
	} else if ((psel & 0x48) == 0x40)
		bit = psel & 7;

	if (!(event & PM_BUSEVENT_MSK) || bit == -1)
		return 0;

	byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
	unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
	mask = marked_bus_events[unit];
	return (mask >> (byte * 8 + bit)) & 1;
}

/*
 * Assign PMC numbers and compute MMCR1 value for a set of events
 */
static int p6_compute_mmcr(u64 event[], int n_ev,
			   unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
{
	unsigned long mmcr1 = 0;
	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
	int i;
	unsigned int pmc, ev, b, u, s, psel;
	unsigned int ttmset = 0;
	unsigned int pmc_inuse = 0;

	if (n_ev > 6)
		return -1;
	for (i = 0; i < n_ev; ++i) {
		pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
		if (pmc) {
			if (pmc_inuse & (1 << (pmc - 1)))
				return -1;	/* collision! */
			pmc_inuse |= 1 << (pmc - 1);
		}
	}
	for (i = 0; i < n_ev; ++i) {
		ev = event[i];
		pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
		if (pmc) {
			--pmc;
		} else {
			/* can go on any PMC; find a free one */
			for (pmc = 0; pmc < 4; ++pmc)
				if (!(pmc_inuse & (1 << pmc)))
					break;
			if (pmc >= 4)
				return -1;
			pmc_inuse |= 1 << pmc;
		}
		hwc[i] = pmc;
		psel = ev & PM_PMCSEL_MSK;
		if (ev & PM_BUSEVENT_MSK) {
			/* this event uses the event bus */
			b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
			u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
			/* check for conflict on this byte of event bus */
			if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
				return -1;
			mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
			ttmset |= 1 << b;
			if (u == 5) {
				/* Nest events have a further mux */
				s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
				if ((ttmset & 0x10) &&
				    MMCR1_NESTSEL(mmcr1) != s)
					return -1;
				ttmset |= 0x10;
				mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
			}
			if (0x30 <= psel && psel <= 0x3d) {
				/* these need the PMCx_ADDR_SEL bits */
				if (b >= 2)
					mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
			}
			/* bus select values are different for PMC3/4 */
			if (pmc >= 2 && (psel & 0x90) == 0x80)
				psel ^= 0x20;
		}
		if (ev & PM_LLA) {
			mmcr1 |= MMCR1_PMC1_LLA >> pmc;
			if (ev & PM_LLAV)
				mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
		}
		if (power6_marked_instr_event(event[i]))
			mmcra |= MMCRA_SAMPLE_ENABLE;
		if (pmc < 4)
			mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
	}
	mmcr[0] = 0;
	if (pmc_inuse & 1)
		mmcr[0] = MMCR0_PMC1CE;
	if (pmc_inuse & 0xe)
		mmcr[0] |= MMCR0_PMCjCE;
	mmcr[1] = mmcr1;
	mmcr[2] = mmcra;
	return 0;
}

/*
 * Layout of constraint bits:
 *
 *	0-1	add field: number of uses of PMC1 (max 1)
 *	2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
 *	12-15	add field: number of uses of PMC1-4 (max 4)
 *	16-19	select field: unit on byte 0 of event bus
 *	20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
 *	32-34	select field: nest (subunit) event selector
 */
static int p6_get_constraint(u64 event, unsigned long *maskp,
			     unsigned long *valp)
{
	int pmc, byte, sh, subunit;
	unsigned long mask = 0, value = 0;

	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	if (pmc) {
		if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
			return -1;
		sh = (pmc - 1) * 2;
		mask |= 2 << sh;
		value |= 1 << sh;
	}
	if (event & PM_BUSEVENT_MSK) {
		byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
		sh = byte * 4 + (16 - PM_UNIT_SH);
		mask |= PM_UNIT_MSKS << sh;
		value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
		if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
			subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
			mask  |= (unsigned long)PM_SUBUNIT_MSK << 32;
			value |= (unsigned long)subunit << 32;
		}
	}
	if (pmc <= 4) {
		mask  |= 0x8000;	/* add field for count of PMC1-4 uses */
		value |= 0x1000;
	}
	*maskp = mask;
	*valp = value;
	return 0;
}

static int p6_limited_pmc_event(u64 event)
{
	int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;

	return pmc == 5 || pmc == 6;
}

#define MAX_ALT	4	/* at most 4 alternatives for any event */

static const unsigned int event_alternatives[][MAX_ALT] = {
	{ 0x0130e8, 0x2000f6, 0x3000fc },	/* PM_PTEG_RELOAD_VALID */
	{ 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
	{ 0x080088, 0x200054, 0x3000f0 },	/* PM_ST_MISS_L1 */
	{ 0x10000a, 0x2000f4, 0x600005 },	/* PM_RUN_CYC */
	{ 0x10000b, 0x2000f5 },			/* PM_RUN_COUNT */
	{ 0x10000e, 0x400010 },			/* PM_PURR */
	{ 0x100010, 0x4000f8 },			/* PM_FLUSH */
	{ 0x10001a, 0x200010 },			/* PM_MRK_INST_DISP */
	{ 0x100026, 0x3000f8 },			/* PM_TB_BIT_TRANS */
	{ 0x100054, 0x2000f0 },			/* PM_ST_FIN */
	{ 0x100056, 0x2000fc },			/* PM_L1_ICACHE_MISS */
	{ 0x1000f0, 0x40000a },			/* PM_INST_IMC_MATCH_CMPL */
	{ 0x1000f8, 0x200008 },			/* PM_GCT_EMPTY_CYC */
	{ 0x1000fc, 0x400006 },			/* PM_LSU_DERAT_MISS_CYC */
	{ 0x20000e, 0x400007 },			/* PM_LSU_DERAT_MISS */
	{ 0x200012, 0x300012 },			/* PM_INST_DISP */
	{ 0x2000f2, 0x3000f2 },			/* PM_INST_DISP */
	{ 0x2000f8, 0x300010 },			/* PM_EXT_INT */
	{ 0x2000fe, 0x300056 },			/* PM_DATA_FROM_L2MISS */
	{ 0x2d0030, 0x30001a },			/* PM_MRK_FPU_FIN */
	{ 0x30000a, 0x400018 },			/* PM_MRK_INST_FIN */
	{ 0x3000f6, 0x40000e },			/* PM_L1_DCACHE_RELOAD_VALID */
	{ 0x3000fe, 0x400056 },			/* PM_DATA_FROM_L3MISS */
};

/*
 * This could be made more efficient with a binary search on
 * a presorted list, if necessary
 */
static int find_alternatives_list(u64 event)
{
	int i, j;
	unsigned int alt;

	for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
		if (event < event_alternatives[i][0])
			return -1;
		for (j = 0; j < MAX_ALT; ++j) {
			alt = event_alternatives[i][j];
			if (!alt || event < alt)
				break;
			if (event == alt)
				return i;
		}
	}
	return -1;
}

static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
{
	int i, j, nlim;
	unsigned int psel, pmc;
	unsigned int nalt = 1;
	u64 aevent;

	alt[0] = event;
	nlim = p6_limited_pmc_event(event);

	/* check the alternatives table */
	i = find_alternatives_list(event);
	if (i >= 0) {
		/* copy out alternatives from list */
		for (j = 0; j < MAX_ALT; ++j) {
			aevent = event_alternatives[i][j];
			if (!aevent)
				break;
			if (aevent != event)
				alt[nalt++] = aevent;
			nlim += p6_limited_pmc_event(aevent);
		}

	} else {
		/* Check for alternative ways of computing sum events */
		/* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
		psel = event & (PM_PMCSEL_MSK & ~1);	/* ignore edge bit */
		pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
		if (pmc && (psel == 0x32 || psel == 0x34))
			alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
				((5 - pmc) << PM_PMC_SH);

		/* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
		if (pmc && (psel == 0x38 || psel == 0x3a))
			alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
				((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
	}

	if (flags & PPMU_ONLY_COUNT_RUN) {
		/*
		 * We're only counting in RUN state,
		 * so PM_CYC is equivalent to PM_RUN_CYC,
		 * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
		 * This doesn't include alternatives that don't provide
		 * any extra flexibility in assigning PMCs (e.g.
		 * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
		 * Note that even with these additional alternatives
		 * we never end up with more than 4 alternatives for any event.
		 */
		j = nalt;
		for (i = 0; i < nalt; ++i) {
			switch (alt[i]) {
			case 0x1e:	/* PM_CYC */
				alt[j++] = 0x600005;	/* PM_RUN_CYC */
				++nlim;
				break;
			case 0x10000a:	/* PM_RUN_CYC */
				alt[j++] = 0x1e;	/* PM_CYC */
				break;
			case 2:		/* PM_INST_CMPL */
				alt[j++] = 0x500009;	/* PM_RUN_INST_CMPL */
				++nlim;
				break;
			case 0x500009:	/* PM_RUN_INST_CMPL */
				alt[j++] = 2;		/* PM_INST_CMPL */
				break;
			case 0x10000e:	/* PM_PURR */
				alt[j++] = 0x4000f4;	/* PM_RUN_PURR */
				break;
			case 0x4000f4:	/* PM_RUN_PURR */
				alt[j++] = 0x10000e;	/* PM_PURR */
				break;
			}
		}
		nalt = j;
	}

	if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
		/* remove the limited PMC events */
		j = 0;
		for (i = 0; i < nalt; ++i) {
			if (!p6_limited_pmc_event(alt[i])) {
				alt[j] = alt[i];
				++j;
			}
		}
		nalt = j;
	} else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
		/* remove all but the limited PMC events */
		j = 0;
		for (i = 0; i < nalt; ++i) {
			if (p6_limited_pmc_event(alt[i])) {
				alt[j] = alt[i];
				++j;
			}
		}
		nalt = j;
	}

	return nalt;
}

static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{
	/* Set PMCxSEL to 0 to disable PMCx */
	if (pmc <= 3)
		mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
}

static int power6_generic_events[] = {
	[PERF_COUNT_HW_CPU_CYCLES]		= 0x1e,
	[PERF_COUNT_HW_INSTRUCTIONS]		= 2,
	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0x280030, /* LD_REF_L1 */
	[PERF_COUNT_HW_CACHE_MISSES]		= 0x30000c, /* LD_MISS_L1 */
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x410a0,  /* BR_PRED */
	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x400052, /* BR_MPRED */
};

#define C(x)	PERF_COUNT_HW_CACHE_##x

/*
 * Table of generalized cache-related events.
 * 0 means not supported, -1 means nonsensical, other values
 * are event codes.
 * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
 */
static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0x280030,	0x80080		},
		[C(OP_WRITE)] = {	0x180032,	0x80088		},
		[C(OP_PREFETCH)] = {	0x810a4,	0		},
	},
	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x100056 	},
		[C(OP_WRITE)] = {	-1,		-1		},
		[C(OP_PREFETCH)] = {	0x4008c,	0		},
	},
	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0x150730,	0x250532	},
		[C(OP_WRITE)] = {	0x250432,	0x150432	},
		[C(OP_PREFETCH)] = {	0x810a6,	0		},
	},
	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x20000e	},
		[C(OP_WRITE)] = {	-1,		-1		},
		[C(OP_PREFETCH)] = {	-1,		-1		},
	},
	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x420ce		},
		[C(OP_WRITE)] = {	-1,		-1		},
		[C(OP_PREFETCH)] = {	-1,		-1		},
	},
	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0x430e6,	0x400052	},
		[C(OP_WRITE)] = {	-1,		-1		},
		[C(OP_PREFETCH)] = {	-1,		-1		},
	},
	[C(NODE)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	-1,		-1		},
		[C(OP_WRITE)] = {	-1,		-1		},
		[C(OP_PREFETCH)] = {	-1,		-1		},
	},
};

static struct power_pmu power6_pmu = {
	.name			= "POWER6",
	.n_counter		= 6,
	.max_alternatives	= MAX_ALT,
	.add_fields		= 0x1555,
	.test_adder		= 0x3000,
	.compute_mmcr		= p6_compute_mmcr,
	.get_constraint		= p6_get_constraint,
	.get_alternatives	= p6_get_alternatives,
	.disable_pmc		= p6_disable_pmc,
	.limited_pmc_event	= p6_limited_pmc_event,
	.flags			= PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
	.n_generic		= ARRAY_SIZE(power6_generic_events),
	.generic_events		= power6_generic_events,
	.cache_events		= &power6_cache_events,
};

int init_power6_pmu(void)
{
	if (!cur_cpu_spec->oprofile_cpu_type ||
	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
		return -ENODEV;

	return register_power_pmu(&power6_pmu);
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
f7862837 PM	2	/*
	3	* Performance counter support for POWER6 processors.
	4	*
	5	* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
f7862837 PM	6	*/
f7862837 PM	7	#include <linux/kernel.h>
cdd6c482	8	#include <linux/perf_event.h>
079b3c56	9	#include <linux/string.h>
f7862837	10	#include <asm/reg.h>
079b3c56	11	#include <asm/cputable.h>
f7862837 PM	12
	13	/*
	14	* Bits in event code for POWER6
	15	*/
	16	#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
	17	#define PM_PMC_MSK 0x7
	18	#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
	19	#define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */
	20	#define PM_UNIT_MSK 0xf
	21	#define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH)
	22	#define PM_LLAV 0x8000 /* Load lookahead match value */
	23	#define PM_LLA 0x4000 /* Load lookahead match enable */
	24	#define PM_BYTE_SH 12 /* Byte of event bus to use */
	25	#define PM_BYTE_MSK 3
	26	#define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */
	27	#define PM_SUBUNIT_MSK 7
	28	#define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
	29	#define PM_PMCSEL_MSK 0xff /* PMCxSEL value */
	30	#define PM_BUSEVENT_MSK 0xf3700
	31
	32	/*
	33	* Bits in MMCR1 for POWER6
	34	*/
	35	#define MMCR1_TTM0SEL_SH 60
	36	#define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
	37	#define MMCR1_TTMSEL_MSK 0xf
	38	#define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
	39	#define MMCR1_NESTSEL_SH 45
	40	#define MMCR1_NESTSEL_MSK 0x7
	41	#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
448d64f8 PM	42	#define MMCR1_PMC1_LLA (1ul << 44)
	43	#define MMCR1_PMC1_LLA_VALUE (1ul << 39)
	44	#define MMCR1_PMC1_ADDR_SEL (1ul << 35)
f7862837 PM	45	#define MMCR1_PMC1SEL_SH 24
	46	#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
	47	#define MMCR1_PMCSEL_MSK 0xff
	48
f708223d PM	49	/*
	50	* Map of which direct events on which PMCs are marked instruction events.
	51	* Indexed by PMCSEL value >> 1.
	52	* Bottom 4 bits are a map of which PMCs are interesting,
	53	* top 4 bits say what sort of event:
	54	* 0 = direct marked event,
	55	* 1 = byte decode event,
	56	* 4 = add/and event (PMC1 -> bits 0 & 4),
	57	* 5 = add/and event (PMC1 -> bits 1 & 5),
	58	* 6 = add/and event (PMC1 -> bits 2 & 6),
	59	* 7 = add/and event (PMC1 -> bits 3 & 7).
	60	*/
	61	static unsigned char direct_event_is_marked[0x60 >> 1] = {
	62	0, /* 00 */
	63	0, /* 02 */
	64	0, /* 04 */
	65	0x07, /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
	66	0x04, /* 08 PM_MRK_DFU_FIN */
	67	0x06, /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
	68	0, /* 0c */
	69	0, /* 0e */
	70	0x02, /* 10 PM_MRK_INST_DISP */
	71	0x08, /* 12 PM_MRK_LSU_DERAT_MISS */
	72	0, /* 14 */
	73	0, /* 16 */
	74	0x0c, /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
	75	0x0f, /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
	76	0x01, /* 1c PM_MRK_INST_ISSUED */
	77	0, /* 1e */
	78	0, /* 20 */
	79	0, /* 22 */
	80	0, /* 24 */
	81	0, /* 26 */
	82	0x15, /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
	83	0, /* 2a */
	84	0, /* 2c */
	85	0, /* 2e */
	86	0x4f, /* 30 */
	87	0x7f, /* 32 */
	88	0x4f, /* 34 */
	89	0x5f, /* 36 */
	90	0x6f, /* 38 */
	91	0x4f, /* 3a */
	92	0, /* 3c */
	93	0x08, /* 3e PM_MRK_INST_TIMEO */
	94	0x1f, /* 40 */
	95	0x1f, /* 42 */
	96	0x1f, /* 44 */
	97	0x1f, /* 46 */
	98	0x1f, /* 48 */
	99	0x1f, /* 4a */
	100	0x1f, /* 4c */
	101	0x1f, /* 4e */
	102	0, /* 50 */
	103	0x05, /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
	104	0x1c, /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
	105	0x02, /* 56 PM_MRK_LD_MISS_L1 */
	106	0, /* 58 */
	107	0, /* 5a */
	108	0, /* 5c */
	109	0, /* 5e */
	110	};
	111
	112	/*
113	* Masks showing for each unit which bits are marked events.
114	* These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
115	*/
116	static u32 marked_bus_events[16] = {
117	0x01000000, /* direct events set 1: byte 3 bit 0 */
118	0x00010000, /* direct events set 2: byte 2 bit 0 */
119	0, 0, 0, 0, /* IDU, IFU, nest: nothing */
120	0x00000088, /* VMX set 1: byte 0 bits 3, 7 */
121	0x000000c0, /* VMX set 2: byte 0 bits 4-7 */
122	0x04010000, /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
123	0xff010000u, /* LSU set 2: byte 2 bit 0, all of byte 3 */
124	0, /* LSU set 3 */
125	0x00000010, /* VMX set 3: byte 0 bit 4 */
126	0, /* BFP set 1 */
127	0x00000022, /* BFP set 2: byte 0 bits 1, 5 */
128	0, 0
129	};
f2699491	130
f708223d PM	131	/*
	132	* Returns 1 if event counts things relating to marked instructions
	133	* and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
	134	*/
ef923214	135	static int power6_marked_instr_event(u64 event)
f708223d PM	136	{
	137	int pmc, psel, ptype;
	138	int bit, byte, unit;
	139	u32 mask;
	140
	141	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	142	psel = (event & PM_PMCSEL_MSK) >> 1; /* drop edge/level bit */
	143	if (pmc >= 5)
	144	return 0;
	145
	146	bit = -1;
	147	if (psel < sizeof(direct_event_is_marked)) {
	148	ptype = direct_event_is_marked[psel];
	149	if (pmc == 0 \|\| !(ptype & (1 << (pmc - 1))))
	150	return 0;
	151	ptype >>= 4;
	152	if (ptype == 0)
	153	return 1;
	154	if (ptype == 1)
	155	bit = 0;
	156	else
	157	bit = ptype ^ (pmc - 1);
	158	} else if ((psel & 0x48) == 0x40)
	159	bit = psel & 7;
	160
	161	if (!(event & PM_BUSEVENT_MSK) \|\| bit == -1)
	162	return 0;
	163
	164	byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
	165	unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
	166	mask = marked_bus_events[unit];
	167	return (mask >> (byte * 8 + bit)) & 1;
	168	}
	169
f7862837 PM	170	/*
	171	* Assign PMC numbers and compute MMCR1 value for a set of events
	172	*/
ef923214	173	static int p6_compute_mmcr(u64 event[], int n_ev,
8abd818f	174	unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
f7862837	175	{
448d64f8	176	unsigned long mmcr1 = 0;
81cd5ae3	177	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS \| MMCRA_SDAR_ERAT_MISS;
f7862837 PM	178	int i;
	179	unsigned int pmc, ev, b, u, s, psel;
	180	unsigned int ttmset = 0;
	181	unsigned int pmc_inuse = 0;
	182
ab7ef2e5	183	if (n_ev > 6)
f7862837 PM	184	return -1;
	185	for (i = 0; i < n_ev; ++i) {
	186	pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
	187	if (pmc) {
	188	if (pmc_inuse & (1 << (pmc - 1)))
	189	return -1; /* collision! */
	190	pmc_inuse \|= 1 << (pmc - 1);
	191	}
	192	}
	193	for (i = 0; i < n_ev; ++i) {
	194	ev = event[i];
	195	pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
	196	if (pmc) {
	197	--pmc;
	198	} else {
	199	/* can go on any PMC; find a free one */
	200	for (pmc = 0; pmc < 4; ++pmc)
	201	if (!(pmc_inuse & (1 << pmc)))
	202	break;
ab7ef2e5 PM	203	if (pmc >= 4)
ab7ef2e5 PM	204	return -1;
f7862837 PM	205	pmc_inuse \|= 1 << pmc;
	206	}
	207	hwc[i] = pmc;
	208	psel = ev & PM_PMCSEL_MSK;
	209	if (ev & PM_BUSEVENT_MSK) {
	210	/* this event uses the event bus */
	211	b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
	212	u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
	213	/* check for conflict on this byte of event bus */
	214	if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
	215	return -1;
448d64f8	216	mmcr1 \|= (unsigned long)u << MMCR1_TTMSEL_SH(b);
f7862837 PM	217	ttmset \|= 1 << b;
	218	if (u == 5) {
	219	/* Nest events have a further mux */
	220	s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
	221	if ((ttmset & 0x10) &&
	222	MMCR1_NESTSEL(mmcr1) != s)
	223	return -1;
	224	ttmset \|= 0x10;
448d64f8	225	mmcr1 \|= (unsigned long)s << MMCR1_NESTSEL_SH;
f7862837 PM	226	}
	227	if (0x30 <= psel && psel <= 0x3d) {
	228	/* these need the PMCx_ADDR_SEL bits */
	229	if (b >= 2)
	230	mmcr1 \|= MMCR1_PMC1_ADDR_SEL >> pmc;
	231	}
	232	/* bus select values are different for PMC3/4 */
	233	if (pmc >= 2 && (psel & 0x90) == 0x80)
	234	psel ^= 0x20;
	235	}
	236	if (ev & PM_LLA) {
	237	mmcr1 \|= MMCR1_PMC1_LLA >> pmc;
	238	if (ev & PM_LLAV)
	239	mmcr1 \|= MMCR1_PMC1_LLA_VALUE >> pmc;
	240	}
f708223d PM	241	if (power6_marked_instr_event(event[i]))
f708223d PM	242	mmcra \|= MMCRA_SAMPLE_ENABLE;
ab7ef2e5	243	if (pmc < 4)
448d64f8	244	mmcr1 \|= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
f7862837 PM	245	}
	246	mmcr[0] = 0;
	247	if (pmc_inuse & 1)
	248	mmcr[0] = MMCR0_PMC1CE;
	249	if (pmc_inuse & 0xe)
	250	mmcr[0] \|= MMCR0_PMCjCE;
	251	mmcr[1] = mmcr1;
f708223d	252	mmcr[2] = mmcra;
f7862837 PM	253	return 0;
	254	}
	255
	256	/*
	257	* Layout of constraint bits:
	258	*
	259	* 0-1 add field: number of uses of PMC1 (max 1)
ab7ef2e5 PM	260	* 2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
ab7ef2e5 PM	261	* 12-15 add field: number of uses of PMC1-4 (max 4)
f7862837 PM	262	* 16-19 select field: unit on byte 0 of event bus
f7862837 PM	263	* 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
ab7ef2e5	264	* 32-34 select field: nest (subunit) event selector
f7862837	265	*/
448d64f8 PM	266	static int p6_get_constraint(u64 event, unsigned long *maskp,
448d64f8 PM	267	unsigned long *valp)
f7862837	268	{
ab7ef2e5	269	int pmc, byte, sh, subunit;
448d64f8	270	unsigned long mask = 0, value = 0;
f7862837 PM	271
	272	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	273	if (pmc) {
ab7ef2e5	274	if (pmc > 4 && !(event == 0x500009 \|\| event == 0x600005))
f7862837 PM	275	return -1;
	276	sh = (pmc - 1) * 2;
	277	mask \|= 2 << sh;
	278	value \|= 1 << sh;
	279	}
	280	if (event & PM_BUSEVENT_MSK) {
	281	byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
ab7ef2e5	282	sh = byte * 4 + (16 - PM_UNIT_SH);
f7862837	283	mask \|= PM_UNIT_MSKS << sh;
448d64f8	284	value \|= (unsigned long)(event & PM_UNIT_MSKS) << sh;
f7862837	285	if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
ab7ef2e5	286	subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
448d64f8 PM	287	mask \|= (unsigned long)PM_SUBUNIT_MSK << 32;
448d64f8 PM	288	value \|= (unsigned long)subunit << 32;
f7862837 PM	289	}
f7862837 PM	290	}
ab7ef2e5 PM	291	if (pmc <= 4) {
	292	mask \|= 0x8000; /* add field for count of PMC1-4 uses */
	293	value \|= 0x1000;
	294	}
f7862837 PM	295	*maskp = mask;
	296	*valp = value;
	297	return 0;
	298	}
	299
ef923214	300	static int p6_limited_pmc_event(u64 event)
ab7ef2e5 PM	301	{
	302	int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	303
	304	return pmc == 5 \|\| pmc == 6;
	305	}
	306
f7862837 PM	307	#define MAX_ALT 4 /* at most 4 alternatives for any event */
	308
	309	static const unsigned int event_alternatives[][MAX_ALT] = {
	310	{ 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */
	311	{ 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
	312	{ 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */
ab7ef2e5	313	{ 0x10000a, 0x2000f4, 0x600005 }, /* PM_RUN_CYC */
f7862837 PM	314	{ 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */
	315	{ 0x10000e, 0x400010 }, /* PM_PURR */
	316	{ 0x100010, 0x4000f8 }, /* PM_FLUSH */
	317	{ 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */
	318	{ 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */
	319	{ 0x100054, 0x2000f0 }, /* PM_ST_FIN */
	320	{ 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */
	321	{ 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */
	322	{ 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */
	323	{ 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */
	324	{ 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */
	325	{ 0x200012, 0x300012 }, /* PM_INST_DISP */
	326	{ 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */
	327	{ 0x2000f8, 0x300010 }, /* PM_EXT_INT */
	328	{ 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */
	329	{ 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */
	330	{ 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */
	331	{ 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */
	332	{ 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */
	333	};
	334
	335	/*
	336	* This could be made more efficient with a binary search on
	337	* a presorted list, if necessary
	338	*/
ef923214	339	static int find_alternatives_list(u64 event)
f7862837 PM	340	{
	341	int i, j;
	342	unsigned int alt;
	343
	344	for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
	345	if (event < event_alternatives[i][0])
	346	return -1;
	347	for (j = 0; j < MAX_ALT; ++j) {
	348	alt = event_alternatives[i][j];
	349	if (!alt \|\| event < alt)
	350	break;
	351	if (event == alt)
	352	return i;
	353	}
	354	}
	355	return -1;
	356	}
	357
ef923214	358	static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
f7862837	359	{
ab7ef2e5	360	int i, j, nlim;
ef923214	361	unsigned int psel, pmc;
f7862837	362	unsigned int nalt = 1;
ef923214	363	u64 aevent;
f7862837 PM	364
f7862837 PM	365	alt[0] = event;
ab7ef2e5	366	nlim = p6_limited_pmc_event(event);
f7862837 PM	367
	368	/* check the alternatives table */
	369	i = find_alternatives_list(event);
	370	if (i >= 0) {
	371	/* copy out alternatives from list */
	372	for (j = 0; j < MAX_ALT; ++j) {
	373	aevent = event_alternatives[i][j];
	374	if (!aevent)
	375	break;
	376	if (aevent != event)
	377	alt[nalt++] = aevent;
ab7ef2e5	378	nlim += p6_limited_pmc_event(aevent);
f7862837 PM	379	}
	380
	381	} else {
	382	/* Check for alternative ways of computing sum events */
	383	/* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
	384	psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */
	385	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	386	if (pmc && (psel == 0x32 \|\| psel == 0x34))
	387	alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) \|
	388	((5 - pmc) << PM_PMC_SH);
	389
	390	/* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
	391	if (pmc && (psel == 0x38 \|\| psel == 0x3a))
	392	alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) \|
	393	((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
	394	}
	395
ab7ef2e5 PM	396	if (flags & PPMU_ONLY_COUNT_RUN) {
	397	/*
	398	* We're only counting in RUN state,
	399	* so PM_CYC is equivalent to PM_RUN_CYC,
	400	* PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
	401	* This doesn't include alternatives that don't provide
	402	* any extra flexibility in assigning PMCs (e.g.
	403	* 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
	404	* Note that even with these additional alternatives
	405	* we never end up with more than 4 alternatives for any event.
	406	*/
	407	j = nalt;
	408	for (i = 0; i < nalt; ++i) {
	409	switch (alt[i]) {
	410	case 0x1e: /* PM_CYC */
	411	alt[j++] = 0x600005; /* PM_RUN_CYC */
	412	++nlim;
	413	break;
	414	case 0x10000a: /* PM_RUN_CYC */
	415	alt[j++] = 0x1e; /* PM_CYC */
	416	break;
	417	case 2: /* PM_INST_CMPL */
	418	alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */
	419	++nlim;
	420	break;
	421	case 0x500009: /* PM_RUN_INST_CMPL */
	422	alt[j++] = 2; /* PM_INST_CMPL */
	423	break;
	424	case 0x10000e: /* PM_PURR */
	425	alt[j++] = 0x4000f4; /* PM_RUN_PURR */
	426	break;
	427	case 0x4000f4: /* PM_RUN_PURR */
	428	alt[j++] = 0x10000e; /* PM_PURR */
	429	break;
	430	}
	431	}
	432	nalt = j;
	433	}
	434
	435	if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
	436	/* remove the limited PMC events */
	437	j = 0;
	438	for (i = 0; i < nalt; ++i) {
	439	if (!p6_limited_pmc_event(alt[i])) {
	440	alt[j] = alt[i];
	441	++j;
	442	}
	443	}
	444	nalt = j;
	445	} else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
	446	/* remove all but the limited PMC events */
	447	j = 0;
	448	for (i = 0; i < nalt; ++i) {
	449	if (p6_limited_pmc_event(alt[i])) {
	450	alt[j] = alt[i];
	451	++j;
	452	}
	453	}
	454	nalt = j;
	455	}
	456
f7862837 PM	457	return nalt;
	458	}
	459
448d64f8	460	static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[])
f7862837 PM	461	{
f7862837 PM	462	/* Set PMCxSEL to 0 to disable PMCx */
ab7ef2e5 PM	463	if (pmc <= 3)
ab7ef2e5 PM	464	mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
f7862837 PM	465	}
	466
	467	static int power6_generic_events[] = {
f4dbfa8f PZ	468	[PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
	469	[PERF_COUNT_HW_INSTRUCTIONS] = 2,
	470	[PERF_COUNT_HW_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */
	471	[PERF_COUNT_HW_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */
	472	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */
	473	[PERF_COUNT_HW_BRANCH_MISSES] = 0x400052, /* BR_MPRED */
f7862837 PM	474	};
f7862837 PM	475
106b506c PM	476	#define C(x) PERF_COUNT_HW_CACHE_##x
	477
	478	/*
	479	* Table of generalized cache-related events.
	480	* 0 means not supported, -1 means nonsensical, other values
	481	* are event codes.
	482	* The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
	483	*/
	484	static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	485	[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
d15f02eb CL	486	[C(OP_READ)] = { 0x280030, 0x80080 },
d15f02eb CL	487	[C(OP_WRITE)] = { 0x180032, 0x80088 },
106b506c PM	488	[C(OP_PREFETCH)] = { 0x810a4, 0 },
	489	},
	490	[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
	491	[C(OP_READ)] = { 0, 0x100056 },
	492	[C(OP_WRITE)] = { -1, -1 },
	493	[C(OP_PREFETCH)] = { 0x4008c, 0 },
	494	},
8be6e8f3	495	[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
106b506c PM	496	[C(OP_READ)] = { 0x150730, 0x250532 },
	497	[C(OP_WRITE)] = { 0x250432, 0x150432 },
	498	[C(OP_PREFETCH)] = { 0x810a6, 0 },
	499	},
	500	[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
	501	[C(OP_READ)] = { 0, 0x20000e },
	502	[C(OP_WRITE)] = { -1, -1 },
	503	[C(OP_PREFETCH)] = { -1, -1 },
	504	},
	505	[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
	506	[C(OP_READ)] = { 0, 0x420ce },
	507	[C(OP_WRITE)] = { -1, -1 },
	508	[C(OP_PREFETCH)] = { -1, -1 },
	509	},
	510	[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
	511	[C(OP_READ)] = { 0x430e6, 0x400052 },
	512	[C(OP_WRITE)] = { -1, -1 },
	513	[C(OP_PREFETCH)] = { -1, -1 },
	514	},
89d6c0b5 PZ	515	[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
	516	[C(OP_READ)] = { -1, -1 },
	517	[C(OP_WRITE)] = { -1, -1 },
	518	[C(OP_PREFETCH)] = { -1, -1 },
	519	},
106b506c PM	520	};
106b506c PM	521
079b3c56 PM	522	static struct power_pmu power6_pmu = {
079b3c56 PM	523	.name = "POWER6",
448d64f8 PM	524	.n_counter = 6,
	525	.max_alternatives = MAX_ALT,
	526	.add_fields = 0x1555,
	527	.test_adder = 0x3000,
	528	.compute_mmcr = p6_compute_mmcr,
	529	.get_constraint = p6_get_constraint,
	530	.get_alternatives = p6_get_alternatives,
	531	.disable_pmc = p6_disable_pmc,
	532	.limited_pmc_event = p6_limited_pmc_event,
	533	.flags = PPMU_LIMITED_PMC5_6 \| PPMU_ALT_SIPR,
	534	.n_generic = ARRAY_SIZE(power6_generic_events),
	535	.generic_events = power6_generic_events,
	536	.cache_events = &power6_cache_events,
f7862837	537	};
079b3c56	538
708597da	539	int init_power6_pmu(void)
079b3c56	540	{
e0d82a0a BH	541	if (!cur_cpu_spec->oprofile_cpu_type \|\|
e0d82a0a BH	542	strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
079b3c56 PM	543	return -ENODEV;
	544
	545	return register_power_pmu(&power6_pmu);
	546	}