[linux-2.6-block.git] / arch / powerpc / perf / mpc7450-pmu.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Performance counter support for MPC7450-family processors.
 *
 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
 */
#include <linux/string.h>
#include <linux/perf_event.h>
#include <asm/reg.h>
#include <asm/cputable.h>

#define N_COUNTER	6	/* Number of hardware counters */
#define MAX_ALT		3	/* Maximum number of event alternative codes */

/*
 * Bits in event code for MPC7450 family
 */
#define PM_THRMULT_MSKS	0x40000
#define PM_THRESH_SH	12
#define PM_THRESH_MSK	0x3f
#define PM_PMC_SH	8
#define PM_PMC_MSK	7
#define PM_PMCSEL_MSK	0x7f

/*
 * Classify events according to how specific their PMC requirements are.
 * Result is:
 *	0: can go on any PMC
 *	1: can go on PMCs 1-4
 *	2: can go on PMCs 1,2,4
 *	3: can go on PMCs 1 or 2
 *	4: can only go on one PMC
 *	-1: event code is invalid
 */
#define N_CLASSES	5

static int mpc7450_classify_event(u32 event)
{
	int pmc;

	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	if (pmc) {
		if (pmc > N_COUNTER)
			return -1;
		return 4;
	}
	event &= PM_PMCSEL_MSK;
	if (event <= 1)
		return 0;
	if (event <= 7)
		return 1;
	if (event <= 13)
		return 2;
	if (event <= 22)
		return 3;
	return -1;
}

/*
 * Events using threshold and possible threshold scale:
 *	code	scale?	name
 *	11e	N	PM_INSTQ_EXCEED_CYC
 *	11f	N	PM_ALTV_IQ_EXCEED_CYC
 *	128	Y	PM_DTLB_SEARCH_EXCEED_CYC
 *	12b	Y	PM_LD_MISS_EXCEED_L1_CYC
 *	220	N	PM_CQ_EXCEED_CYC
 *	30c	N	PM_GPR_RB_EXCEED_CYC
 *	30d	?	PM_FPR_IQ_EXCEED_CYC ?
 *	311	Y	PM_ITLB_SEARCH_EXCEED
 *	410	N	PM_GPR_IQ_EXCEED_CYC
 */

/*
 * Return use of threshold and threshold scale bits:
 * 0 = uses neither, 1 = uses threshold, 2 = uses both
 */
static int mpc7450_threshold_use(u32 event)
{
	int pmc, sel;

	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	sel = event & PM_PMCSEL_MSK;
	switch (pmc) {
	case 1:
		if (sel == 0x1e || sel == 0x1f)
			return 1;
		if (sel == 0x28 || sel == 0x2b)
			return 2;
		break;
	case 2:
		if (sel == 0x20)
			return 1;
		break;
	case 3:
		if (sel == 0xc || sel == 0xd)
			return 1;
		if (sel == 0x11)
			return 2;
		break;
	case 4:
		if (sel == 0x10)
			return 1;
		break;
	}
	return 0;
}

/*
 * Layout of constraint bits:
 * 33222222222211111111110000000000
 * 10987654321098765432109876543210
 *  |<    ><  > < > < ><><><><><><>
 *  TS TV   G4   G3  G2P6P5P4P3P2P1
 *
 * P1 - P6
 *	0 - 11: Count of events needing PMC1 .. PMC6
 *
 * G2
 *	12 - 14: Count of events needing PMC1 or PMC2
 *
 * G3
 *	16 - 18: Count of events needing PMC1, PMC2 or PMC4
 *
 * G4
 *	20 - 23: Count of events needing PMC1, PMC2, PMC3 or PMC4
 *
 * TV
 *	24 - 29: Threshold value requested
 *
 * TS
 *	30: Threshold scale value requested
 */

static u32 pmcbits[N_COUNTER][2] = {
	{ 0x00844002, 0x00111001 },	/* PMC1 mask, value: P1,G2,G3,G4 */
	{ 0x00844008, 0x00111004 },	/* PMC2: P2,G2,G3,G4 */
	{ 0x00800020, 0x00100010 },	/* PMC3: P3,G4 */
	{ 0x00840080, 0x00110040 },	/* PMC4: P4,G3,G4 */
	{ 0x00000200, 0x00000100 },	/* PMC5: P5 */
	{ 0x00000800, 0x00000400 }	/* PMC6: P6 */
};

static u32 classbits[N_CLASSES - 1][2] = {
	{ 0x00000000, 0x00000000 },	/* class 0: no constraint */
	{ 0x00800000, 0x00100000 },	/* class 1: G4 */
	{ 0x00040000, 0x00010000 },	/* class 2: G3 */
	{ 0x00004000, 0x00001000 },	/* class 3: G2 */
};

static int mpc7450_get_constraint(u64 event, unsigned long *maskp,
				  unsigned long *valp)
{
	int pmc, class;
	u32 mask, value;
	int thresh, tuse;

	class = mpc7450_classify_event(event);
	if (class < 0)
		return -1;
	if (class == 4) {
		pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK;
		mask  = pmcbits[pmc - 1][0];
		value = pmcbits[pmc - 1][1];
	} else {
		mask  = classbits[class][0];
		value = classbits[class][1];
	}

	tuse = mpc7450_threshold_use(event);
	if (tuse) {
		thresh = ((unsigned int)event >> PM_THRESH_SH) & PM_THRESH_MSK;
		mask  |= 0x3f << 24;
		value |= thresh << 24;
		if (tuse == 2) {
			mask |= 0x40000000;
			if ((unsigned int)event & PM_THRMULT_MSKS)
				value |= 0x40000000;
		}
	}

	*maskp = mask;
	*valp = value;
	return 0;
}

static const unsigned int event_alternatives[][MAX_ALT] = {
	{ 0x217, 0x317 },		/* PM_L1_DCACHE_MISS */
	{ 0x418, 0x50f, 0x60f },	/* PM_SNOOP_RETRY */
	{ 0x502, 0x602 },		/* PM_L2_HIT */
	{ 0x503, 0x603 },		/* PM_L3_HIT */
	{ 0x504, 0x604 },		/* PM_L2_ICACHE_MISS */
	{ 0x505, 0x605 },		/* PM_L3_ICACHE_MISS */
	{ 0x506, 0x606 },		/* PM_L2_DCACHE_MISS */
	{ 0x507, 0x607 },		/* PM_L3_DCACHE_MISS */
	{ 0x50a, 0x623 },		/* PM_LD_HIT_L3 */
	{ 0x50b, 0x624 },		/* PM_ST_HIT_L3 */
	{ 0x50d, 0x60d },		/* PM_L2_TOUCH_HIT */
	{ 0x50e, 0x60e },		/* PM_L3_TOUCH_HIT */
	{ 0x512, 0x612 },		/* PM_INT_LOCAL */
	{ 0x513, 0x61d },		/* PM_L2_MISS */
	{ 0x514, 0x61e },		/* PM_L3_MISS */
};

/*
 * Scan the alternatives table for a match and return the
 * index into the alternatives table if found, else -1.
 */
static int find_alternative(u32 event)
{
	int i, j;

	for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
		if (event < event_alternatives[i][0])
			break;
		for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
			if (event == event_alternatives[i][j])
				return i;
	}
	return -1;
}

static int mpc7450_get_alternatives(u64 event, unsigned int flags, u64 alt[])
{
	int i, j, nalt = 1;
	u32 ae;

	alt[0] = event;
	nalt = 1;
	i = find_alternative((u32)event);
	if (i >= 0) {
		for (j = 0; j < MAX_ALT; ++j) {
			ae = event_alternatives[i][j];
			if (ae && ae != (u32)event)
				alt[nalt++] = ae;
		}
	}
	return nalt;
}

/*
 * Bitmaps of which PMCs each class can use for classes 0 - 3.
 * Bit i is set if PMC i+1 is usable.
 */
static const u8 classmap[N_CLASSES] = {
	0x3f, 0x0f, 0x0b, 0x03, 0
};

/* Bit position and width of each PMCSEL field */
static const int pmcsel_shift[N_COUNTER] = {
	6,	0,	27,	22,	17,	11
};
static const u32 pmcsel_mask[N_COUNTER] = {
	0x7f,	0x3f,	0x1f,	0x1f,	0x1f,	0x3f
};

/*
 * Compute MMCR0/1/2 values for a set of events.
 */
static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[],
				unsigned long mmcr[],
				struct perf_event *pevents[])
{
	u8 event_index[N_CLASSES][N_COUNTER];
	int n_classevent[N_CLASSES];
	int i, j, class, tuse;
	u32 pmc_inuse = 0, pmc_avail;
	u32 mmcr0 = 0, mmcr1 = 0, mmcr2 = 0;
	u32 ev, pmc, thresh;

	if (n_ev > N_COUNTER)
		return -1;

	/* First pass: count usage in each class */
	for (i = 0; i < N_CLASSES; ++i)
		n_classevent[i] = 0;
	for (i = 0; i < n_ev; ++i) {
		class = mpc7450_classify_event(event[i]);
		if (class < 0)
			return -1;
		j = n_classevent[class]++;
		event_index[class][j] = i;
	}

	/* Second pass: allocate PMCs from most specific event to least */
	for (class = N_CLASSES - 1; class >= 0; --class) {
		for (i = 0; i < n_classevent[class]; ++i) {
			ev = event[event_index[class][i]];
			if (class == 4) {
				pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
				if (pmc_inuse & (1 << (pmc - 1)))
					return -1;
			} else {
				/* Find a suitable PMC */
				pmc_avail = classmap[class] & ~pmc_inuse;
				if (!pmc_avail)
					return -1;
				pmc = ffs(pmc_avail);
			}
			pmc_inuse |= 1 << (pmc - 1);

			tuse = mpc7450_threshold_use(ev);
			if (tuse) {
				thresh = (ev >> PM_THRESH_SH) & PM_THRESH_MSK;
				mmcr0 |= thresh << 16;
				if (tuse == 2 && (ev & PM_THRMULT_MSKS))
					mmcr2 = 0x80000000;
			}
			ev &= pmcsel_mask[pmc - 1];
			ev <<= pmcsel_shift[pmc - 1];
			if (pmc <= 2)
				mmcr0 |= ev;
			else
				mmcr1 |= ev;
			hwc[event_index[class][i]] = pmc - 1;
		}
	}

	if (pmc_inuse & 1)
		mmcr0 |= MMCR0_PMC1CE;
	if (pmc_inuse & 0x3e)
		mmcr0 |= MMCR0_PMCnCE;

	/* Return MMCRx values */
	mmcr[0] = mmcr0;
	mmcr[1] = mmcr1;
	mmcr[2] = mmcr2;
	return 0;
}

/*
 * Disable counting by a PMC.
 * Note that the pmc argument is 0-based here, not 1-based.
 */
static void mpc7450_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{
	if (pmc <= 1)
		mmcr[0] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
	else
		mmcr[1] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
}

static int mpc7450_generic_events[] = {
	[PERF_COUNT_HW_CPU_CYCLES]		= 1,
	[PERF_COUNT_HW_INSTRUCTIONS]		= 2,
	[PERF_COUNT_HW_CACHE_MISSES]		= 0x217, /* PM_L1_DCACHE_MISS */
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x122, /* PM_BR_CMPL */
	[PERF_COUNT_HW_BRANCH_MISSES] 		= 0x41c, /* PM_BR_MPRED */
};

#define C(x)	PERF_COUNT_HW_CACHE_##x

/*
 * Table of generalized cache-related events.
 * 0 means not supported, -1 means nonsensical, other values
 * are event codes.
 */
static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x225	},
		[C(OP_WRITE)] = {	0,		0x227	},
		[C(OP_PREFETCH)] = {	0,		0	},
	},
	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0x129,		0x115	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	0x634,		0	},
	},
	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0	},
		[C(OP_WRITE)] = {	0,		0	},
		[C(OP_PREFETCH)] = {	0,		0	},
	},
	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x312	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0,		0x223	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	0x122,		0x41c	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(NODE)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	-1,		-1	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
};

struct power_pmu mpc7450_pmu = {
	.name			= "MPC7450 family",
	.n_counter		= N_COUNTER,
	.max_alternatives	= MAX_ALT,
	.add_fields		= 0x00111555ul,
	.test_adder		= 0x00301000ul,
	.compute_mmcr		= mpc7450_compute_mmcr,
	.get_constraint		= mpc7450_get_constraint,
	.get_alternatives	= mpc7450_get_alternatives,
	.disable_pmc		= mpc7450_disable_pmc,
	.n_generic		= ARRAY_SIZE(mpc7450_generic_events),
	.generic_events		= mpc7450_generic_events,
	.cache_events		= &mpc7450_cache_events,
};

static int __init init_mpc7450_pmu(void)
{
	if (!cur_cpu_spec->oprofile_cpu_type ||
	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
		return -ENODEV;

	return register_power_pmu(&mpc7450_pmu);
}

early_initcall(init_mpc7450_pmu);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
7325927e PM	2	/*
	3	* Performance counter support for MPC7450-family processors.
	4	*
	5	* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
7325927e PM	6	*/
7325927e PM	7	#include <linux/string.h>
cdd6c482	8	#include <linux/perf_event.h>
7325927e PM	9	#include <asm/reg.h>
	10	#include <asm/cputable.h>
	11
	12	#define N_COUNTER 6 /* Number of hardware counters */
	13	#define MAX_ALT 3 /* Maximum number of event alternative codes */
	14
	15	/*
	16	* Bits in event code for MPC7450 family
	17	*/
	18	#define PM_THRMULT_MSKS 0x40000
	19	#define PM_THRESH_SH 12
	20	#define PM_THRESH_MSK 0x3f
	21	#define PM_PMC_SH 8
	22	#define PM_PMC_MSK 7
	23	#define PM_PMCSEL_MSK 0x7f
	24
	25	/*
	26	* Classify events according to how specific their PMC requirements are.
	27	* Result is:
	28	* 0: can go on any PMC
	29	* 1: can go on PMCs 1-4
	30	* 2: can go on PMCs 1,2,4
	31	* 3: can go on PMCs 1 or 2
	32	* 4: can only go on one PMC
	33	* -1: event code is invalid
	34	*/
	35	#define N_CLASSES 5
	36
	37	static int mpc7450_classify_event(u32 event)
	38	{
	39	int pmc;
	40
	41	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
	42	if (pmc) {
	43	if (pmc > N_COUNTER)
	44	return -1;
	45	return 4;
	46	}
	47	event &= PM_PMCSEL_MSK;
	48	if (event <= 1)
	49	return 0;
	50	if (event <= 7)
	51	return 1;
	52	if (event <= 13)
	53	return 2;
	54	if (event <= 22)
	55	return 3;
	56	return -1;
	57	}
	58
	59	/*
	60	* Events using threshold and possible threshold scale:
	61	* code scale? name
	62	* 11e N PM_INSTQ_EXCEED_CYC
	63	* 11f N PM_ALTV_IQ_EXCEED_CYC
	64	* 128 Y PM_DTLB_SEARCH_EXCEED_CYC
	65	* 12b Y PM_LD_MISS_EXCEED_L1_CYC
	66	* 220 N PM_CQ_EXCEED_CYC
	67	* 30c N PM_GPR_RB_EXCEED_CYC
	68	* 30d ? PM_FPR_IQ_EXCEED_CYC ?
	69	* 311 Y PM_ITLB_SEARCH_EXCEED
	70	* 410 N PM_GPR_IQ_EXCEED_CYC
	71	*/
	72
73	/*
74	* Return use of threshold and threshold scale bits:
75	* 0 = uses neither, 1 = uses threshold, 2 = uses both
76	*/
77	static int mpc7450_threshold_use(u32 event)
78	{
79	int pmc, sel;
80
81	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
82	sel = event & PM_PMCSEL_MSK;
83	switch (pmc) {
84	case 1:
85	if (sel == 0x1e \|\| sel == 0x1f)
86	return 1;
87	if (sel == 0x28 \|\| sel == 0x2b)
88	return 2;
89	break;
90	case 2:
91	if (sel == 0x20)
92	return 1;
93	break;
94	case 3:
95	if (sel == 0xc \|\| sel == 0xd)
96	return 1;
97	if (sel == 0x11)
98	return 2;
99	break;
100	case 4:
101	if (sel == 0x10)
102	return 1;
103	break;
104	}
105	return 0;
106	}
107
108	/*
109	* Layout of constraint bits:
110	* 33222222222211111111110000000000
111	* 10987654321098765432109876543210
112	* \|< >< > < > < ><><><><><><>
113	* TS TV G4 G3 G2P6P5P4P3P2P1
114	*
115	* P1 - P6
116	* 0 - 11: Count of events needing PMC1 .. PMC6
117	*
118	* G2
119	* 12 - 14: Count of events needing PMC1 or PMC2
120	*
121	* G3
122	* 16 - 18: Count of events needing PMC1, PMC2 or PMC4
123	*
124	* G4
125	* 20 - 23: Count of events needing PMC1, PMC2, PMC3 or PMC4
126	*
127	* TV
128	* 24 - 29: Threshold value requested
129	*
130	* TS
131	* 30: Threshold scale value requested
132	*/
133
134	static u32 pmcbits[N_COUNTER][2] = {
135	{ 0x00844002, 0x00111001 }, /* PMC1 mask, value: P1,G2,G3,G4 */
136	{ 0x00844008, 0x00111004 }, /* PMC2: P2,G2,G3,G4 */
137	{ 0x00800020, 0x00100010 }, /* PMC3: P3,G4 */
138	{ 0x00840080, 0x00110040 }, /* PMC4: P4,G3,G4 */
139	{ 0x00000200, 0x00000100 }, /* PMC5: P5 */
140	{ 0x00000800, 0x00000400 } /* PMC6: P6 */
141	};
142
143	static u32 classbits[N_CLASSES - 1][2] = {
144	{ 0x00000000, 0x00000000 }, /* class 0: no constraint */
145	{ 0x00800000, 0x00100000 }, /* class 1: G4 */
146	{ 0x00040000, 0x00010000 }, /* class 2: G3 */
147	{ 0x00004000, 0x00001000 }, /* class 3: G2 */
148	};
149
150	static int mpc7450_get_constraint(u64 event, unsigned long *maskp,
151	unsigned long *valp)
152	{
153	int pmc, class;
154	u32 mask, value;
155	int thresh, tuse;
156
157	class = mpc7450_classify_event(event);
158	if (class < 0)
159	return -1;
160	if (class == 4) {
161	pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK;
162	mask = pmcbits[pmc - 1][0];
163	value = pmcbits[pmc - 1][1];
164	} else {
165	mask = classbits[class][0];
166	value = classbits[class][1];
167	}
168
169	tuse = mpc7450_threshold_use(event);
170	if (tuse) {
171	thresh = ((unsigned int)event >> PM_THRESH_SH) & PM_THRESH_MSK;
172	mask \|= 0x3f << 24;
173	value \|= thresh << 24;
174	if (tuse == 2) {
175	mask \|= 0x40000000;
176	if ((unsigned int)event & PM_THRMULT_MSKS)
177	value \|= 0x40000000;
178	}
179	}
180
181	*maskp = mask;
182	*valp = value;
183	return 0;
184	}
185
186	static const unsigned int event_alternatives[][MAX_ALT] = {
187	{ 0x217, 0x317 }, /* PM_L1_DCACHE_MISS */
188	{ 0x418, 0x50f, 0x60f }, /* PM_SNOOP_RETRY */
189	{ 0x502, 0x602 }, /* PM_L2_HIT */
190	{ 0x503, 0x603 }, /* PM_L3_HIT */
191	{ 0x504, 0x604 }, /* PM_L2_ICACHE_MISS */
192	{ 0x505, 0x605 }, /* PM_L3_ICACHE_MISS */
193	{ 0x506, 0x606 }, /* PM_L2_DCACHE_MISS */
194	{ 0x507, 0x607 }, /* PM_L3_DCACHE_MISS */
195	{ 0x50a, 0x623 }, /* PM_LD_HIT_L3 */
196	{ 0x50b, 0x624 }, /* PM_ST_HIT_L3 */
197	{ 0x50d, 0x60d }, /* PM_L2_TOUCH_HIT */
198	{ 0x50e, 0x60e }, /* PM_L3_TOUCH_HIT */
199	{ 0x512, 0x612 }, /* PM_INT_LOCAL */
200	{ 0x513, 0x61d }, /* PM_L2_MISS */
201	{ 0x514, 0x61e }, /* PM_L3_MISS */
202	};
203
204	/*
205	* Scan the alternatives table for a match and return the
206	* index into the alternatives table if found, else -1.
207	*/
208	static int find_alternative(u32 event)
209	{
210	int i, j;
211
212	for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
213	if (event < event_alternatives[i][0])
214	break;
215	for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
216	if (event == event_alternatives[i][j])
217	return i;
218	}
219	return -1;
220	}
221
222	static int mpc7450_get_alternatives(u64 event, unsigned int flags, u64 alt[])
223	{
224	int i, j, nalt = 1;
225	u32 ae;
226
227	alt[0] = event;
228	nalt = 1;
229	i = find_alternative((u32)event);
230	if (i >= 0) {
231	for (j = 0; j < MAX_ALT; ++j) {
232	ae = event_alternatives[i][j];
233	if (ae && ae != (u32)event)
234	alt[nalt++] = ae;
235	}
236	}
237	return nalt;
238	}
239
240	/*
241	* Bitmaps of which PMCs each class can use for classes 0 - 3.
242	* Bit i is set if PMC i+1 is usable.
243	*/
244	static const u8 classmap[N_CLASSES] = {
245	0x3f, 0x0f, 0x0b, 0x03, 0
246	};
247
248	/* Bit position and width of each PMCSEL field */
249	static const int pmcsel_shift[N_COUNTER] = {
250	6, 0, 27, 22, 17, 11
251	};
252	static const u32 pmcsel_mask[N_COUNTER] = {
253	0x7f, 0x3f, 0x1f, 0x1f, 0x1f, 0x3f
254	};
255
256	/*
257	* Compute MMCR0/1/2 values for a set of events.
258	*/
8abd818f ME	259	static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[],
	260	unsigned long mmcr[],
	261	struct perf_event *pevents[])
7325927e PM	262	{
	263	u8 event_index[N_CLASSES][N_COUNTER];
	264	int n_classevent[N_CLASSES];
	265	int i, j, class, tuse;
	266	u32 pmc_inuse = 0, pmc_avail;
	267	u32 mmcr0 = 0, mmcr1 = 0, mmcr2 = 0;
	268	u32 ev, pmc, thresh;
	269
	270	if (n_ev > N_COUNTER)
	271	return -1;
	272
	273	/* First pass: count usage in each class */
	274	for (i = 0; i < N_CLASSES; ++i)
	275	n_classevent[i] = 0;
	276	for (i = 0; i < n_ev; ++i) {
	277	class = mpc7450_classify_event(event[i]);
	278	if (class < 0)
	279	return -1;
	280	j = n_classevent[class]++;
	281	event_index[class][j] = i;
	282	}
	283
	284	/* Second pass: allocate PMCs from most specific event to least */
	285	for (class = N_CLASSES - 1; class >= 0; --class) {
	286	for (i = 0; i < n_classevent[class]; ++i) {
	287	ev = event[event_index[class][i]];
	288	if (class == 4) {
	289	pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
	290	if (pmc_inuse & (1 << (pmc - 1)))
	291	return -1;
	292	} else {
	293	/* Find a suitable PMC */
	294	pmc_avail = classmap[class] & ~pmc_inuse;
	295	if (!pmc_avail)
	296	return -1;
	297	pmc = ffs(pmc_avail);
	298	}
	299	pmc_inuse \|= 1 << (pmc - 1);
	300
	301	tuse = mpc7450_threshold_use(ev);
	302	if (tuse) {
	303	thresh = (ev >> PM_THRESH_SH) & PM_THRESH_MSK;
	304	mmcr0 \|= thresh << 16;
	305	if (tuse == 2 && (ev & PM_THRMULT_MSKS))
	306	mmcr2 = 0x80000000;
	307	}
	308	ev &= pmcsel_mask[pmc - 1];
	309	ev <<= pmcsel_shift[pmc - 1];
	310	if (pmc <= 2)
	311	mmcr0 \|= ev;
	312	else
	313	mmcr1 \|= ev;
	314	hwc[event_index[class][i]] = pmc - 1;
	315	}
	316	}
	317
	318	if (pmc_inuse & 1)
	319	mmcr0 \|= MMCR0_PMC1CE;
	320	if (pmc_inuse & 0x3e)
	321	mmcr0 \|= MMCR0_PMCnCE;
	322
	323	/* Return MMCRx values */
	324	mmcr[0] = mmcr0;
	325	mmcr[1] = mmcr1;
326	mmcr[2] = mmcr2;
327	return 0;
328	}
329
330	/*
331	* Disable counting by a PMC.
332	* Note that the pmc argument is 0-based here, not 1-based.
333	*/
334	static void mpc7450_disable_pmc(unsigned int pmc, unsigned long mmcr[])
335	{
336	if (pmc <= 1)
337	mmcr[0] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
338	else
339	mmcr[1] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
340	}
341
342	static int mpc7450_generic_events[] = {
343	[PERF_COUNT_HW_CPU_CYCLES] = 1,
344	[PERF_COUNT_HW_INSTRUCTIONS] = 2,
345	[PERF_COUNT_HW_CACHE_MISSES] = 0x217, /* PM_L1_DCACHE_MISS */
346	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x122, /* PM_BR_CMPL */
347	[PERF_COUNT_HW_BRANCH_MISSES] = 0x41c, /* PM_BR_MPRED */
348	};
349
350	#define C(x) PERF_COUNT_HW_CACHE_##x
351
352	/*
353	* Table of generalized cache-related events.
354	* 0 means not supported, -1 means nonsensical, other values
355	* are event codes.
356	*/
357	static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
358	[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
359	[C(OP_READ)] = { 0, 0x225 },
360	[C(OP_WRITE)] = { 0, 0x227 },
361	[C(OP_PREFETCH)] = { 0, 0 },
362	},
363	[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
364	[C(OP_READ)] = { 0x129, 0x115 },
365	[C(OP_WRITE)] = { -1, -1 },
366	[C(OP_PREFETCH)] = { 0x634, 0 },
367	},
368	[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
369	[C(OP_READ)] = { 0, 0 },
370	[C(OP_WRITE)] = { 0, 0 },
371	[C(OP_PREFETCH)] = { 0, 0 },
372	},
373	[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
374	[C(OP_READ)] = { 0, 0x312 },
375	[C(OP_WRITE)] = { -1, -1 },
376	[C(OP_PREFETCH)] = { -1, -1 },
377	},
378	[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
379	[C(OP_READ)] = { 0, 0x223 },
380	[C(OP_WRITE)] = { -1, -1 },
381	[C(OP_PREFETCH)] = { -1, -1 },
382	},
383	[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
384	[C(OP_READ)] = { 0x122, 0x41c },
385	[C(OP_WRITE)] = { -1, -1 },
386	[C(OP_PREFETCH)] = { -1, -1 },
387	},
89d6c0b5 PZ	388	[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
	389	[C(OP_READ)] = { -1, -1 },
	390	[C(OP_WRITE)] = { -1, -1 },
	391	[C(OP_PREFETCH)] = { -1, -1 },
	392	},
7325927e PM	393	};
	394
	395	struct power_pmu mpc7450_pmu = {
	396	.name = "MPC7450 family",
	397	.n_counter = N_COUNTER,
	398	.max_alternatives = MAX_ALT,
	399	.add_fields = 0x00111555ul,
	400	.test_adder = 0x00301000ul,
	401	.compute_mmcr = mpc7450_compute_mmcr,
	402	.get_constraint = mpc7450_get_constraint,
	403	.get_alternatives = mpc7450_get_alternatives,
	404	.disable_pmc = mpc7450_disable_pmc,
	405	.n_generic = ARRAY_SIZE(mpc7450_generic_events),
	406	.generic_events = mpc7450_generic_events,
	407	.cache_events = &mpc7450_cache_events,
	408	};
	409
77c2342a	410	static int __init init_mpc7450_pmu(void)
7325927e	411	{
e0d82a0a BH	412	if (!cur_cpu_spec->oprofile_cpu_type \|\|
e0d82a0a BH	413	strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
7325927e PM	414	return -ENODEV;
	415
	416	return register_power_pmu(&mpc7450_pmu);
	417	}
	418
004417a6	419	early_initcall(init_mpc7450_pmu);