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885dcd70 AS |
1 | /* |
2 | * In-Memory Collection (IMC) Performance Monitor counter support. | |
3 | * | |
4 | * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation. | |
5 | * (C) 2017 Anju T Sudhakar, IBM Corporation. | |
6 | * (C) 2017 Hemant K Shaw, IBM Corporation. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or later version. | |
12 | */ | |
13 | #include <linux/perf_event.h> | |
14 | #include <linux/slab.h> | |
15 | #include <asm/opal.h> | |
16 | #include <asm/imc-pmu.h> | |
17 | #include <asm/cputhreads.h> | |
18 | #include <asm/smp.h> | |
19 | #include <linux/string.h> | |
20 | ||
21 | /* Nest IMC data structures and variables */ | |
22 | ||
23 | /* | |
24 | * Used to avoid races in counting the nest-pmu units during hotplug | |
25 | * register and unregister | |
26 | */ | |
27 | static DEFINE_MUTEX(nest_init_lock); | |
28 | static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc); | |
73ce9aec | 29 | static struct imc_pmu **per_nest_pmu_arr; |
885dcd70 | 30 | static cpumask_t nest_imc_cpumask; |
4851f750 | 31 | static struct imc_pmu_ref *nest_imc_refc; |
885dcd70 AS |
32 | static int nest_pmus; |
33 | ||
39a846db AS |
34 | /* Core IMC data structures and variables */ |
35 | ||
36 | static cpumask_t core_imc_cpumask; | |
4851f750 | 37 | static struct imc_pmu_ref *core_imc_refc; |
39a846db AS |
38 | static struct imc_pmu *core_imc_pmu; |
39 | ||
f74c89bd AS |
40 | /* Thread IMC data structures and variables */ |
41 | ||
42 | static DEFINE_PER_CPU(u64 *, thread_imc_mem); | |
25af86b2 | 43 | static struct imc_pmu *thread_imc_pmu; |
f74c89bd AS |
44 | static int thread_imc_mem_size; |
45 | ||
4851f750 | 46 | static struct imc_pmu *imc_event_to_pmu(struct perf_event *event) |
885dcd70 AS |
47 | { |
48 | return container_of(event->pmu, struct imc_pmu, pmu); | |
49 | } | |
50 | ||
51 | PMU_FORMAT_ATTR(event, "config:0-40"); | |
52 | PMU_FORMAT_ATTR(offset, "config:0-31"); | |
53 | PMU_FORMAT_ATTR(rvalue, "config:32"); | |
54 | PMU_FORMAT_ATTR(mode, "config:33-40"); | |
55 | static struct attribute *imc_format_attrs[] = { | |
56 | &format_attr_event.attr, | |
57 | &format_attr_offset.attr, | |
58 | &format_attr_rvalue.attr, | |
59 | &format_attr_mode.attr, | |
60 | NULL, | |
61 | }; | |
62 | ||
63 | static struct attribute_group imc_format_group = { | |
64 | .name = "format", | |
65 | .attrs = imc_format_attrs, | |
66 | }; | |
67 | ||
68 | /* Get the cpumask printed to a buffer "buf" */ | |
69 | static ssize_t imc_pmu_cpumask_get_attr(struct device *dev, | |
70 | struct device_attribute *attr, | |
71 | char *buf) | |
72 | { | |
73 | struct pmu *pmu = dev_get_drvdata(dev); | |
74 | struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu); | |
75 | cpumask_t *active_mask; | |
76 | ||
885dcd70 AS |
77 | switch(imc_pmu->domain){ |
78 | case IMC_DOMAIN_NEST: | |
79 | active_mask = &nest_imc_cpumask; | |
80 | break; | |
39a846db AS |
81 | case IMC_DOMAIN_CORE: |
82 | active_mask = &core_imc_cpumask; | |
83 | break; | |
885dcd70 AS |
84 | default: |
85 | return 0; | |
86 | } | |
87 | ||
88 | return cpumap_print_to_pagebuf(true, buf, active_mask); | |
89 | } | |
90 | ||
91 | static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL); | |
92 | ||
93 | static struct attribute *imc_pmu_cpumask_attrs[] = { | |
94 | &dev_attr_cpumask.attr, | |
95 | NULL, | |
96 | }; | |
97 | ||
98 | static struct attribute_group imc_pmu_cpumask_attr_group = { | |
99 | .attrs = imc_pmu_cpumask_attrs, | |
100 | }; | |
101 | ||
102 | /* device_str_attr_create : Populate event "name" and string "str" in attribute */ | |
103 | static struct attribute *device_str_attr_create(const char *name, const char *str) | |
104 | { | |
105 | struct perf_pmu_events_attr *attr; | |
106 | ||
107 | attr = kzalloc(sizeof(*attr), GFP_KERNEL); | |
108 | if (!attr) | |
109 | return NULL; | |
110 | sysfs_attr_init(&attr->attr.attr); | |
111 | ||
112 | attr->event_str = str; | |
113 | attr->attr.attr.name = name; | |
114 | attr->attr.attr.mode = 0444; | |
115 | attr->attr.show = perf_event_sysfs_show; | |
116 | ||
117 | return &attr->attr.attr; | |
118 | } | |
119 | ||
8b4e6dea AS |
120 | static int imc_parse_event(struct device_node *np, const char *scale, |
121 | const char *unit, const char *prefix, | |
122 | u32 base, struct imc_events *event) | |
885dcd70 | 123 | { |
885dcd70 AS |
124 | const char *s; |
125 | u32 reg; | |
126 | ||
885dcd70 AS |
127 | if (of_property_read_u32(np, "reg", ®)) |
128 | goto error; | |
129 | /* Add the base_reg value to the "reg" */ | |
130 | event->value = base + reg; | |
131 | ||
132 | if (of_property_read_string(np, "event-name", &s)) | |
133 | goto error; | |
134 | ||
135 | event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s); | |
136 | if (!event->name) | |
137 | goto error; | |
138 | ||
139 | if (of_property_read_string(np, "scale", &s)) | |
140 | s = scale; | |
141 | ||
142 | if (s) { | |
143 | event->scale = kstrdup(s, GFP_KERNEL); | |
144 | if (!event->scale) | |
145 | goto error; | |
146 | } | |
147 | ||
148 | if (of_property_read_string(np, "unit", &s)) | |
149 | s = unit; | |
150 | ||
151 | if (s) { | |
152 | event->unit = kstrdup(s, GFP_KERNEL); | |
153 | if (!event->unit) | |
154 | goto error; | |
155 | } | |
156 | ||
8b4e6dea | 157 | return 0; |
885dcd70 AS |
158 | error: |
159 | kfree(event->unit); | |
160 | kfree(event->scale); | |
161 | kfree(event->name); | |
8b4e6dea AS |
162 | return -EINVAL; |
163 | } | |
164 | ||
165 | /* | |
166 | * imc_free_events: Function to cleanup the events list, having | |
167 | * "nr_entries". | |
168 | */ | |
169 | static void imc_free_events(struct imc_events *events, int nr_entries) | |
170 | { | |
171 | int i; | |
172 | ||
173 | /* Nothing to clean, return */ | |
174 | if (!events) | |
175 | return; | |
176 | for (i = 0; i < nr_entries; i++) { | |
177 | kfree(events[i].unit); | |
178 | kfree(events[i].scale); | |
179 | kfree(events[i].name); | |
180 | } | |
885dcd70 | 181 | |
8b4e6dea | 182 | kfree(events); |
885dcd70 AS |
183 | } |
184 | ||
185 | /* | |
186 | * update_events_in_group: Update the "events" information in an attr_group | |
187 | * and assign the attr_group to the pmu "pmu". | |
188 | */ | |
189 | static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu) | |
190 | { | |
191 | struct attribute_group *attr_group; | |
192 | struct attribute **attrs, *dev_str; | |
193 | struct device_node *np, *pmu_events; | |
885dcd70 | 194 | u32 handle, base_reg; |
8b4e6dea | 195 | int i = 0, j = 0, ct, ret; |
885dcd70 AS |
196 | const char *prefix, *g_scale, *g_unit; |
197 | const char *ev_val_str, *ev_scale_str, *ev_unit_str; | |
198 | ||
199 | if (!of_property_read_u32(node, "events", &handle)) | |
200 | pmu_events = of_find_node_by_phandle(handle); | |
201 | else | |
202 | return 0; | |
203 | ||
204 | /* Did not find any node with a given phandle */ | |
205 | if (!pmu_events) | |
206 | return 0; | |
207 | ||
208 | /* Get a count of number of child nodes */ | |
209 | ct = of_get_child_count(pmu_events); | |
210 | ||
211 | /* Get the event prefix */ | |
212 | if (of_property_read_string(node, "events-prefix", &prefix)) | |
213 | return 0; | |
214 | ||
215 | /* Get a global unit and scale data if available */ | |
216 | if (of_property_read_string(node, "scale", &g_scale)) | |
217 | g_scale = NULL; | |
218 | ||
219 | if (of_property_read_string(node, "unit", &g_unit)) | |
220 | g_unit = NULL; | |
221 | ||
222 | /* "reg" property gives out the base offset of the counters data */ | |
223 | of_property_read_u32(node, "reg", &base_reg); | |
224 | ||
225 | /* Allocate memory for the events */ | |
226 | pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL); | |
227 | if (!pmu->events) | |
228 | return -ENOMEM; | |
229 | ||
230 | ct = 0; | |
231 | /* Parse the events and update the struct */ | |
232 | for_each_child_of_node(pmu_events, np) { | |
8b4e6dea AS |
233 | ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]); |
234 | if (!ret) | |
235 | ct++; | |
885dcd70 AS |
236 | } |
237 | ||
238 | /* Allocate memory for attribute group */ | |
239 | attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL); | |
8b4e6dea AS |
240 | if (!attr_group) { |
241 | imc_free_events(pmu->events, ct); | |
885dcd70 | 242 | return -ENOMEM; |
8b4e6dea | 243 | } |
885dcd70 AS |
244 | |
245 | /* | |
246 | * Allocate memory for attributes. | |
247 | * Since we have count of events for this pmu, we also allocate | |
248 | * memory for the scale and unit attribute for now. | |
249 | * "ct" has the total event structs added from the events-parent node. | |
250 | * So allocate three times the "ct" (this includes event, event_scale and | |
251 | * event_unit). | |
252 | */ | |
253 | attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL); | |
254 | if (!attrs) { | |
255 | kfree(attr_group); | |
8b4e6dea | 256 | imc_free_events(pmu->events, ct); |
885dcd70 AS |
257 | return -ENOMEM; |
258 | } | |
259 | ||
260 | attr_group->name = "events"; | |
261 | attr_group->attrs = attrs; | |
262 | do { | |
8b4e6dea AS |
263 | ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value); |
264 | dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str); | |
885dcd70 AS |
265 | if (!dev_str) |
266 | continue; | |
267 | ||
268 | attrs[j++] = dev_str; | |
8b4e6dea AS |
269 | if (pmu->events[i].scale) { |
270 | ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name); | |
271 | dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale); | |
885dcd70 AS |
272 | if (!dev_str) |
273 | continue; | |
274 | ||
275 | attrs[j++] = dev_str; | |
276 | } | |
277 | ||
8b4e6dea AS |
278 | if (pmu->events[i].unit) { |
279 | ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name); | |
280 | dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit); | |
885dcd70 AS |
281 | if (!dev_str) |
282 | continue; | |
283 | ||
284 | attrs[j++] = dev_str; | |
285 | } | |
286 | } while (++i < ct); | |
287 | ||
288 | /* Save the event attribute */ | |
289 | pmu->attr_groups[IMC_EVENT_ATTR] = attr_group; | |
290 | ||
885dcd70 AS |
291 | return 0; |
292 | } | |
293 | ||
294 | /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */ | |
295 | static struct imc_pmu_ref *get_nest_pmu_ref(int cpu) | |
296 | { | |
297 | return per_cpu(local_nest_imc_refc, cpu); | |
298 | } | |
299 | ||
300 | static void nest_change_cpu_context(int old_cpu, int new_cpu) | |
301 | { | |
302 | struct imc_pmu **pn = per_nest_pmu_arr; | |
885dcd70 AS |
303 | |
304 | if (old_cpu < 0 || new_cpu < 0) | |
305 | return; | |
306 | ||
73ce9aec | 307 | while (*pn) { |
885dcd70 | 308 | perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu); |
73ce9aec MS |
309 | pn++; |
310 | } | |
885dcd70 AS |
311 | } |
312 | ||
313 | static int ppc_nest_imc_cpu_offline(unsigned int cpu) | |
314 | { | |
315 | int nid, target = -1; | |
316 | const struct cpumask *l_cpumask; | |
317 | struct imc_pmu_ref *ref; | |
318 | ||
319 | /* | |
320 | * Check in the designated list for this cpu. Dont bother | |
321 | * if not one of them. | |
322 | */ | |
323 | if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask)) | |
324 | return 0; | |
325 | ||
ad2b6e01 AS |
326 | /* |
327 | * Check whether nest_imc is registered. We could end up here if the | |
328 | * cpuhotplug callback registration fails. i.e, callback invokes the | |
329 | * offline path for all successfully registered nodes. At this stage, | |
330 | * nest_imc pmu will not be registered and we should return here. | |
331 | * | |
332 | * We return with a zero since this is not an offline failure. And | |
333 | * cpuhp_setup_state() returns the actual failure reason to the caller, | |
334 | * which in turn will call the cleanup routine. | |
335 | */ | |
336 | if (!nest_pmus) | |
337 | return 0; | |
338 | ||
885dcd70 AS |
339 | /* |
340 | * Now that this cpu is one of the designated, | |
341 | * find a next cpu a) which is online and b) in same chip. | |
342 | */ | |
343 | nid = cpu_to_node(cpu); | |
344 | l_cpumask = cpumask_of_node(nid); | |
345 | target = cpumask_any_but(l_cpumask, cpu); | |
346 | ||
347 | /* | |
348 | * Update the cpumask with the target cpu and | |
349 | * migrate the context if needed | |
350 | */ | |
351 | if (target >= 0 && target < nr_cpu_ids) { | |
352 | cpumask_set_cpu(target, &nest_imc_cpumask); | |
353 | nest_change_cpu_context(cpu, target); | |
354 | } else { | |
355 | opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, | |
356 | get_hard_smp_processor_id(cpu)); | |
357 | /* | |
358 | * If this is the last cpu in this chip then, skip the reference | |
359 | * count mutex lock and make the reference count on this chip zero. | |
360 | */ | |
361 | ref = get_nest_pmu_ref(cpu); | |
362 | if (!ref) | |
363 | return -EINVAL; | |
364 | ||
365 | ref->refc = 0; | |
366 | } | |
367 | return 0; | |
368 | } | |
369 | ||
370 | static int ppc_nest_imc_cpu_online(unsigned int cpu) | |
371 | { | |
372 | const struct cpumask *l_cpumask; | |
373 | static struct cpumask tmp_mask; | |
374 | int res; | |
375 | ||
376 | /* Get the cpumask of this node */ | |
377 | l_cpumask = cpumask_of_node(cpu_to_node(cpu)); | |
378 | ||
379 | /* | |
380 | * If this is not the first online CPU on this node, then | |
381 | * just return. | |
382 | */ | |
383 | if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask)) | |
384 | return 0; | |
385 | ||
386 | /* | |
387 | * If this is the first online cpu on this node | |
388 | * disable the nest counters by making an OPAL call. | |
389 | */ | |
390 | res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, | |
391 | get_hard_smp_processor_id(cpu)); | |
392 | if (res) | |
393 | return res; | |
394 | ||
395 | /* Make this CPU the designated target for counter collection */ | |
396 | cpumask_set_cpu(cpu, &nest_imc_cpumask); | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static int nest_pmu_cpumask_init(void) | |
401 | { | |
402 | return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE, | |
403 | "perf/powerpc/imc:online", | |
404 | ppc_nest_imc_cpu_online, | |
405 | ppc_nest_imc_cpu_offline); | |
406 | } | |
407 | ||
408 | static void nest_imc_counters_release(struct perf_event *event) | |
409 | { | |
410 | int rc, node_id; | |
411 | struct imc_pmu_ref *ref; | |
412 | ||
413 | if (event->cpu < 0) | |
414 | return; | |
415 | ||
416 | node_id = cpu_to_node(event->cpu); | |
417 | ||
418 | /* | |
419 | * See if we need to disable the nest PMU. | |
420 | * If no events are currently in use, then we have to take a | |
421 | * mutex to ensure that we don't race with another task doing | |
422 | * enable or disable the nest counters. | |
423 | */ | |
424 | ref = get_nest_pmu_ref(event->cpu); | |
425 | if (!ref) | |
426 | return; | |
427 | ||
428 | /* Take the mutex lock for this node and then decrement the reference count */ | |
429 | mutex_lock(&ref->lock); | |
0d923820 AS |
430 | if (ref->refc == 0) { |
431 | /* | |
432 | * The scenario where this is true is, when perf session is | |
433 | * started, followed by offlining of all cpus in a given node. | |
434 | * | |
435 | * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline() | |
436 | * function set the ref->count to zero, if the cpu which is | |
437 | * about to offline is the last cpu in a given node and make | |
438 | * an OPAL call to disable the engine in that node. | |
439 | * | |
440 | */ | |
441 | mutex_unlock(&ref->lock); | |
442 | return; | |
443 | } | |
885dcd70 AS |
444 | ref->refc--; |
445 | if (ref->refc == 0) { | |
446 | rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, | |
447 | get_hard_smp_processor_id(event->cpu)); | |
448 | if (rc) { | |
711bd207 | 449 | mutex_unlock(&ref->lock); |
885dcd70 AS |
450 | pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id); |
451 | return; | |
452 | } | |
453 | } else if (ref->refc < 0) { | |
454 | WARN(1, "nest-imc: Invalid event reference count\n"); | |
455 | ref->refc = 0; | |
456 | } | |
457 | mutex_unlock(&ref->lock); | |
458 | } | |
459 | ||
460 | static int nest_imc_event_init(struct perf_event *event) | |
461 | { | |
462 | int chip_id, rc, node_id; | |
463 | u32 l_config, config = event->attr.config; | |
464 | struct imc_mem_info *pcni; | |
465 | struct imc_pmu *pmu; | |
466 | struct imc_pmu_ref *ref; | |
467 | bool flag = false; | |
468 | ||
469 | if (event->attr.type != event->pmu->type) | |
470 | return -ENOENT; | |
471 | ||
472 | /* Sampling not supported */ | |
473 | if (event->hw.sample_period) | |
474 | return -EINVAL; | |
475 | ||
885dcd70 AS |
476 | if (event->cpu < 0) |
477 | return -EINVAL; | |
478 | ||
479 | pmu = imc_event_to_pmu(event); | |
480 | ||
481 | /* Sanity check for config (event offset) */ | |
482 | if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size) | |
483 | return -EINVAL; | |
484 | ||
485 | /* | |
486 | * Nest HW counter memory resides in a per-chip reserve-memory (HOMER). | |
487 | * Get the base memory addresss for this cpu. | |
488 | */ | |
f3f1dfd6 | 489 | chip_id = cpu_to_chip_id(event->cpu); |
a913e5e8 AS |
490 | |
491 | /* Return, if chip_id is not valid */ | |
492 | if (chip_id < 0) | |
493 | return -ENODEV; | |
494 | ||
885dcd70 AS |
495 | pcni = pmu->mem_info; |
496 | do { | |
497 | if (pcni->id == chip_id) { | |
498 | flag = true; | |
499 | break; | |
500 | } | |
501 | pcni++; | |
860b7d22 | 502 | } while (pcni->vbase != 0); |
885dcd70 AS |
503 | |
504 | if (!flag) | |
505 | return -ENODEV; | |
506 | ||
507 | /* | |
508 | * Add the event offset to the base address. | |
509 | */ | |
510 | l_config = config & IMC_EVENT_OFFSET_MASK; | |
511 | event->hw.event_base = (u64)pcni->vbase + l_config; | |
512 | node_id = cpu_to_node(event->cpu); | |
513 | ||
514 | /* | |
515 | * Get the imc_pmu_ref struct for this node. | |
516 | * Take the mutex lock and then increment the count of nest pmu events | |
517 | * inited. | |
518 | */ | |
519 | ref = get_nest_pmu_ref(event->cpu); | |
520 | if (!ref) | |
521 | return -EINVAL; | |
522 | ||
523 | mutex_lock(&ref->lock); | |
524 | if (ref->refc == 0) { | |
525 | rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST, | |
526 | get_hard_smp_processor_id(event->cpu)); | |
527 | if (rc) { | |
711bd207 | 528 | mutex_unlock(&ref->lock); |
885dcd70 AS |
529 | pr_err("nest-imc: Unable to start the counters for node %d\n", |
530 | node_id); | |
531 | return rc; | |
532 | } | |
533 | } | |
534 | ++ref->refc; | |
535 | mutex_unlock(&ref->lock); | |
536 | ||
537 | event->destroy = nest_imc_counters_release; | |
538 | return 0; | |
539 | } | |
540 | ||
39a846db AS |
541 | /* |
542 | * core_imc_mem_init : Initializes memory for the current core. | |
543 | * | |
544 | * Uses alloc_pages_node() and uses the returned address as an argument to | |
545 | * an opal call to configure the pdbar. The address sent as an argument is | |
546 | * converted to physical address before the opal call is made. This is the | |
547 | * base address at which the core imc counters are populated. | |
548 | */ | |
549 | static int core_imc_mem_init(int cpu, int size) | |
550 | { | |
f3f1dfd6 | 551 | int nid, rc = 0, core_id = (cpu / threads_per_core); |
39a846db AS |
552 | struct imc_mem_info *mem_info; |
553 | ||
554 | /* | |
555 | * alloc_pages_node() will allocate memory for core in the | |
556 | * local node only. | |
557 | */ | |
f3f1dfd6 | 558 | nid = cpu_to_node(cpu); |
39a846db AS |
559 | mem_info = &core_imc_pmu->mem_info[core_id]; |
560 | mem_info->id = core_id; | |
561 | ||
562 | /* We need only vbase for core counters */ | |
f3f1dfd6 | 563 | mem_info->vbase = page_address(alloc_pages_node(nid, |
cd4f2b30 AS |
564 | GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE | |
565 | __GFP_NOWARN, get_order(size))); | |
39a846db AS |
566 | if (!mem_info->vbase) |
567 | return -ENOMEM; | |
568 | ||
569 | /* Init the mutex */ | |
570 | core_imc_refc[core_id].id = core_id; | |
571 | mutex_init(&core_imc_refc[core_id].lock); | |
572 | ||
573 | rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE, | |
574 | __pa((void *)mem_info->vbase), | |
575 | get_hard_smp_processor_id(cpu)); | |
576 | if (rc) { | |
577 | free_pages((u64)mem_info->vbase, get_order(size)); | |
578 | mem_info->vbase = NULL; | |
579 | } | |
580 | ||
581 | return rc; | |
582 | } | |
583 | ||
584 | static bool is_core_imc_mem_inited(int cpu) | |
585 | { | |
586 | struct imc_mem_info *mem_info; | |
587 | int core_id = (cpu / threads_per_core); | |
588 | ||
589 | mem_info = &core_imc_pmu->mem_info[core_id]; | |
590 | if (!mem_info->vbase) | |
591 | return false; | |
592 | ||
593 | return true; | |
594 | } | |
595 | ||
596 | static int ppc_core_imc_cpu_online(unsigned int cpu) | |
597 | { | |
598 | const struct cpumask *l_cpumask; | |
599 | static struct cpumask tmp_mask; | |
600 | int ret = 0; | |
601 | ||
602 | /* Get the cpumask for this core */ | |
603 | l_cpumask = cpu_sibling_mask(cpu); | |
604 | ||
605 | /* If a cpu for this core is already set, then, don't do anything */ | |
606 | if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask)) | |
607 | return 0; | |
608 | ||
609 | if (!is_core_imc_mem_inited(cpu)) { | |
610 | ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size); | |
611 | if (ret) { | |
612 | pr_info("core_imc memory allocation for cpu %d failed\n", cpu); | |
613 | return ret; | |
614 | } | |
615 | } | |
616 | ||
617 | /* set the cpu in the mask */ | |
618 | cpumask_set_cpu(cpu, &core_imc_cpumask); | |
619 | return 0; | |
620 | } | |
621 | ||
622 | static int ppc_core_imc_cpu_offline(unsigned int cpu) | |
623 | { | |
074db39e AS |
624 | unsigned int core_id; |
625 | int ncpu; | |
39a846db AS |
626 | struct imc_pmu_ref *ref; |
627 | ||
628 | /* | |
629 | * clear this cpu out of the mask, if not present in the mask, | |
630 | * don't bother doing anything. | |
631 | */ | |
632 | if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask)) | |
633 | return 0; | |
634 | ||
7ecb37f6 MS |
635 | /* |
636 | * Check whether core_imc is registered. We could end up here | |
637 | * if the cpuhotplug callback registration fails. i.e, callback | |
638 | * invokes the offline path for all sucessfully registered cpus. | |
639 | * At this stage, core_imc pmu will not be registered and we | |
640 | * should return here. | |
641 | * | |
642 | * We return with a zero since this is not an offline failure. | |
643 | * And cpuhp_setup_state() returns the actual failure reason | |
644 | * to the caller, which inturn will call the cleanup routine. | |
645 | */ | |
646 | if (!core_imc_pmu->pmu.event_init) | |
647 | return 0; | |
648 | ||
39a846db AS |
649 | /* Find any online cpu in that core except the current "cpu" */ |
650 | ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu); | |
651 | ||
652 | if (ncpu >= 0 && ncpu < nr_cpu_ids) { | |
653 | cpumask_set_cpu(ncpu, &core_imc_cpumask); | |
654 | perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu); | |
655 | } else { | |
656 | /* | |
657 | * If this is the last cpu in this core then, skip taking refernce | |
658 | * count mutex lock for this core and directly zero "refc" for | |
659 | * this core. | |
660 | */ | |
661 | opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, | |
662 | get_hard_smp_processor_id(cpu)); | |
663 | core_id = cpu / threads_per_core; | |
664 | ref = &core_imc_refc[core_id]; | |
665 | if (!ref) | |
666 | return -EINVAL; | |
667 | ||
668 | ref->refc = 0; | |
669 | } | |
670 | return 0; | |
671 | } | |
672 | ||
673 | static int core_imc_pmu_cpumask_init(void) | |
674 | { | |
675 | return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE, | |
676 | "perf/powerpc/imc_core:online", | |
677 | ppc_core_imc_cpu_online, | |
678 | ppc_core_imc_cpu_offline); | |
679 | } | |
680 | ||
681 | static void core_imc_counters_release(struct perf_event *event) | |
682 | { | |
683 | int rc, core_id; | |
684 | struct imc_pmu_ref *ref; | |
685 | ||
686 | if (event->cpu < 0) | |
687 | return; | |
688 | /* | |
689 | * See if we need to disable the IMC PMU. | |
690 | * If no events are currently in use, then we have to take a | |
691 | * mutex to ensure that we don't race with another task doing | |
692 | * enable or disable the core counters. | |
693 | */ | |
694 | core_id = event->cpu / threads_per_core; | |
695 | ||
696 | /* Take the mutex lock and decrement the refernce count for this core */ | |
697 | ref = &core_imc_refc[core_id]; | |
698 | if (!ref) | |
699 | return; | |
700 | ||
701 | mutex_lock(&ref->lock); | |
0d923820 AS |
702 | if (ref->refc == 0) { |
703 | /* | |
704 | * The scenario where this is true is, when perf session is | |
705 | * started, followed by offlining of all cpus in a given core. | |
706 | * | |
707 | * In the cpuhotplug offline path, ppc_core_imc_cpu_offline() | |
708 | * function set the ref->count to zero, if the cpu which is | |
709 | * about to offline is the last cpu in a given core and make | |
710 | * an OPAL call to disable the engine in that core. | |
711 | * | |
712 | */ | |
713 | mutex_unlock(&ref->lock); | |
714 | return; | |
715 | } | |
39a846db AS |
716 | ref->refc--; |
717 | if (ref->refc == 0) { | |
718 | rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, | |
719 | get_hard_smp_processor_id(event->cpu)); | |
720 | if (rc) { | |
721 | mutex_unlock(&ref->lock); | |
722 | pr_err("IMC: Unable to stop the counters for core %d\n", core_id); | |
723 | return; | |
724 | } | |
725 | } else if (ref->refc < 0) { | |
726 | WARN(1, "core-imc: Invalid event reference count\n"); | |
727 | ref->refc = 0; | |
728 | } | |
729 | mutex_unlock(&ref->lock); | |
730 | } | |
731 | ||
732 | static int core_imc_event_init(struct perf_event *event) | |
733 | { | |
734 | int core_id, rc; | |
735 | u64 config = event->attr.config; | |
736 | struct imc_mem_info *pcmi; | |
737 | struct imc_pmu *pmu; | |
738 | struct imc_pmu_ref *ref; | |
739 | ||
740 | if (event->attr.type != event->pmu->type) | |
741 | return -ENOENT; | |
742 | ||
743 | /* Sampling not supported */ | |
744 | if (event->hw.sample_period) | |
745 | return -EINVAL; | |
746 | ||
39a846db AS |
747 | if (event->cpu < 0) |
748 | return -EINVAL; | |
749 | ||
750 | event->hw.idx = -1; | |
751 | pmu = imc_event_to_pmu(event); | |
752 | ||
753 | /* Sanity check for config (event offset) */ | |
754 | if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)) | |
755 | return -EINVAL; | |
756 | ||
757 | if (!is_core_imc_mem_inited(event->cpu)) | |
758 | return -ENODEV; | |
759 | ||
760 | core_id = event->cpu / threads_per_core; | |
761 | pcmi = &core_imc_pmu->mem_info[core_id]; | |
762 | if ((!pcmi->vbase)) | |
763 | return -ENODEV; | |
764 | ||
765 | /* Get the core_imc mutex for this core */ | |
766 | ref = &core_imc_refc[core_id]; | |
767 | if (!ref) | |
768 | return -EINVAL; | |
769 | ||
770 | /* | |
771 | * Core pmu units are enabled only when it is used. | |
772 | * See if this is triggered for the first time. | |
773 | * If yes, take the mutex lock and enable the core counters. | |
774 | * If not, just increment the count in core_imc_refc struct. | |
775 | */ | |
776 | mutex_lock(&ref->lock); | |
777 | if (ref->refc == 0) { | |
778 | rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE, | |
779 | get_hard_smp_processor_id(event->cpu)); | |
780 | if (rc) { | |
781 | mutex_unlock(&ref->lock); | |
782 | pr_err("core-imc: Unable to start the counters for core %d\n", | |
783 | core_id); | |
784 | return rc; | |
785 | } | |
786 | } | |
787 | ++ref->refc; | |
788 | mutex_unlock(&ref->lock); | |
789 | ||
790 | event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK); | |
791 | event->destroy = core_imc_counters_release; | |
792 | return 0; | |
793 | } | |
794 | ||
f74c89bd | 795 | /* |
dd50cf7c AS |
796 | * Allocates a page of memory for each of the online cpus, and load |
797 | * LDBAR with 0. | |
798 | * The physical base address of the page allocated for a cpu will be | |
799 | * written to the LDBAR for that cpu, when the thread-imc event | |
800 | * is added. | |
f74c89bd AS |
801 | * |
802 | * LDBAR Register Layout: | |
803 | * | |
804 | * 0 4 8 12 16 20 24 28 | |
805 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | | |
806 | * | | [ ] [ Counter Address [8:50] | |
807 | * | * Mode | | |
808 | * | * PB Scope | |
809 | * * Enable/Disable | |
810 | * | |
811 | * 32 36 40 44 48 52 56 60 | |
812 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | | |
813 | * Counter Address [8:50] ] | |
814 | * | |
815 | */ | |
816 | static int thread_imc_mem_alloc(int cpu_id, int size) | |
817 | { | |
dd50cf7c | 818 | u64 *local_mem = per_cpu(thread_imc_mem, cpu_id); |
f3f1dfd6 | 819 | int nid = cpu_to_node(cpu_id); |
f74c89bd AS |
820 | |
821 | if (!local_mem) { | |
822 | /* | |
823 | * This case could happen only once at start, since we dont | |
824 | * free the memory in cpu offline path. | |
825 | */ | |
f3f1dfd6 | 826 | local_mem = page_address(alloc_pages_node(nid, |
cd4f2b30 AS |
827 | GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE | |
828 | __GFP_NOWARN, get_order(size))); | |
f74c89bd AS |
829 | if (!local_mem) |
830 | return -ENOMEM; | |
831 | ||
832 | per_cpu(thread_imc_mem, cpu_id) = local_mem; | |
833 | } | |
834 | ||
dd50cf7c | 835 | mtspr(SPRN_LDBAR, 0); |
f74c89bd AS |
836 | return 0; |
837 | } | |
838 | ||
839 | static int ppc_thread_imc_cpu_online(unsigned int cpu) | |
885dcd70 | 840 | { |
f74c89bd AS |
841 | return thread_imc_mem_alloc(cpu, thread_imc_mem_size); |
842 | } | |
843 | ||
844 | static int ppc_thread_imc_cpu_offline(unsigned int cpu) | |
845 | { | |
846 | mtspr(SPRN_LDBAR, 0); | |
847 | return 0; | |
848 | } | |
849 | ||
850 | static int thread_imc_cpu_init(void) | |
851 | { | |
852 | return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE, | |
853 | "perf/powerpc/imc_thread:online", | |
854 | ppc_thread_imc_cpu_online, | |
855 | ppc_thread_imc_cpu_offline); | |
856 | } | |
857 | ||
f74c89bd AS |
858 | static int thread_imc_event_init(struct perf_event *event) |
859 | { | |
860 | u32 config = event->attr.config; | |
861 | struct task_struct *target; | |
862 | struct imc_pmu *pmu; | |
863 | ||
864 | if (event->attr.type != event->pmu->type) | |
865 | return -ENOENT; | |
866 | ||
216c3087 MS |
867 | if (!capable(CAP_SYS_ADMIN)) |
868 | return -EACCES; | |
869 | ||
f74c89bd AS |
870 | /* Sampling not supported */ |
871 | if (event->hw.sample_period) | |
872 | return -EINVAL; | |
873 | ||
874 | event->hw.idx = -1; | |
875 | pmu = imc_event_to_pmu(event); | |
876 | ||
877 | /* Sanity check for config offset */ | |
878 | if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)) | |
879 | return -EINVAL; | |
880 | ||
881 | target = event->hw.target; | |
882 | if (!target) | |
883 | return -EINVAL; | |
884 | ||
885 | event->pmu->task_ctx_nr = perf_sw_context; | |
886 | return 0; | |
887 | } | |
888 | ||
889 | static bool is_thread_imc_pmu(struct perf_event *event) | |
890 | { | |
891 | if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc"))) | |
892 | return true; | |
893 | ||
894 | return false; | |
895 | } | |
896 | ||
897 | static u64 * get_event_base_addr(struct perf_event *event) | |
898 | { | |
899 | u64 addr; | |
900 | ||
901 | if (is_thread_imc_pmu(event)) { | |
902 | addr = (u64)per_cpu(thread_imc_mem, smp_processor_id()); | |
903 | return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK)); | |
904 | } | |
905 | ||
885dcd70 AS |
906 | return (u64 *)event->hw.event_base; |
907 | } | |
908 | ||
f74c89bd AS |
909 | static void thread_imc_pmu_start_txn(struct pmu *pmu, |
910 | unsigned int txn_flags) | |
911 | { | |
912 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
913 | return; | |
914 | perf_pmu_disable(pmu); | |
915 | } | |
916 | ||
917 | static void thread_imc_pmu_cancel_txn(struct pmu *pmu) | |
918 | { | |
919 | perf_pmu_enable(pmu); | |
920 | } | |
921 | ||
922 | static int thread_imc_pmu_commit_txn(struct pmu *pmu) | |
923 | { | |
924 | perf_pmu_enable(pmu); | |
925 | return 0; | |
926 | } | |
927 | ||
885dcd70 AS |
928 | static u64 imc_read_counter(struct perf_event *event) |
929 | { | |
930 | u64 *addr, data; | |
931 | ||
932 | /* | |
933 | * In-Memory Collection (IMC) counters are free flowing counters. | |
934 | * So we take a snapshot of the counter value on enable and save it | |
935 | * to calculate the delta at later stage to present the event counter | |
936 | * value. | |
937 | */ | |
938 | addr = get_event_base_addr(event); | |
939 | data = be64_to_cpu(READ_ONCE(*addr)); | |
940 | local64_set(&event->hw.prev_count, data); | |
941 | ||
942 | return data; | |
943 | } | |
944 | ||
945 | static void imc_event_update(struct perf_event *event) | |
946 | { | |
947 | u64 counter_prev, counter_new, final_count; | |
948 | ||
949 | counter_prev = local64_read(&event->hw.prev_count); | |
950 | counter_new = imc_read_counter(event); | |
951 | final_count = counter_new - counter_prev; | |
952 | ||
953 | /* Update the delta to the event count */ | |
954 | local64_add(final_count, &event->count); | |
955 | } | |
956 | ||
957 | static void imc_event_start(struct perf_event *event, int flags) | |
958 | { | |
959 | /* | |
960 | * In Memory Counters are free flowing counters. HW or the microcode | |
961 | * keeps adding to the counter offset in memory. To get event | |
962 | * counter value, we snapshot the value here and we calculate | |
963 | * delta at later point. | |
964 | */ | |
965 | imc_read_counter(event); | |
966 | } | |
967 | ||
968 | static void imc_event_stop(struct perf_event *event, int flags) | |
969 | { | |
970 | /* | |
971 | * Take a snapshot and calculate the delta and update | |
972 | * the event counter values. | |
973 | */ | |
974 | imc_event_update(event); | |
975 | } | |
976 | ||
977 | static int imc_event_add(struct perf_event *event, int flags) | |
978 | { | |
979 | if (flags & PERF_EF_START) | |
980 | imc_event_start(event, flags); | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
f74c89bd AS |
985 | static int thread_imc_event_add(struct perf_event *event, int flags) |
986 | { | |
7ccc4fe5 AS |
987 | int core_id; |
988 | struct imc_pmu_ref *ref; | |
dd50cf7c | 989 | u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id()); |
7ccc4fe5 | 990 | |
f74c89bd AS |
991 | if (flags & PERF_EF_START) |
992 | imc_event_start(event, flags); | |
993 | ||
7ccc4fe5 AS |
994 | if (!is_core_imc_mem_inited(smp_processor_id())) |
995 | return -EINVAL; | |
996 | ||
997 | core_id = smp_processor_id() / threads_per_core; | |
dd50cf7c AS |
998 | ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE; |
999 | mtspr(SPRN_LDBAR, ldbar_value); | |
1000 | ||
7ccc4fe5 AS |
1001 | /* |
1002 | * imc pmus are enabled only when it is used. | |
1003 | * See if this is triggered for the first time. | |
1004 | * If yes, take the mutex lock and enable the counters. | |
1005 | * If not, just increment the count in ref count struct. | |
1006 | */ | |
1007 | ref = &core_imc_refc[core_id]; | |
1008 | if (!ref) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | mutex_lock(&ref->lock); | |
1012 | if (ref->refc == 0) { | |
1013 | if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE, | |
1014 | get_hard_smp_processor_id(smp_processor_id()))) { | |
1015 | mutex_unlock(&ref->lock); | |
1016 | pr_err("thread-imc: Unable to start the counter\ | |
1017 | for core %d\n", core_id); | |
1018 | return -EINVAL; | |
1019 | } | |
1020 | } | |
1021 | ++ref->refc; | |
1022 | mutex_unlock(&ref->lock); | |
f74c89bd AS |
1023 | return 0; |
1024 | } | |
1025 | ||
1026 | static void thread_imc_event_del(struct perf_event *event, int flags) | |
1027 | { | |
7ccc4fe5 AS |
1028 | |
1029 | int core_id; | |
1030 | struct imc_pmu_ref *ref; | |
1031 | ||
dd50cf7c | 1032 | mtspr(SPRN_LDBAR, 0); |
7ccc4fe5 AS |
1033 | |
1034 | core_id = smp_processor_id() / threads_per_core; | |
1035 | ref = &core_imc_refc[core_id]; | |
1036 | ||
1037 | mutex_lock(&ref->lock); | |
1038 | ref->refc--; | |
1039 | if (ref->refc == 0) { | |
1040 | if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, | |
1041 | get_hard_smp_processor_id(smp_processor_id()))) { | |
1042 | mutex_unlock(&ref->lock); | |
1043 | pr_err("thread-imc: Unable to stop the counters\ | |
1044 | for core %d\n", core_id); | |
1045 | return; | |
1046 | } | |
1047 | } else if (ref->refc < 0) { | |
1048 | ref->refc = 0; | |
1049 | } | |
1050 | mutex_unlock(&ref->lock); | |
dd50cf7c AS |
1051 | /* |
1052 | * Take a snapshot and calculate the delta and update | |
1053 | * the event counter values. | |
1054 | */ | |
1055 | imc_event_update(event); | |
f74c89bd AS |
1056 | } |
1057 | ||
885dcd70 AS |
1058 | /* update_pmu_ops : Populate the appropriate operations for "pmu" */ |
1059 | static int update_pmu_ops(struct imc_pmu *pmu) | |
1060 | { | |
1061 | pmu->pmu.task_ctx_nr = perf_invalid_context; | |
1062 | pmu->pmu.add = imc_event_add; | |
1063 | pmu->pmu.del = imc_event_stop; | |
1064 | pmu->pmu.start = imc_event_start; | |
1065 | pmu->pmu.stop = imc_event_stop; | |
1066 | pmu->pmu.read = imc_event_update; | |
1067 | pmu->pmu.attr_groups = pmu->attr_groups; | |
c2c9091d | 1068 | pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE; |
885dcd70 AS |
1069 | pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group; |
1070 | ||
885dcd70 AS |
1071 | switch (pmu->domain) { |
1072 | case IMC_DOMAIN_NEST: | |
1073 | pmu->pmu.event_init = nest_imc_event_init; | |
1074 | pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group; | |
1075 | break; | |
39a846db AS |
1076 | case IMC_DOMAIN_CORE: |
1077 | pmu->pmu.event_init = core_imc_event_init; | |
1078 | pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group; | |
1079 | break; | |
f74c89bd AS |
1080 | case IMC_DOMAIN_THREAD: |
1081 | pmu->pmu.event_init = thread_imc_event_init; | |
f74c89bd AS |
1082 | pmu->pmu.add = thread_imc_event_add; |
1083 | pmu->pmu.del = thread_imc_event_del; | |
1084 | pmu->pmu.start_txn = thread_imc_pmu_start_txn; | |
1085 | pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn; | |
1086 | pmu->pmu.commit_txn = thread_imc_pmu_commit_txn; | |
1087 | break; | |
885dcd70 AS |
1088 | default: |
1089 | break; | |
1090 | } | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */ | |
1096 | static int init_nest_pmu_ref(void) | |
1097 | { | |
1098 | int nid, i, cpu; | |
1099 | ||
1100 | nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc), | |
1101 | GFP_KERNEL); | |
1102 | ||
1103 | if (!nest_imc_refc) | |
1104 | return -ENOMEM; | |
1105 | ||
1106 | i = 0; | |
1107 | for_each_node(nid) { | |
1108 | /* | |
1109 | * Mutex lock to avoid races while tracking the number of | |
1110 | * sessions using the chip's nest pmu units. | |
1111 | */ | |
1112 | mutex_init(&nest_imc_refc[i].lock); | |
1113 | ||
1114 | /* | |
1115 | * Loop to init the "id" with the node_id. Variable "i" initialized to | |
1116 | * 0 and will be used as index to the array. "i" will not go off the | |
1117 | * end of the array since the "for_each_node" loops for "N_POSSIBLE" | |
1118 | * nodes only. | |
1119 | */ | |
1120 | nest_imc_refc[i++].id = nid; | |
1121 | } | |
1122 | ||
1123 | /* | |
1124 | * Loop to init the per_cpu "local_nest_imc_refc" with the proper | |
1125 | * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple. | |
1126 | */ | |
1127 | for_each_possible_cpu(cpu) { | |
1128 | nid = cpu_to_node(cpu); | |
7efbae90 | 1129 | for (i = 0; i < num_possible_nodes(); i++) { |
885dcd70 AS |
1130 | if (nest_imc_refc[i].id == nid) { |
1131 | per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i]; | |
1132 | break; | |
1133 | } | |
1134 | } | |
1135 | } | |
1136 | return 0; | |
1137 | } | |
1138 | ||
39a846db AS |
1139 | static void cleanup_all_core_imc_memory(void) |
1140 | { | |
d2032678 | 1141 | int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core); |
39a846db AS |
1142 | struct imc_mem_info *ptr = core_imc_pmu->mem_info; |
1143 | int size = core_imc_pmu->counter_mem_size; | |
1144 | ||
1145 | /* mem_info will never be NULL */ | |
1146 | for (i = 0; i < nr_cores; i++) { | |
1147 | if (ptr[i].vbase) | |
cb094fa5 | 1148 | free_pages((u64)ptr[i].vbase, get_order(size)); |
39a846db AS |
1149 | } |
1150 | ||
1151 | kfree(ptr); | |
1152 | kfree(core_imc_refc); | |
1153 | } | |
1154 | ||
f74c89bd AS |
1155 | static void thread_imc_ldbar_disable(void *dummy) |
1156 | { | |
1157 | /* | |
1158 | * By Zeroing LDBAR, we disable thread-imc | |
1159 | * updates. | |
1160 | */ | |
1161 | mtspr(SPRN_LDBAR, 0); | |
1162 | } | |
1163 | ||
1164 | void thread_imc_disable(void) | |
1165 | { | |
1166 | on_each_cpu(thread_imc_ldbar_disable, NULL, 1); | |
1167 | } | |
1168 | ||
1169 | static void cleanup_all_thread_imc_memory(void) | |
1170 | { | |
1171 | int i, order = get_order(thread_imc_mem_size); | |
1172 | ||
1173 | for_each_online_cpu(i) { | |
1174 | if (per_cpu(thread_imc_mem, i)) | |
1175 | free_pages((u64)per_cpu(thread_imc_mem, i), order); | |
1176 | ||
1177 | } | |
1178 | } | |
1179 | ||
ed8e443f AS |
1180 | /* Function to free the attr_groups which are dynamically allocated */ |
1181 | static void imc_common_mem_free(struct imc_pmu *pmu_ptr) | |
1182 | { | |
1183 | if (pmu_ptr->attr_groups[IMC_EVENT_ATTR]) | |
1184 | kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs); | |
1185 | kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]); | |
ed8e443f AS |
1186 | } |
1187 | ||
885dcd70 AS |
1188 | /* |
1189 | * Common function to unregister cpu hotplug callback and | |
1190 | * free the memory. | |
1191 | * TODO: Need to handle pmu unregistering, which will be | |
1192 | * done in followup series. | |
1193 | */ | |
1194 | static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr) | |
1195 | { | |
1196 | if (pmu_ptr->domain == IMC_DOMAIN_NEST) { | |
b3376dcc | 1197 | mutex_lock(&nest_init_lock); |
885dcd70 AS |
1198 | if (nest_pmus == 1) { |
1199 | cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE); | |
1200 | kfree(nest_imc_refc); | |
110df8bd | 1201 | kfree(per_nest_pmu_arr); |
cb094fa5 | 1202 | per_nest_pmu_arr = NULL; |
885dcd70 AS |
1203 | } |
1204 | ||
1205 | if (nest_pmus > 0) | |
1206 | nest_pmus--; | |
1207 | mutex_unlock(&nest_init_lock); | |
1208 | } | |
1209 | ||
39a846db AS |
1210 | /* Free core_imc memory */ |
1211 | if (pmu_ptr->domain == IMC_DOMAIN_CORE) { | |
1212 | cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE); | |
1213 | cleanup_all_core_imc_memory(); | |
1214 | } | |
1215 | ||
f74c89bd AS |
1216 | /* Free thread_imc memory */ |
1217 | if (pmu_ptr->domain == IMC_DOMAIN_THREAD) { | |
1218 | cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE); | |
1219 | cleanup_all_thread_imc_memory(); | |
1220 | } | |
885dcd70 AS |
1221 | } |
1222 | ||
25af86b2 AS |
1223 | /* |
1224 | * Function to unregister thread-imc if core-imc | |
1225 | * is not registered. | |
1226 | */ | |
1227 | void unregister_thread_imc(void) | |
1228 | { | |
1229 | imc_common_cpuhp_mem_free(thread_imc_pmu); | |
1230 | imc_common_mem_free(thread_imc_pmu); | |
1231 | perf_pmu_unregister(&thread_imc_pmu->pmu); | |
1232 | } | |
885dcd70 AS |
1233 | |
1234 | /* | |
1235 | * imc_mem_init : Function to support memory allocation for core imc. | |
1236 | */ | |
1237 | static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent, | |
1238 | int pmu_index) | |
1239 | { | |
1240 | const char *s; | |
b41bb28b | 1241 | int nr_cores, cpu, res = -ENOMEM; |
885dcd70 AS |
1242 | |
1243 | if (of_property_read_string(parent, "name", &s)) | |
1244 | return -ENODEV; | |
1245 | ||
885dcd70 AS |
1246 | switch (pmu_ptr->domain) { |
1247 | case IMC_DOMAIN_NEST: | |
1248 | /* Update the pmu name */ | |
1249 | pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s); | |
1250 | if (!pmu_ptr->pmu.name) | |
b41bb28b | 1251 | goto err; |
885dcd70 AS |
1252 | |
1253 | /* Needed for hotplug/migration */ | |
73ce9aec MS |
1254 | if (!per_nest_pmu_arr) { |
1255 | per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1, | |
1256 | sizeof(struct imc_pmu *), | |
1257 | GFP_KERNEL); | |
1258 | if (!per_nest_pmu_arr) | |
b41bb28b | 1259 | goto err; |
73ce9aec | 1260 | } |
885dcd70 AS |
1261 | per_nest_pmu_arr[pmu_index] = pmu_ptr; |
1262 | break; | |
39a846db AS |
1263 | case IMC_DOMAIN_CORE: |
1264 | /* Update the pmu name */ | |
1265 | pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc"); | |
1266 | if (!pmu_ptr->pmu.name) | |
b41bb28b | 1267 | goto err; |
39a846db | 1268 | |
d2032678 | 1269 | nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core); |
39a846db AS |
1270 | pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info), |
1271 | GFP_KERNEL); | |
1272 | ||
1273 | if (!pmu_ptr->mem_info) | |
b41bb28b | 1274 | goto err; |
39a846db AS |
1275 | |
1276 | core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref), | |
1277 | GFP_KERNEL); | |
1278 | ||
ed8e443f AS |
1279 | if (!core_imc_refc) { |
1280 | kfree(pmu_ptr->mem_info); | |
b41bb28b | 1281 | goto err; |
ed8e443f | 1282 | } |
39a846db AS |
1283 | |
1284 | core_imc_pmu = pmu_ptr; | |
1285 | break; | |
f74c89bd AS |
1286 | case IMC_DOMAIN_THREAD: |
1287 | /* Update the pmu name */ | |
1288 | pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc"); | |
1289 | if (!pmu_ptr->pmu.name) | |
b41bb28b | 1290 | goto err; |
f74c89bd AS |
1291 | |
1292 | thread_imc_mem_size = pmu_ptr->counter_mem_size; | |
1293 | for_each_online_cpu(cpu) { | |
1294 | res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size); | |
ed8e443f AS |
1295 | if (res) { |
1296 | cleanup_all_thread_imc_memory(); | |
b41bb28b | 1297 | goto err; |
ed8e443f | 1298 | } |
f74c89bd AS |
1299 | } |
1300 | ||
25af86b2 | 1301 | thread_imc_pmu = pmu_ptr; |
f74c89bd | 1302 | break; |
885dcd70 AS |
1303 | default: |
1304 | return -EINVAL; | |
1305 | } | |
1306 | ||
1307 | return 0; | |
b41bb28b AS |
1308 | err: |
1309 | return res; | |
885dcd70 AS |
1310 | } |
1311 | ||
1312 | /* | |
1313 | * init_imc_pmu : Setup and register the IMC pmu device. | |
1314 | * | |
1315 | * @parent: Device tree unit node | |
1316 | * @pmu_ptr: memory allocated for this pmu | |
1317 | * @pmu_idx: Count of nest pmc registered | |
1318 | * | |
1319 | * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback. | |
1320 | * Handles failure cases and accordingly frees memory. | |
1321 | */ | |
1322 | int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx) | |
1323 | { | |
1324 | int ret; | |
1325 | ||
1326 | ret = imc_mem_init(pmu_ptr, parent, pmu_idx); | |
cb094fa5 AS |
1327 | if (ret) |
1328 | goto err_free_mem; | |
885dcd70 | 1329 | |
885dcd70 AS |
1330 | switch (pmu_ptr->domain) { |
1331 | case IMC_DOMAIN_NEST: | |
1332 | /* | |
1333 | * Nest imc pmu need only one cpu per chip, we initialize the | |
1334 | * cpumask for the first nest imc pmu and use the same for the | |
1335 | * rest. To handle the cpuhotplug callback unregister, we track | |
1336 | * the number of nest pmus in "nest_pmus". | |
1337 | */ | |
1338 | mutex_lock(&nest_init_lock); | |
1339 | if (nest_pmus == 0) { | |
1340 | ret = init_nest_pmu_ref(); | |
1341 | if (ret) { | |
1342 | mutex_unlock(&nest_init_lock); | |
cb094fa5 AS |
1343 | kfree(per_nest_pmu_arr); |
1344 | per_nest_pmu_arr = NULL; | |
1345 | goto err_free_mem; | |
885dcd70 AS |
1346 | } |
1347 | /* Register for cpu hotplug notification. */ | |
1348 | ret = nest_pmu_cpumask_init(); | |
1349 | if (ret) { | |
1350 | mutex_unlock(&nest_init_lock); | |
110df8bd AS |
1351 | kfree(nest_imc_refc); |
1352 | kfree(per_nest_pmu_arr); | |
cb094fa5 AS |
1353 | per_nest_pmu_arr = NULL; |
1354 | goto err_free_mem; | |
885dcd70 AS |
1355 | } |
1356 | } | |
1357 | nest_pmus++; | |
1358 | mutex_unlock(&nest_init_lock); | |
39a846db AS |
1359 | break; |
1360 | case IMC_DOMAIN_CORE: | |
1361 | ret = core_imc_pmu_cpumask_init(); | |
1362 | if (ret) { | |
1363 | cleanup_all_core_imc_memory(); | |
cb094fa5 | 1364 | goto err_free_mem; |
39a846db AS |
1365 | } |
1366 | ||
f74c89bd AS |
1367 | break; |
1368 | case IMC_DOMAIN_THREAD: | |
1369 | ret = thread_imc_cpu_init(); | |
1370 | if (ret) { | |
1371 | cleanup_all_thread_imc_memory(); | |
cb094fa5 | 1372 | goto err_free_mem; |
f74c89bd AS |
1373 | } |
1374 | ||
885dcd70 AS |
1375 | break; |
1376 | default: | |
e7a8ac43 | 1377 | return -EINVAL; /* Unknown domain */ |
885dcd70 AS |
1378 | } |
1379 | ||
1380 | ret = update_events_in_group(parent, pmu_ptr); | |
1381 | if (ret) | |
cb094fa5 | 1382 | goto err_free_cpuhp_mem; |
885dcd70 AS |
1383 | |
1384 | ret = update_pmu_ops(pmu_ptr); | |
1385 | if (ret) | |
cb094fa5 | 1386 | goto err_free_cpuhp_mem; |
885dcd70 AS |
1387 | |
1388 | ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1); | |
1389 | if (ret) | |
cb094fa5 | 1390 | goto err_free_cpuhp_mem; |
885dcd70 | 1391 | |
6233b6da | 1392 | pr_debug("%s performance monitor hardware support registered\n", |
885dcd70 AS |
1393 | pmu_ptr->pmu.name); |
1394 | ||
1395 | return 0; | |
1396 | ||
cb094fa5 | 1397 | err_free_cpuhp_mem: |
885dcd70 | 1398 | imc_common_cpuhp_mem_free(pmu_ptr); |
cb094fa5 AS |
1399 | err_free_mem: |
1400 | imc_common_mem_free(pmu_ptr); | |
885dcd70 AS |
1401 | return ret; |
1402 | } |