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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
16 | #include <asm/reg.h> | |
17 | #include <asm/pmc.h> | |
01d0287f | 18 | #include <asm/machdep.h> |
0475f9ea | 19 | #include <asm/firmware.h> |
0bbd0d4b | 20 | #include <asm/ptrace.h> |
4574910e | 21 | |
3925f46b AK |
22 | #define BHRB_MAX_ENTRIES 32 |
23 | #define BHRB_TARGET 0x0000000000000002 | |
24 | #define BHRB_PREDICTION 0x0000000000000001 | |
25 | #define BHRB_EA 0xFFFFFFFFFFFFFFFC | |
26 | ||
cdd6c482 IM |
27 | struct cpu_hw_events { |
28 | int n_events; | |
4574910e PM |
29 | int n_percpu; |
30 | int disabled; | |
31 | int n_added; | |
ab7ef2e5 PM |
32 | int n_limited; |
33 | u8 pmcs_enabled; | |
cdd6c482 IM |
34 | struct perf_event *event[MAX_HWEVENTS]; |
35 | u64 events[MAX_HWEVENTS]; | |
36 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 37 | unsigned long mmcr[3]; |
a8f90e90 PM |
38 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
39 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
40 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
41 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
42 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
43 | |
44 | unsigned int group_flag; | |
45 | int n_txn_start; | |
3925f46b AK |
46 | |
47 | /* BHRB bits */ | |
48 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
49 | int bhrb_users; | |
50 | void *bhrb_context; | |
51 | struct perf_branch_stack bhrb_stack; | |
52 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 53 | }; |
3925f46b | 54 | |
cdd6c482 | 55 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
56 | |
57 | struct power_pmu *ppmu; | |
58 | ||
d095cd46 | 59 | /* |
57c0c15b | 60 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
61 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
62 | * hypervisor bit set in the MSR, or if we are running on a processor | |
63 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
64 | * then we need to use the FCHV bit to ignore kernel events. | |
65 | */ | |
cdd6c482 | 66 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 67 | |
98fb1807 PM |
68 | /* |
69 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
70 | * and a few other names are different. | |
71 | */ | |
72 | #ifdef CONFIG_PPC32 | |
73 | ||
74 | #define MMCR0_FCHV 0 | |
75 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
76 | ||
77 | #define SPRN_MMCRA SPRN_MMCR2 | |
78 | #define MMCRA_SAMPLE_ENABLE 0 | |
79 | ||
80 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
81 | { | |
82 | return 0; | |
83 | } | |
98fb1807 PM |
84 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
85 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
86 | { | |
87 | return 0; | |
88 | } | |
75382aa7 AB |
89 | static inline void perf_read_regs(struct pt_regs *regs) |
90 | { | |
91 | regs->result = 0; | |
92 | } | |
98fb1807 PM |
93 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
94 | { | |
95 | return 0; | |
96 | } | |
97 | ||
e6878835 | 98 | static inline int siar_valid(struct pt_regs *regs) |
99 | { | |
100 | return 1; | |
101 | } | |
102 | ||
98fb1807 PM |
103 | #endif /* CONFIG_PPC32 */ |
104 | ||
33904054 ME |
105 | static bool regs_use_siar(struct pt_regs *regs) |
106 | { | |
107 | return !!(regs->result & 1); | |
108 | } | |
109 | ||
98fb1807 PM |
110 | /* |
111 | * Things that are specific to 64-bit implementations. | |
112 | */ | |
113 | #ifdef CONFIG_PPC64 | |
114 | ||
115 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
116 | { | |
117 | unsigned long mmcra = regs->dsisr; | |
118 | ||
7a786832 | 119 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
120 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
121 | if (slot > 1) | |
122 | return 4 * (slot - 1); | |
123 | } | |
7a786832 | 124 | |
98fb1807 PM |
125 | return 0; |
126 | } | |
127 | ||
98fb1807 PM |
128 | /* |
129 | * The user wants a data address recorded. | |
130 | * If we're not doing instruction sampling, give them the SDAR | |
131 | * (sampled data address). If we are doing instruction sampling, then | |
132 | * only give them the SDAR if it corresponds to the instruction | |
e6878835 | 133 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or |
134 | * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA. | |
98fb1807 PM |
135 | */ |
136 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
137 | { | |
138 | unsigned long mmcra = regs->dsisr; | |
e6878835 | 139 | unsigned long sdsync; |
140 | ||
141 | if (ppmu->flags & PPMU_SIAR_VALID) | |
142 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
143 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
144 | sdsync = POWER6_MMCRA_SDSYNC; | |
145 | else | |
146 | sdsync = MMCRA_SDSYNC; | |
98fb1807 PM |
147 | |
148 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | |
149 | *addrp = mfspr(SPRN_SDAR); | |
150 | } | |
151 | ||
5682c460 | 152 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
153 | { |
154 | unsigned long sihv = MMCRA_SIHV; | |
155 | ||
8f61aa32 ME |
156 | if (ppmu->flags & PPMU_HAS_SIER) |
157 | return !!(regs->dar & SIER_SIHV); | |
158 | ||
68b30bb9 AB |
159 | if (ppmu->flags & PPMU_ALT_SIPR) |
160 | sihv = POWER6_MMCRA_SIHV; | |
161 | ||
5682c460 | 162 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
163 | } |
164 | ||
5682c460 | 165 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
166 | { |
167 | unsigned long sipr = MMCRA_SIPR; | |
168 | ||
8f61aa32 ME |
169 | if (ppmu->flags & PPMU_HAS_SIER) |
170 | return !!(regs->dar & SIER_SIPR); | |
171 | ||
68b30bb9 AB |
172 | if (ppmu->flags & PPMU_ALT_SIPR) |
173 | sipr = POWER6_MMCRA_SIPR; | |
174 | ||
5682c460 | 175 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
176 | } |
177 | ||
860aad71 ME |
178 | static bool regs_no_sipr(struct pt_regs *regs) |
179 | { | |
180 | return !!(regs->result & 2); | |
181 | } | |
182 | ||
1ce447b9 BH |
183 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
184 | { | |
185 | if (regs->msr & MSR_PR) | |
186 | return PERF_RECORD_MISC_USER; | |
187 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
188 | return PERF_RECORD_MISC_HYPERVISOR; | |
189 | return PERF_RECORD_MISC_KERNEL; | |
190 | } | |
191 | ||
98fb1807 PM |
192 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
193 | { | |
33904054 | 194 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 195 | |
75382aa7 | 196 | if (!use_siar) |
1ce447b9 BH |
197 | return perf_flags_from_msr(regs); |
198 | ||
199 | /* | |
200 | * If we don't have flags in MMCRA, rather than using | |
201 | * the MSR, we intuit the flags from the address in | |
202 | * SIAR which should give slightly more reliable | |
203 | * results | |
204 | */ | |
860aad71 | 205 | if (regs_no_sipr(regs)) { |
1ce447b9 BH |
206 | unsigned long siar = mfspr(SPRN_SIAR); |
207 | if (siar >= PAGE_OFFSET) | |
208 | return PERF_RECORD_MISC_KERNEL; | |
209 | return PERF_RECORD_MISC_USER; | |
210 | } | |
98fb1807 | 211 | |
7abb840b | 212 | /* PR has priority over HV, so order below is important */ |
5682c460 | 213 | if (regs_sipr(regs)) |
7abb840b | 214 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
215 | |
216 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 217 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 218 | |
7abb840b | 219 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
220 | } |
221 | ||
222 | /* | |
223 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
224 | * on each interrupt. | |
8f61aa32 | 225 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
226 | * Overload regs->result to specify whether we should use the MSR (result |
227 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
228 | */ |
229 | static inline void perf_read_regs(struct pt_regs *regs) | |
230 | { | |
75382aa7 AB |
231 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
232 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
233 | int use_siar; | |
234 | ||
5682c460 | 235 | regs->dsisr = mmcra; |
860aad71 ME |
236 | regs->result = 0; |
237 | ||
238 | if (ppmu->flags & PPMU_NO_SIPR) | |
239 | regs->result |= 2; | |
5682c460 | 240 | |
8f61aa32 ME |
241 | /* |
242 | * On power8 if we're in random sampling mode, the SIER is updated. | |
243 | * If we're in continuous sampling mode, we don't have SIPR. | |
244 | */ | |
245 | if (ppmu->flags & PPMU_HAS_SIER) { | |
246 | if (marked) | |
247 | regs->dar = mfspr(SPRN_SIER); | |
248 | else | |
249 | regs->result |= 2; | |
250 | } | |
251 | ||
252 | ||
5c093efa AB |
253 | /* |
254 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
255 | * not valid. Use pt_regs. | |
256 | * | |
257 | * If it is a marked event use the SIAR. | |
258 | * | |
259 | * If the PMU doesn't update the SIAR for non marked events use | |
260 | * pt_regs. | |
261 | * | |
262 | * If the PMU has HV/PR flags then check to see if they | |
263 | * place the exception in userspace. If so, use pt_regs. In | |
264 | * continuous sampling mode the SIAR and the PMU exception are | |
265 | * not synchronised, so they may be many instructions apart. | |
266 | * This can result in confusing backtraces. We still want | |
267 | * hypervisor samples as well as samples in the kernel with | |
268 | * interrupts off hence the userspace check. | |
269 | */ | |
75382aa7 AB |
270 | if (TRAP(regs) != 0xf00) |
271 | use_siar = 0; | |
5c093efa AB |
272 | else if (marked) |
273 | use_siar = 1; | |
274 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
275 | use_siar = 0; | |
860aad71 | 276 | else if (!regs_no_sipr(regs) && regs_sipr(regs)) |
75382aa7 AB |
277 | use_siar = 0; |
278 | else | |
279 | use_siar = 1; | |
280 | ||
860aad71 | 281 | regs->result |= use_siar; |
98fb1807 PM |
282 | } |
283 | ||
284 | /* | |
285 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
286 | * it as an NMI. | |
287 | */ | |
288 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
289 | { | |
290 | return !regs->softe; | |
291 | } | |
292 | ||
e6878835 | 293 | /* |
294 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
295 | * must be sampled only if the SIAR-valid bit is set. | |
296 | * | |
297 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
298 | * bit, assume that SIAR is valid. | |
299 | */ | |
300 | static inline int siar_valid(struct pt_regs *regs) | |
301 | { | |
302 | unsigned long mmcra = regs->dsisr; | |
303 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
304 | ||
305 | if ((ppmu->flags & PPMU_SIAR_VALID) && marked) | |
306 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
307 | ||
308 | return 1; | |
309 | } | |
310 | ||
98fb1807 PM |
311 | #endif /* CONFIG_PPC64 */ |
312 | ||
cdd6c482 | 313 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 314 | |
cdd6c482 | 315 | void perf_event_print_debug(void) |
4574910e PM |
316 | { |
317 | } | |
318 | ||
4574910e | 319 | /* |
57c0c15b | 320 | * Read one performance monitor counter (PMC). |
4574910e PM |
321 | */ |
322 | static unsigned long read_pmc(int idx) | |
323 | { | |
324 | unsigned long val; | |
325 | ||
326 | switch (idx) { | |
327 | case 1: | |
328 | val = mfspr(SPRN_PMC1); | |
329 | break; | |
330 | case 2: | |
331 | val = mfspr(SPRN_PMC2); | |
332 | break; | |
333 | case 3: | |
334 | val = mfspr(SPRN_PMC3); | |
335 | break; | |
336 | case 4: | |
337 | val = mfspr(SPRN_PMC4); | |
338 | break; | |
339 | case 5: | |
340 | val = mfspr(SPRN_PMC5); | |
341 | break; | |
342 | case 6: | |
343 | val = mfspr(SPRN_PMC6); | |
344 | break; | |
98fb1807 | 345 | #ifdef CONFIG_PPC64 |
4574910e PM |
346 | case 7: |
347 | val = mfspr(SPRN_PMC7); | |
348 | break; | |
349 | case 8: | |
350 | val = mfspr(SPRN_PMC8); | |
351 | break; | |
98fb1807 | 352 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
353 | default: |
354 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
355 | val = 0; | |
356 | } | |
357 | return val; | |
358 | } | |
359 | ||
360 | /* | |
361 | * Write one PMC. | |
362 | */ | |
363 | static void write_pmc(int idx, unsigned long val) | |
364 | { | |
365 | switch (idx) { | |
366 | case 1: | |
367 | mtspr(SPRN_PMC1, val); | |
368 | break; | |
369 | case 2: | |
370 | mtspr(SPRN_PMC2, val); | |
371 | break; | |
372 | case 3: | |
373 | mtspr(SPRN_PMC3, val); | |
374 | break; | |
375 | case 4: | |
376 | mtspr(SPRN_PMC4, val); | |
377 | break; | |
378 | case 5: | |
379 | mtspr(SPRN_PMC5, val); | |
380 | break; | |
381 | case 6: | |
382 | mtspr(SPRN_PMC6, val); | |
383 | break; | |
98fb1807 | 384 | #ifdef CONFIG_PPC64 |
4574910e PM |
385 | case 7: |
386 | mtspr(SPRN_PMC7, val); | |
387 | break; | |
388 | case 8: | |
389 | mtspr(SPRN_PMC8, val); | |
390 | break; | |
98fb1807 | 391 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
392 | default: |
393 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
394 | } | |
395 | } | |
396 | ||
397 | /* | |
398 | * Check if a set of events can all go on the PMU at once. | |
399 | * If they can't, this will look at alternative codes for the events | |
400 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 401 | * The feasible set is returned in event_id[]. |
4574910e | 402 | */ |
cdd6c482 IM |
403 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
404 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 405 | int n_ev) |
4574910e | 406 | { |
448d64f8 | 407 | unsigned long mask, value, nv; |
cdd6c482 IM |
408 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
409 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 410 | int i, j; |
448d64f8 PM |
411 | unsigned long addf = ppmu->add_fields; |
412 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 413 | |
a8f90e90 | 414 | if (n_ev > ppmu->n_counter) |
4574910e PM |
415 | return -1; |
416 | ||
417 | /* First see if the events will go on as-is */ | |
418 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 419 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
420 | && !ppmu->limited_pmc_event(event_id[i])) { |
421 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 422 | cpuhw->alternatives[i]); |
cdd6c482 | 423 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 424 | } |
cdd6c482 | 425 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 426 | &cpuhw->avalues[i][0])) |
4574910e | 427 | return -1; |
4574910e PM |
428 | } |
429 | value = mask = 0; | |
430 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
431 | nv = (value | cpuhw->avalues[i][0]) + |
432 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 433 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
434 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
435 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
436 | break; |
437 | value = nv; | |
e51ee31e | 438 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
439 | } |
440 | if (i == n_ev) | |
441 | return 0; /* all OK */ | |
442 | ||
443 | /* doesn't work, gather alternatives... */ | |
444 | if (!ppmu->get_alternatives) | |
445 | return -1; | |
446 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 447 | choice[i] = 0; |
cdd6c482 | 448 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 449 | cpuhw->alternatives[i]); |
4574910e | 450 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
451 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
452 | &cpuhw->amasks[i][j], | |
453 | &cpuhw->avalues[i][j]); | |
4574910e PM |
454 | } |
455 | ||
456 | /* enumerate all possibilities and see if any will work */ | |
457 | i = 0; | |
458 | j = -1; | |
459 | value = mask = nv = 0; | |
460 | while (i < n_ev) { | |
461 | if (j >= 0) { | |
462 | /* we're backtracking, restore context */ | |
463 | value = svalues[i]; | |
464 | mask = smasks[i]; | |
465 | j = choice[i]; | |
466 | } | |
467 | /* | |
cdd6c482 | 468 | * See if any alternative k for event_id i, |
4574910e PM |
469 | * where k > j, will satisfy the constraints. |
470 | */ | |
471 | while (++j < n_alt[i]) { | |
e51ee31e PM |
472 | nv = (value | cpuhw->avalues[i][j]) + |
473 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 474 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
475 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
476 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
477 | break; |
478 | } | |
479 | if (j >= n_alt[i]) { | |
480 | /* | |
481 | * No feasible alternative, backtrack | |
cdd6c482 | 482 | * to event_id i-1 and continue enumerating its |
4574910e PM |
483 | * alternatives from where we got up to. |
484 | */ | |
485 | if (--i < 0) | |
486 | return -1; | |
487 | } else { | |
488 | /* | |
cdd6c482 IM |
489 | * Found a feasible alternative for event_id i, |
490 | * remember where we got up to with this event_id, | |
491 | * go on to the next event_id, and start with | |
4574910e PM |
492 | * the first alternative for it. |
493 | */ | |
494 | choice[i] = j; | |
495 | svalues[i] = value; | |
496 | smasks[i] = mask; | |
497 | value = nv; | |
e51ee31e | 498 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
499 | ++i; |
500 | j = -1; | |
501 | } | |
502 | } | |
503 | ||
504 | /* OK, we have a feasible combination, tell the caller the solution */ | |
505 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 506 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
507 | return 0; |
508 | } | |
509 | ||
0475f9ea | 510 | /* |
cdd6c482 | 511 | * Check if newly-added events have consistent settings for |
0475f9ea | 512 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 513 | * added events. |
0475f9ea | 514 | */ |
cdd6c482 | 515 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 516 | int n_prev, int n_new) |
0475f9ea | 517 | { |
ab7ef2e5 PM |
518 | int eu = 0, ek = 0, eh = 0; |
519 | int i, n, first; | |
cdd6c482 | 520 | struct perf_event *event; |
0475f9ea PM |
521 | |
522 | n = n_prev + n_new; | |
523 | if (n <= 1) | |
524 | return 0; | |
525 | ||
ab7ef2e5 PM |
526 | first = 1; |
527 | for (i = 0; i < n; ++i) { | |
528 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
529 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
530 | continue; | |
531 | } | |
cdd6c482 | 532 | event = ctrs[i]; |
ab7ef2e5 | 533 | if (first) { |
cdd6c482 IM |
534 | eu = event->attr.exclude_user; |
535 | ek = event->attr.exclude_kernel; | |
536 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 537 | first = 0; |
cdd6c482 IM |
538 | } else if (event->attr.exclude_user != eu || |
539 | event->attr.exclude_kernel != ek || | |
540 | event->attr.exclude_hv != eh) { | |
0475f9ea | 541 | return -EAGAIN; |
ab7ef2e5 | 542 | } |
0475f9ea | 543 | } |
ab7ef2e5 PM |
544 | |
545 | if (eu || ek || eh) | |
546 | for (i = 0; i < n; ++i) | |
547 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
548 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
549 | ||
0475f9ea PM |
550 | return 0; |
551 | } | |
552 | ||
86c74ab3 EM |
553 | static u64 check_and_compute_delta(u64 prev, u64 val) |
554 | { | |
555 | u64 delta = (val - prev) & 0xfffffffful; | |
556 | ||
557 | /* | |
558 | * POWER7 can roll back counter values, if the new value is smaller | |
559 | * than the previous value it will cause the delta and the counter to | |
560 | * have bogus values unless we rolled a counter over. If a coutner is | |
561 | * rolled back, it will be smaller, but within 256, which is the maximum | |
562 | * number of events to rollback at once. If we dectect a rollback | |
563 | * return 0. This can lead to a small lack of precision in the | |
564 | * counters. | |
565 | */ | |
566 | if (prev > val && (prev - val) < 256) | |
567 | delta = 0; | |
568 | ||
569 | return delta; | |
570 | } | |
571 | ||
cdd6c482 | 572 | static void power_pmu_read(struct perf_event *event) |
4574910e | 573 | { |
98fb1807 | 574 | s64 val, delta, prev; |
4574910e | 575 | |
a4eaf7f1 PZ |
576 | if (event->hw.state & PERF_HES_STOPPED) |
577 | return; | |
578 | ||
cdd6c482 | 579 | if (!event->hw.idx) |
4574910e PM |
580 | return; |
581 | /* | |
582 | * Performance monitor interrupts come even when interrupts | |
583 | * are soft-disabled, as long as interrupts are hard-enabled. | |
584 | * Therefore we treat them like NMIs. | |
585 | */ | |
586 | do { | |
e7850595 | 587 | prev = local64_read(&event->hw.prev_count); |
4574910e | 588 | barrier(); |
cdd6c482 | 589 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
590 | delta = check_and_compute_delta(prev, val); |
591 | if (!delta) | |
592 | return; | |
e7850595 | 593 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 594 | |
e7850595 PZ |
595 | local64_add(delta, &event->count); |
596 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
597 | } |
598 | ||
ab7ef2e5 PM |
599 | /* |
600 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
601 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 602 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
603 | */ |
604 | static int is_limited_pmc(int pmcnum) | |
605 | { | |
0bbd0d4b PM |
606 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
607 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
608 | } |
609 | ||
a8f90e90 | 610 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
611 | unsigned long pmc5, unsigned long pmc6) |
612 | { | |
cdd6c482 | 613 | struct perf_event *event; |
ab7ef2e5 PM |
614 | u64 val, prev, delta; |
615 | int i; | |
616 | ||
617 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 618 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 619 | if (!event->hw.idx) |
ab7ef2e5 | 620 | continue; |
cdd6c482 | 621 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 622 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 623 | event->hw.idx = 0; |
86c74ab3 EM |
624 | delta = check_and_compute_delta(prev, val); |
625 | if (delta) | |
626 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
627 | } |
628 | } | |
629 | ||
a8f90e90 | 630 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
631 | unsigned long pmc5, unsigned long pmc6) |
632 | { | |
cdd6c482 | 633 | struct perf_event *event; |
86c74ab3 | 634 | u64 val, prev; |
ab7ef2e5 PM |
635 | int i; |
636 | ||
637 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 638 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
639 | event->hw.idx = cpuhw->limited_hwidx[i]; |
640 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
641 | prev = local64_read(&event->hw.prev_count); |
642 | if (check_and_compute_delta(prev, val)) | |
643 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 644 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
645 | } |
646 | } | |
647 | ||
648 | /* | |
cdd6c482 | 649 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 650 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
651 | * other events. We try to keep the values from the limited |
652 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 653 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
654 | * the limited events as small and consistent as possible. |
655 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
656 | * both, and always in the same order, to minimize variability, |
657 | * and do it inside the same asm that writes MMCR0. | |
658 | */ | |
cdd6c482 | 659 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
660 | { |
661 | unsigned long pmc5, pmc6; | |
662 | ||
663 | if (!cpuhw->n_limited) { | |
664 | mtspr(SPRN_MMCR0, mmcr0); | |
665 | return; | |
666 | } | |
667 | ||
668 | /* | |
669 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
670 | * To ensure we don't get a performance monitor interrupt |
671 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 672 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 673 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
674 | */ |
675 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
676 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
677 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
678 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
679 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
680 | ||
681 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 682 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 683 | else |
a8f90e90 | 684 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
685 | |
686 | /* | |
cdd6c482 | 687 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
688 | * enable bits, if necessary. |
689 | */ | |
690 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
691 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
692 | } |
693 | ||
4574910e | 694 | /* |
cdd6c482 IM |
695 | * Disable all events to prevent PMU interrupts and to allow |
696 | * events to be added or removed. | |
4574910e | 697 | */ |
a4eaf7f1 | 698 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 699 | { |
cdd6c482 | 700 | struct cpu_hw_events *cpuhw; |
4574910e PM |
701 | unsigned long flags; |
702 | ||
f36a1a13 PM |
703 | if (!ppmu) |
704 | return; | |
4574910e | 705 | local_irq_save(flags); |
cdd6c482 | 706 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 707 | |
448d64f8 | 708 | if (!cpuhw->disabled) { |
4574910e PM |
709 | cpuhw->disabled = 1; |
710 | cpuhw->n_added = 0; | |
711 | ||
01d0287f PM |
712 | /* |
713 | * Check if we ever enabled the PMU on this cpu. | |
714 | */ | |
715 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 716 | ppc_enable_pmcs(); |
01d0287f PM |
717 | cpuhw->pmcs_enabled = 1; |
718 | } | |
719 | ||
f708223d PM |
720 | /* |
721 | * Disable instruction sampling if it was enabled | |
722 | */ | |
723 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
724 | mtspr(SPRN_MMCRA, | |
725 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
726 | mb(); | |
727 | } | |
728 | ||
4574910e | 729 | /* |
57c0c15b | 730 | * Set the 'freeze counters' bit. |
4574910e | 731 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 732 | * executed and the PMU has frozen the events |
4574910e PM |
733 | * before we return. |
734 | */ | |
ab7ef2e5 | 735 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
736 | mb(); |
737 | } | |
738 | local_irq_restore(flags); | |
4574910e PM |
739 | } |
740 | ||
741 | /* | |
cdd6c482 IM |
742 | * Re-enable all events if disable == 0. |
743 | * If we were previously disabled and events were added, then | |
4574910e PM |
744 | * put the new config on the PMU. |
745 | */ | |
a4eaf7f1 | 746 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 747 | { |
cdd6c482 IM |
748 | struct perf_event *event; |
749 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
750 | unsigned long flags; |
751 | long i; | |
752 | unsigned long val; | |
753 | s64 left; | |
cdd6c482 | 754 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
755 | int n_lim; |
756 | int idx; | |
4574910e | 757 | |
f36a1a13 PM |
758 | if (!ppmu) |
759 | return; | |
4574910e | 760 | local_irq_save(flags); |
cdd6c482 | 761 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
762 | if (!cpuhw->disabled) { |
763 | local_irq_restore(flags); | |
764 | return; | |
765 | } | |
4574910e PM |
766 | cpuhw->disabled = 0; |
767 | ||
768 | /* | |
cdd6c482 | 769 | * If we didn't change anything, or only removed events, |
4574910e PM |
770 | * no need to recalculate MMCR* settings and reset the PMCs. |
771 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 772 | * (possibly updated for removal of events). |
4574910e PM |
773 | */ |
774 | if (!cpuhw->n_added) { | |
f708223d | 775 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 776 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 777 | if (cpuhw->n_events == 0) |
a6dbf93a | 778 | ppc_set_pmu_inuse(0); |
f708223d | 779 | goto out_enable; |
4574910e PM |
780 | } |
781 | ||
782 | /* | |
cdd6c482 | 783 | * Compute MMCR* values for the new set of events |
4574910e | 784 | */ |
cdd6c482 | 785 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
786 | cpuhw->mmcr)) { |
787 | /* shouldn't ever get here */ | |
788 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
789 | goto out; | |
790 | } | |
791 | ||
0475f9ea PM |
792 | /* |
793 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
794 | * attr.exclude_* bits for the first event. |
795 | * We have already checked that all events have the | |
796 | * same values for these bits as the first event. | |
0475f9ea | 797 | */ |
cdd6c482 IM |
798 | event = cpuhw->event[0]; |
799 | if (event->attr.exclude_user) | |
0475f9ea | 800 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
801 | if (event->attr.exclude_kernel) |
802 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
803 | if (event->attr.exclude_hv) | |
0475f9ea PM |
804 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
805 | ||
4574910e PM |
806 | /* |
807 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
808 | * bit set and set the hardware events to their initial values. |
809 | * Then unfreeze the events. | |
4574910e | 810 | */ |
a6dbf93a | 811 | ppc_set_pmu_inuse(1); |
f708223d | 812 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
813 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
814 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
815 | | MMCR0_FC); | |
816 | ||
817 | /* | |
cdd6c482 | 818 | * Read off any pre-existing events that need to move |
4574910e PM |
819 | * to another PMC. |
820 | */ | |
cdd6c482 IM |
821 | for (i = 0; i < cpuhw->n_events; ++i) { |
822 | event = cpuhw->event[i]; | |
823 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
824 | power_pmu_read(event); | |
825 | write_pmc(event->hw.idx, 0); | |
826 | event->hw.idx = 0; | |
4574910e PM |
827 | } |
828 | } | |
829 | ||
830 | /* | |
cdd6c482 | 831 | * Initialize the PMCs for all the new and moved events. |
4574910e | 832 | */ |
ab7ef2e5 | 833 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
834 | for (i = 0; i < cpuhw->n_events; ++i) { |
835 | event = cpuhw->event[i]; | |
836 | if (event->hw.idx) | |
4574910e | 837 | continue; |
ab7ef2e5 PM |
838 | idx = hwc_index[i] + 1; |
839 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 840 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
841 | cpuhw->limited_hwidx[n_lim] = idx; |
842 | ++n_lim; | |
843 | continue; | |
844 | } | |
4574910e | 845 | val = 0; |
cdd6c482 | 846 | if (event->hw.sample_period) { |
e7850595 | 847 | left = local64_read(&event->hw.period_left); |
4574910e PM |
848 | if (left < 0x80000000L) |
849 | val = 0x80000000L - left; | |
850 | } | |
e7850595 | 851 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 852 | event->hw.idx = idx; |
a4eaf7f1 PZ |
853 | if (event->hw.state & PERF_HES_STOPPED) |
854 | val = 0; | |
ab7ef2e5 | 855 | write_pmc(idx, val); |
cdd6c482 | 856 | perf_event_update_userpage(event); |
4574910e | 857 | } |
ab7ef2e5 | 858 | cpuhw->n_limited = n_lim; |
4574910e | 859 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
860 | |
861 | out_enable: | |
862 | mb(); | |
ab7ef2e5 | 863 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 864 | |
f708223d PM |
865 | /* |
866 | * Enable instruction sampling if necessary | |
867 | */ | |
868 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
869 | mb(); | |
870 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
871 | } | |
872 | ||
4574910e | 873 | out: |
3925f46b AK |
874 | if (cpuhw->bhrb_users) |
875 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
876 | ||
4574910e PM |
877 | local_irq_restore(flags); |
878 | } | |
879 | ||
cdd6c482 IM |
880 | static int collect_events(struct perf_event *group, int max_count, |
881 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 882 | unsigned int *flags) |
4574910e PM |
883 | { |
884 | int n = 0; | |
cdd6c482 | 885 | struct perf_event *event; |
4574910e | 886 | |
cdd6c482 | 887 | if (!is_software_event(group)) { |
4574910e PM |
888 | if (n >= max_count) |
889 | return -1; | |
890 | ctrs[n] = group; | |
cdd6c482 | 891 | flags[n] = group->hw.event_base; |
4574910e PM |
892 | events[n++] = group->hw.config; |
893 | } | |
a8f90e90 | 894 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
895 | if (!is_software_event(event) && |
896 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
897 | if (n >= max_count) |
898 | return -1; | |
cdd6c482 IM |
899 | ctrs[n] = event; |
900 | flags[n] = event->hw.event_base; | |
901 | events[n++] = event->hw.config; | |
4574910e PM |
902 | } |
903 | } | |
904 | return n; | |
905 | } | |
906 | ||
3925f46b AK |
907 | /* Reset all possible BHRB entries */ |
908 | static void power_pmu_bhrb_reset(void) | |
909 | { | |
910 | asm volatile(PPC_CLRBHRB); | |
911 | } | |
912 | ||
913 | void power_pmu_bhrb_enable(struct perf_event *event) | |
914 | { | |
915 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
916 | ||
917 | if (!ppmu->bhrb_nr) | |
918 | return; | |
919 | ||
920 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
921 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
922 | power_pmu_bhrb_reset(); | |
923 | cpuhw->bhrb_context = event->ctx; | |
924 | } | |
925 | cpuhw->bhrb_users++; | |
926 | } | |
927 | ||
928 | void power_pmu_bhrb_disable(struct perf_event *event) | |
929 | { | |
930 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
931 | ||
932 | if (!ppmu->bhrb_nr) | |
933 | return; | |
934 | ||
935 | cpuhw->bhrb_users--; | |
936 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
937 | ||
938 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
939 | /* BHRB cannot be turned off when other | |
940 | * events are active on the PMU. | |
941 | */ | |
942 | ||
943 | /* avoid stale pointer */ | |
944 | cpuhw->bhrb_context = NULL; | |
945 | } | |
946 | } | |
947 | ||
4574910e | 948 | /* |
cdd6c482 IM |
949 | * Add a event to the PMU. |
950 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 951 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
952 | * actual work of reconfiguring the PMU. |
953 | */ | |
a4eaf7f1 | 954 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 955 | { |
cdd6c482 | 956 | struct cpu_hw_events *cpuhw; |
4574910e | 957 | unsigned long flags; |
4574910e PM |
958 | int n0; |
959 | int ret = -EAGAIN; | |
960 | ||
961 | local_irq_save(flags); | |
33696fc0 | 962 | perf_pmu_disable(event->pmu); |
4574910e PM |
963 | |
964 | /* | |
cdd6c482 | 965 | * Add the event to the list (if there is room) |
4574910e PM |
966 | * and check whether the total set is still feasible. |
967 | */ | |
cdd6c482 IM |
968 | cpuhw = &__get_cpu_var(cpu_hw_events); |
969 | n0 = cpuhw->n_events; | |
a8f90e90 | 970 | if (n0 >= ppmu->n_counter) |
4574910e | 971 | goto out; |
cdd6c482 IM |
972 | cpuhw->event[n0] = event; |
973 | cpuhw->events[n0] = event->hw.config; | |
974 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 975 | |
f53d168c | 976 | /* |
977 | * This event may have been disabled/stopped in record_and_restart() | |
978 | * because we exceeded the ->event_limit. If re-starting the event, | |
979 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
980 | * notification is re-enabled. | |
981 | */ | |
a4eaf7f1 PZ |
982 | if (!(ef_flags & PERF_EF_START)) |
983 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 984 | else |
985 | event->hw.state = 0; | |
a4eaf7f1 | 986 | |
8e6d5573 LM |
987 | /* |
988 | * If group events scheduling transaction was started, | |
25985edc | 989 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
990 | * at commit time(->commit_txn) as a whole |
991 | */ | |
8d2cacbb | 992 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
993 | goto nocheck; |
994 | ||
cdd6c482 | 995 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 996 | goto out; |
e51ee31e | 997 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 998 | goto out; |
cdd6c482 | 999 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1000 | |
1001 | nocheck: | |
cdd6c482 | 1002 | ++cpuhw->n_events; |
4574910e PM |
1003 | ++cpuhw->n_added; |
1004 | ||
1005 | ret = 0; | |
1006 | out: | |
3925f46b AK |
1007 | if (has_branch_stack(event)) |
1008 | power_pmu_bhrb_enable(event); | |
1009 | ||
33696fc0 | 1010 | perf_pmu_enable(event->pmu); |
4574910e PM |
1011 | local_irq_restore(flags); |
1012 | return ret; | |
1013 | } | |
1014 | ||
1015 | /* | |
cdd6c482 | 1016 | * Remove a event from the PMU. |
4574910e | 1017 | */ |
a4eaf7f1 | 1018 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1019 | { |
cdd6c482 | 1020 | struct cpu_hw_events *cpuhw; |
4574910e | 1021 | long i; |
4574910e PM |
1022 | unsigned long flags; |
1023 | ||
1024 | local_irq_save(flags); | |
33696fc0 | 1025 | perf_pmu_disable(event->pmu); |
4574910e | 1026 | |
cdd6c482 IM |
1027 | power_pmu_read(event); |
1028 | ||
1029 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1030 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1031 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1032 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1033 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1034 | cpuhw->events[i-1] = cpuhw->events[i]; |
1035 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1036 | } | |
cdd6c482 IM |
1037 | --cpuhw->n_events; |
1038 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1039 | if (event->hw.idx) { | |
1040 | write_pmc(event->hw.idx, 0); | |
1041 | event->hw.idx = 0; | |
ab7ef2e5 | 1042 | } |
cdd6c482 | 1043 | perf_event_update_userpage(event); |
4574910e PM |
1044 | break; |
1045 | } | |
1046 | } | |
ab7ef2e5 | 1047 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1048 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1049 | break; |
1050 | if (i < cpuhw->n_limited) { | |
1051 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1052 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1053 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1054 | } | |
1055 | --cpuhw->n_limited; | |
1056 | } | |
cdd6c482 IM |
1057 | if (cpuhw->n_events == 0) { |
1058 | /* disable exceptions if no events are running */ | |
4574910e PM |
1059 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1060 | } | |
1061 | ||
3925f46b AK |
1062 | if (has_branch_stack(event)) |
1063 | power_pmu_bhrb_disable(event); | |
1064 | ||
33696fc0 | 1065 | perf_pmu_enable(event->pmu); |
4574910e PM |
1066 | local_irq_restore(flags); |
1067 | } | |
1068 | ||
8a7b8cb9 | 1069 | /* |
a4eaf7f1 PZ |
1070 | * POWER-PMU does not support disabling individual counters, hence |
1071 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1072 | */ |
a4eaf7f1 PZ |
1073 | |
1074 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1075 | { |
8a7b8cb9 | 1076 | unsigned long flags; |
a4eaf7f1 | 1077 | s64 left; |
9a45a940 | 1078 | unsigned long val; |
8a7b8cb9 | 1079 | |
cdd6c482 | 1080 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1081 | return; |
a4eaf7f1 PZ |
1082 | |
1083 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1084 | return; | |
1085 | ||
1086 | if (ef_flags & PERF_EF_RELOAD) | |
1087 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1088 | ||
1089 | local_irq_save(flags); | |
1090 | perf_pmu_disable(event->pmu); | |
1091 | ||
1092 | event->hw.state = 0; | |
1093 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1094 | |
1095 | val = 0; | |
1096 | if (left < 0x80000000L) | |
1097 | val = 0x80000000L - left; | |
1098 | ||
1099 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1100 | |
1101 | perf_event_update_userpage(event); | |
1102 | perf_pmu_enable(event->pmu); | |
1103 | local_irq_restore(flags); | |
1104 | } | |
1105 | ||
1106 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1107 | { | |
1108 | unsigned long flags; | |
1109 | ||
1110 | if (!event->hw.idx || !event->hw.sample_period) | |
1111 | return; | |
1112 | ||
1113 | if (event->hw.state & PERF_HES_STOPPED) | |
1114 | return; | |
1115 | ||
8a7b8cb9 | 1116 | local_irq_save(flags); |
33696fc0 | 1117 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1118 | |
cdd6c482 | 1119 | power_pmu_read(event); |
a4eaf7f1 PZ |
1120 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1121 | write_pmc(event->hw.idx, 0); | |
1122 | ||
cdd6c482 | 1123 | perf_event_update_userpage(event); |
33696fc0 | 1124 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1125 | local_irq_restore(flags); |
1126 | } | |
1127 | ||
8e6d5573 LM |
1128 | /* |
1129 | * Start group events scheduling transaction | |
1130 | * Set the flag to make pmu::enable() not perform the | |
1131 | * schedulability test, it will be performed at commit time | |
1132 | */ | |
51b0fe39 | 1133 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1134 | { |
1135 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1136 | ||
33696fc0 | 1137 | perf_pmu_disable(pmu); |
8d2cacbb | 1138 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1139 | cpuhw->n_txn_start = cpuhw->n_events; |
1140 | } | |
1141 | ||
1142 | /* | |
1143 | * Stop group events scheduling transaction | |
1144 | * Clear the flag and pmu::enable() will perform the | |
1145 | * schedulability test. | |
1146 | */ | |
51b0fe39 | 1147 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1148 | { |
1149 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1150 | ||
8d2cacbb | 1151 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1152 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1153 | } |
1154 | ||
1155 | /* | |
1156 | * Commit group events scheduling transaction | |
1157 | * Perform the group schedulability test as a whole | |
1158 | * Return 0 if success | |
1159 | */ | |
51b0fe39 | 1160 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1161 | { |
1162 | struct cpu_hw_events *cpuhw; | |
1163 | long i, n; | |
1164 | ||
1165 | if (!ppmu) | |
1166 | return -EAGAIN; | |
1167 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1168 | n = cpuhw->n_events; | |
1169 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1170 | return -EAGAIN; | |
1171 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1172 | if (i < 0) | |
1173 | return -EAGAIN; | |
1174 | ||
1175 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1176 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1177 | ||
8d2cacbb | 1178 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1179 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1180 | return 0; |
1181 | } | |
1182 | ||
3925f46b AK |
1183 | /* Called from ctxsw to prevent one process's branch entries to |
1184 | * mingle with the other process's entries during context switch. | |
1185 | */ | |
1186 | void power_pmu_flush_branch_stack(void) | |
1187 | { | |
1188 | if (ppmu->bhrb_nr) | |
1189 | power_pmu_bhrb_reset(); | |
1190 | } | |
1191 | ||
ab7ef2e5 | 1192 | /* |
cdd6c482 | 1193 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1194 | * or 0 if not. |
cdd6c482 | 1195 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1196 | * that a limited PMC can count, doesn't require interrupts, and |
1197 | * doesn't exclude any processor mode. | |
1198 | */ | |
cdd6c482 | 1199 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1200 | unsigned int flags) |
1201 | { | |
1202 | int n; | |
ef923214 | 1203 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1204 | |
cdd6c482 IM |
1205 | if (event->attr.exclude_user |
1206 | || event->attr.exclude_kernel | |
1207 | || event->attr.exclude_hv | |
1208 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1209 | return 0; |
1210 | ||
1211 | if (ppmu->limited_pmc_event(ev)) | |
1212 | return 1; | |
1213 | ||
1214 | /* | |
cdd6c482 | 1215 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1216 | * see if any alternative code goes on a limited PMC. |
1217 | */ | |
1218 | if (!ppmu->get_alternatives) | |
1219 | return 0; | |
1220 | ||
1221 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1222 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1223 | |
ef923214 | 1224 | return n > 0; |
ab7ef2e5 PM |
1225 | } |
1226 | ||
1227 | /* | |
cdd6c482 IM |
1228 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1229 | * and return the event_id code, or 0 if there is no such alternative. | |
1230 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1231 | */ |
ef923214 | 1232 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1233 | { |
ef923214 | 1234 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1235 | int n; |
1236 | ||
1237 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1238 | n = ppmu->get_alternatives(ev, flags, alt); | |
1239 | if (!n) | |
1240 | return 0; | |
1241 | return alt[0]; | |
1242 | } | |
1243 | ||
cdd6c482 IM |
1244 | /* Number of perf_events counting hardware events */ |
1245 | static atomic_t num_events; | |
7595d63b PM |
1246 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1247 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1248 | ||
1249 | /* | |
cdd6c482 | 1250 | * Release the PMU if this is the last perf_event. |
7595d63b | 1251 | */ |
cdd6c482 | 1252 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1253 | { |
cdd6c482 | 1254 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1255 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1256 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1257 | release_pmc_hardware(); |
1258 | mutex_unlock(&pmc_reserve_mutex); | |
1259 | } | |
1260 | } | |
1261 | ||
106b506c | 1262 | /* |
cdd6c482 | 1263 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1264 | */ |
1265 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1266 | { | |
1267 | unsigned long type, op, result; | |
1268 | int ev; | |
1269 | ||
1270 | if (!ppmu->cache_events) | |
1271 | return -EINVAL; | |
1272 | ||
1273 | /* unpack config */ | |
1274 | type = config & 0xff; | |
1275 | op = (config >> 8) & 0xff; | |
1276 | result = (config >> 16) & 0xff; | |
1277 | ||
1278 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1279 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1280 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1281 | return -EINVAL; | |
1282 | ||
1283 | ev = (*ppmu->cache_events)[type][op][result]; | |
1284 | if (ev == 0) | |
1285 | return -EOPNOTSUPP; | |
1286 | if (ev == -1) | |
1287 | return -EINVAL; | |
1288 | *eventp = ev; | |
1289 | return 0; | |
1290 | } | |
1291 | ||
b0a873eb | 1292 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1293 | { |
ef923214 PM |
1294 | u64 ev; |
1295 | unsigned long flags; | |
cdd6c482 IM |
1296 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1297 | u64 events[MAX_HWEVENTS]; | |
1298 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1299 | int n; |
7595d63b | 1300 | int err; |
cdd6c482 | 1301 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1302 | |
1303 | if (!ppmu) | |
b0a873eb PZ |
1304 | return -ENOENT; |
1305 | ||
3925f46b AK |
1306 | if (has_branch_stack(event)) { |
1307 | /* PMU has BHRB enabled */ | |
1308 | if (!(ppmu->flags & PPMU_BHRB)) | |
1309 | return -EOPNOTSUPP; | |
1310 | } | |
2481c5fa | 1311 | |
cdd6c482 | 1312 | switch (event->attr.type) { |
106b506c | 1313 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1314 | ev = event->attr.config; |
9aaa131a | 1315 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1316 | return -EOPNOTSUPP; |
4574910e | 1317 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1318 | break; |
1319 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1320 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1321 | if (err) |
b0a873eb | 1322 | return err; |
106b506c PM |
1323 | break; |
1324 | case PERF_TYPE_RAW: | |
cdd6c482 | 1325 | ev = event->attr.config; |
106b506c | 1326 | break; |
90c8f954 | 1327 | default: |
b0a873eb | 1328 | return -ENOENT; |
4574910e | 1329 | } |
b0a873eb | 1330 | |
cdd6c482 IM |
1331 | event->hw.config_base = ev; |
1332 | event->hw.idx = 0; | |
4574910e | 1333 | |
0475f9ea PM |
1334 | /* |
1335 | * If we are not running on a hypervisor, force the | |
1336 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1337 | * the user set it to. |
0475f9ea PM |
1338 | */ |
1339 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1340 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1341 | |
1342 | /* | |
cdd6c482 | 1343 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1344 | * PM_RUN_* events interchangeably with their non RUN_* |
1345 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1346 | * XXX we should check if the task is an idle task. | |
1347 | */ | |
1348 | flags = 0; | |
57fa7214 | 1349 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1350 | flags |= PPMU_ONLY_COUNT_RUN; |
1351 | ||
1352 | /* | |
cdd6c482 IM |
1353 | * If this machine has limited events, check whether this |
1354 | * event_id could go on a limited event. | |
ab7ef2e5 | 1355 | */ |
0bbd0d4b | 1356 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1357 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1358 | flags |= PPMU_LIMITED_PMC_OK; |
1359 | } else if (ppmu->limited_pmc_event(ev)) { | |
1360 | /* | |
cdd6c482 | 1361 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1362 | * but we can't use a limited PMC; see if any |
1363 | * alternative goes on a normal PMC. | |
1364 | */ | |
1365 | ev = normal_pmc_alternative(ev, flags); | |
1366 | if (!ev) | |
b0a873eb | 1367 | return -EINVAL; |
ab7ef2e5 PM |
1368 | } |
1369 | } | |
1370 | ||
4574910e PM |
1371 | /* |
1372 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1373 | * other hardware events in the group. We assume the event |
4574910e PM |
1374 | * hasn't been linked into its leader's sibling list at this point. |
1375 | */ | |
1376 | n = 0; | |
cdd6c482 | 1377 | if (event->group_leader != event) { |
a8f90e90 | 1378 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1379 | ctrs, events, cflags); |
4574910e | 1380 | if (n < 0) |
b0a873eb | 1381 | return -EINVAL; |
4574910e | 1382 | } |
0475f9ea | 1383 | events[n] = ev; |
cdd6c482 | 1384 | ctrs[n] = event; |
ab7ef2e5 PM |
1385 | cflags[n] = flags; |
1386 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1387 | return -EINVAL; |
e51ee31e | 1388 | |
cdd6c482 | 1389 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1390 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1391 | |
1392 | if (has_branch_stack(event)) { | |
1393 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1394 | event->attr.branch_sample_type); | |
1395 | ||
1396 | if(cpuhw->bhrb_filter == -1) | |
1397 | return -EOPNOTSUPP; | |
1398 | } | |
1399 | ||
cdd6c482 | 1400 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1401 | if (err) |
b0a873eb | 1402 | return -EINVAL; |
4574910e | 1403 | |
cdd6c482 IM |
1404 | event->hw.config = events[n]; |
1405 | event->hw.event_base = cflags[n]; | |
1406 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1407 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1408 | |
1409 | /* | |
1410 | * See if we need to reserve the PMU. | |
cdd6c482 | 1411 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1412 | * mutex to ensure that we don't race with another task doing |
1413 | * reserve_pmc_hardware or release_pmc_hardware. | |
1414 | */ | |
1415 | err = 0; | |
cdd6c482 | 1416 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1417 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1418 | if (atomic_read(&num_events) == 0 && |
1419 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1420 | err = -EBUSY; |
1421 | else | |
cdd6c482 | 1422 | atomic_inc(&num_events); |
7595d63b PM |
1423 | mutex_unlock(&pmc_reserve_mutex); |
1424 | } | |
cdd6c482 | 1425 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1426 | |
b0a873eb | 1427 | return err; |
4574910e PM |
1428 | } |
1429 | ||
35edc2a5 PZ |
1430 | static int power_pmu_event_idx(struct perf_event *event) |
1431 | { | |
1432 | return event->hw.idx; | |
1433 | } | |
1434 | ||
1c53a270 SB |
1435 | ssize_t power_events_sysfs_show(struct device *dev, |
1436 | struct device_attribute *attr, char *page) | |
1437 | { | |
1438 | struct perf_pmu_events_attr *pmu_attr; | |
1439 | ||
1440 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1441 | ||
1442 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1443 | } | |
1444 | ||
b0a873eb | 1445 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1446 | .pmu_enable = power_pmu_enable, |
1447 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1448 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1449 | .add = power_pmu_add, |
1450 | .del = power_pmu_del, | |
1451 | .start = power_pmu_start, | |
1452 | .stop = power_pmu_stop, | |
b0a873eb | 1453 | .read = power_pmu_read, |
b0a873eb PZ |
1454 | .start_txn = power_pmu_start_txn, |
1455 | .cancel_txn = power_pmu_cancel_txn, | |
1456 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1457 | .event_idx = power_pmu_event_idx, |
3925f46b | 1458 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1459 | }; |
1460 | ||
3925f46b AK |
1461 | /* Processing BHRB entries */ |
1462 | void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) | |
1463 | { | |
1464 | u64 val; | |
1465 | u64 addr; | |
1466 | int r_index, u_index, target, pred; | |
1467 | ||
1468 | r_index = 0; | |
1469 | u_index = 0; | |
1470 | while (r_index < ppmu->bhrb_nr) { | |
1471 | /* Assembly read function */ | |
1472 | val = read_bhrb(r_index); | |
1473 | ||
1474 | /* Terminal marker: End of valid BHRB entries */ | |
1475 | if (val == 0) { | |
1476 | break; | |
1477 | } else { | |
1478 | /* BHRB field break up */ | |
1479 | addr = val & BHRB_EA; | |
1480 | pred = val & BHRB_PREDICTION; | |
1481 | target = val & BHRB_TARGET; | |
1482 | ||
1483 | /* Probable Missed entry: Not applicable for POWER8 */ | |
1484 | if ((addr == 0) && (target == 0) && (pred == 1)) { | |
1485 | r_index++; | |
1486 | continue; | |
1487 | } | |
1488 | ||
1489 | /* Real Missed entry: Power8 based missed entry */ | |
1490 | if ((addr == 0) && (target == 1) && (pred == 1)) { | |
1491 | r_index++; | |
1492 | continue; | |
1493 | } | |
1494 | ||
1495 | /* Reserved condition: Not a valid entry */ | |
1496 | if ((addr == 0) && (target == 1) && (pred == 0)) { | |
1497 | r_index++; | |
1498 | continue; | |
1499 | } | |
1500 | ||
1501 | /* Is a target address */ | |
1502 | if (val & BHRB_TARGET) { | |
1503 | /* First address cannot be a target address */ | |
1504 | if (r_index == 0) { | |
1505 | r_index++; | |
1506 | continue; | |
1507 | } | |
1508 | ||
1509 | /* Update target address for the previous entry */ | |
1510 | cpuhw->bhrb_entries[u_index - 1].to = addr; | |
1511 | cpuhw->bhrb_entries[u_index - 1].mispred = pred; | |
1512 | cpuhw->bhrb_entries[u_index - 1].predicted = ~pred; | |
1513 | ||
1514 | /* Dont increment u_index */ | |
1515 | r_index++; | |
1516 | } else { | |
1517 | /* Update address, flags for current entry */ | |
1518 | cpuhw->bhrb_entries[u_index].from = addr; | |
1519 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
1520 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
1521 | ||
1522 | /* Successfully popullated one entry */ | |
1523 | u_index++; | |
1524 | r_index++; | |
1525 | } | |
1526 | } | |
1527 | } | |
1528 | cpuhw->bhrb_stack.nr = u_index; | |
1529 | return; | |
1530 | } | |
e6878835 | 1531 | |
4574910e | 1532 | /* |
57c0c15b | 1533 | * A counter has overflowed; update its count and record |
4574910e PM |
1534 | * things if requested. Note that interrupts are hard-disabled |
1535 | * here so there is no possibility of being interrupted. | |
1536 | */ | |
cdd6c482 | 1537 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1538 | struct pt_regs *regs) |
4574910e | 1539 | { |
cdd6c482 | 1540 | u64 period = event->hw.sample_period; |
4574910e PM |
1541 | s64 prev, delta, left; |
1542 | int record = 0; | |
1543 | ||
a4eaf7f1 PZ |
1544 | if (event->hw.state & PERF_HES_STOPPED) { |
1545 | write_pmc(event->hw.idx, 0); | |
1546 | return; | |
1547 | } | |
1548 | ||
4574910e | 1549 | /* we don't have to worry about interrupts here */ |
e7850595 | 1550 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1551 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1552 | local64_add(delta, &event->count); |
4574910e PM |
1553 | |
1554 | /* | |
cdd6c482 | 1555 | * See if the total period for this event has expired, |
4574910e PM |
1556 | * and update for the next period. |
1557 | */ | |
1558 | val = 0; | |
e7850595 | 1559 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1560 | if (delta == 0) |
1561 | left++; | |
60db5e09 | 1562 | if (period) { |
4574910e | 1563 | if (left <= 0) { |
60db5e09 | 1564 | left += period; |
4574910e | 1565 | if (left <= 0) |
60db5e09 | 1566 | left = period; |
e6878835 | 1567 | record = siar_valid(regs); |
4bca770e | 1568 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1569 | } |
98fb1807 PM |
1570 | if (left < 0x80000000LL) |
1571 | val = 0x80000000LL - left; | |
4574910e | 1572 | } |
4574910e | 1573 | |
a4eaf7f1 PZ |
1574 | write_pmc(event->hw.idx, val); |
1575 | local64_set(&event->hw.prev_count, val); | |
1576 | local64_set(&event->hw.period_left, left); | |
1577 | perf_event_update_userpage(event); | |
1578 | ||
4574910e PM |
1579 | /* |
1580 | * Finally record data if requested. | |
1581 | */ | |
0bbd0d4b | 1582 | if (record) { |
dc1d628a PZ |
1583 | struct perf_sample_data data; |
1584 | ||
fd0d000b | 1585 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1586 | |
cdd6c482 | 1587 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1588 | perf_get_data_addr(regs, &data.addr); |
1589 | ||
3925f46b AK |
1590 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1591 | struct cpu_hw_events *cpuhw; | |
1592 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1593 | power_pmu_bhrb_read(cpuhw); | |
1594 | data.br_stack = &cpuhw->bhrb_stack; | |
1595 | } | |
1596 | ||
a8b0ca17 | 1597 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1598 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1599 | } |
1600 | } | |
1601 | ||
1602 | /* | |
1603 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1604 | * for an event_id. |
0bbd0d4b PM |
1605 | */ |
1606 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1607 | { | |
98fb1807 | 1608 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1609 | |
98fb1807 PM |
1610 | if (flags) |
1611 | return flags; | |
cdd6c482 IM |
1612 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1613 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1614 | } |
1615 | ||
1616 | /* | |
1617 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1618 | * for an event_id. |
0bbd0d4b PM |
1619 | */ |
1620 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1621 | { | |
33904054 | 1622 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1623 | |
e6878835 | 1624 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1625 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1626 | else if (use_siar) |
1627 | return 0; // no valid instruction pointer | |
75382aa7 | 1628 | else |
1ce447b9 | 1629 | return regs->nip; |
4574910e PM |
1630 | } |
1631 | ||
bc09c219 | 1632 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1633 | { |
0837e324 AB |
1634 | /* |
1635 | * Events on POWER7 can roll back if a speculative event doesn't | |
1636 | * eventually complete. Unfortunately in some rare cases they will | |
1637 | * raise a performance monitor exception. We need to catch this to | |
1638 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1639 | * cycles from overflow. | |
1640 | * | |
1641 | * We only do this if the first pass fails to find any overflowing | |
1642 | * PMCs because a user might set a period of less than 256 and we | |
1643 | * don't want to mistakenly reset them. | |
1644 | */ | |
bc09c219 MN |
1645 | if ((0x80000000 - val) <= 256) |
1646 | return true; | |
1647 | ||
1648 | return false; | |
1649 | } | |
1650 | ||
1651 | static bool pmc_overflow(unsigned long val) | |
1652 | { | |
1653 | if ((int)val < 0) | |
0837e324 AB |
1654 | return true; |
1655 | ||
1656 | return false; | |
1657 | } | |
1658 | ||
4574910e PM |
1659 | /* |
1660 | * Performance monitor interrupt stuff | |
1661 | */ | |
cdd6c482 | 1662 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 1663 | { |
bc09c219 | 1664 | int i, j; |
cdd6c482 IM |
1665 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1666 | struct perf_event *event; | |
bc09c219 MN |
1667 | unsigned long val[8]; |
1668 | int found, active; | |
ca8f2d7f PM |
1669 | int nmi; |
1670 | ||
ab7ef2e5 | 1671 | if (cpuhw->n_limited) |
a8f90e90 | 1672 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1673 | mfspr(SPRN_PMC6)); |
1674 | ||
98fb1807 | 1675 | perf_read_regs(regs); |
0bbd0d4b | 1676 | |
98fb1807 | 1677 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1678 | if (nmi) |
1679 | nmi_enter(); | |
1680 | else | |
1681 | irq_enter(); | |
4574910e | 1682 | |
bc09c219 MN |
1683 | /* Read all the PMCs since we'll need them a bunch of times */ |
1684 | for (i = 0; i < ppmu->n_counter; ++i) | |
1685 | val[i] = read_pmc(i + 1); | |
1686 | ||
1687 | /* Try to find what caused the IRQ */ | |
1688 | found = 0; | |
1689 | for (i = 0; i < ppmu->n_counter; ++i) { | |
1690 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 1691 | continue; |
bc09c219 MN |
1692 | if (is_limited_pmc(i + 1)) |
1693 | continue; /* these won't generate IRQs */ | |
1694 | /* | |
1695 | * We've found one that's overflowed. For active | |
1696 | * counters we need to log this. For inactive | |
1697 | * counters, we need to reset it anyway | |
1698 | */ | |
1699 | found = 1; | |
1700 | active = 0; | |
1701 | for (j = 0; j < cpuhw->n_events; ++j) { | |
1702 | event = cpuhw->event[j]; | |
1703 | if (event->hw.idx == (i + 1)) { | |
1704 | active = 1; | |
1705 | record_and_restart(event, val[i], regs); | |
1706 | break; | |
1707 | } | |
4574910e | 1708 | } |
bc09c219 MN |
1709 | if (!active) |
1710 | /* reset non active counters that have overflowed */ | |
1711 | write_pmc(i + 1, 0); | |
4574910e | 1712 | } |
bc09c219 MN |
1713 | if (!found && pvr_version_is(PVR_POWER7)) { |
1714 | /* check active counters for special buggy p7 overflow */ | |
1715 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1716 | event = cpuhw->event[i]; | |
1717 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1718 | continue; |
bc09c219 MN |
1719 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
1720 | /* event has overflowed in a buggy way*/ | |
1721 | found = 1; | |
1722 | record_and_restart(event, | |
1723 | val[event->hw.idx - 1], | |
1724 | regs); | |
1725 | } | |
4574910e PM |
1726 | } |
1727 | } | |
bc09c219 MN |
1728 | if ((!found) && printk_ratelimit()) |
1729 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); | |
4574910e PM |
1730 | |
1731 | /* | |
1732 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1733 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1734 | * and thus allow interrupts to occur again. |
cdd6c482 | 1735 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1736 | * we get back out of this interrupt. |
1737 | */ | |
ab7ef2e5 | 1738 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1739 | |
ca8f2d7f PM |
1740 | if (nmi) |
1741 | nmi_exit(); | |
1742 | else | |
db4fb5ac | 1743 | irq_exit(); |
4574910e PM |
1744 | } |
1745 | ||
3f6da390 | 1746 | static void power_pmu_setup(int cpu) |
01d0287f | 1747 | { |
cdd6c482 | 1748 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1749 | |
f36a1a13 PM |
1750 | if (!ppmu) |
1751 | return; | |
01d0287f PM |
1752 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1753 | cpuhw->mmcr[0] = MMCR0_FC; | |
1754 | } | |
1755 | ||
3f6da390 | 1756 | static int __cpuinit |
85cfabbc | 1757 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1758 | { |
1759 | unsigned int cpu = (long)hcpu; | |
1760 | ||
1761 | switch (action & ~CPU_TASKS_FROZEN) { | |
1762 | case CPU_UP_PREPARE: | |
1763 | power_pmu_setup(cpu); | |
1764 | break; | |
1765 | ||
1766 | default: | |
1767 | break; | |
1768 | } | |
1769 | ||
1770 | return NOTIFY_OK; | |
1771 | } | |
1772 | ||
77c2342a | 1773 | int __cpuinit register_power_pmu(struct power_pmu *pmu) |
4574910e | 1774 | { |
079b3c56 PM |
1775 | if (ppmu) |
1776 | return -EBUSY; /* something's already registered */ | |
1777 | ||
1778 | ppmu = pmu; | |
1779 | pr_info("%s performance monitor hardware support registered\n", | |
1780 | pmu->name); | |
d095cd46 | 1781 | |
1c53a270 SB |
1782 | power_pmu.attr_groups = ppmu->attr_groups; |
1783 | ||
98fb1807 | 1784 | #ifdef MSR_HV |
d095cd46 PM |
1785 | /* |
1786 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1787 | */ | |
1788 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1789 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1790 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1791 | |
2e80a82a | 1792 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1793 | perf_cpu_notifier(power_pmu_notifier); |
1794 | ||
4574910e PM |
1795 | return 0; |
1796 | } |