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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
16 | #include <asm/reg.h> | |
17 | #include <asm/pmc.h> | |
01d0287f | 18 | #include <asm/machdep.h> |
0475f9ea | 19 | #include <asm/firmware.h> |
0bbd0d4b | 20 | #include <asm/ptrace.h> |
4574910e | 21 | |
cdd6c482 IM |
22 | struct cpu_hw_events { |
23 | int n_events; | |
4574910e PM |
24 | int n_percpu; |
25 | int disabled; | |
26 | int n_added; | |
ab7ef2e5 PM |
27 | int n_limited; |
28 | u8 pmcs_enabled; | |
cdd6c482 IM |
29 | struct perf_event *event[MAX_HWEVENTS]; |
30 | u64 events[MAX_HWEVENTS]; | |
31 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 32 | unsigned long mmcr[3]; |
a8f90e90 PM |
33 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
34 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
35 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
36 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
37 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
38 | |
39 | unsigned int group_flag; | |
40 | int n_txn_start; | |
4574910e | 41 | }; |
cdd6c482 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
43 | |
44 | struct power_pmu *ppmu; | |
45 | ||
d095cd46 | 46 | /* |
57c0c15b | 47 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
48 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
49 | * hypervisor bit set in the MSR, or if we are running on a processor | |
50 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
51 | * then we need to use the FCHV bit to ignore kernel events. | |
52 | */ | |
cdd6c482 | 53 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 54 | |
98fb1807 PM |
55 | /* |
56 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
57 | * and a few other names are different. | |
58 | */ | |
59 | #ifdef CONFIG_PPC32 | |
60 | ||
61 | #define MMCR0_FCHV 0 | |
62 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
63 | ||
64 | #define SPRN_MMCRA SPRN_MMCR2 | |
65 | #define MMCRA_SAMPLE_ENABLE 0 | |
66 | ||
67 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
68 | { | |
69 | return 0; | |
70 | } | |
98fb1807 PM |
71 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
72 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
73 | { | |
74 | return 0; | |
75 | } | |
76 | static inline void perf_read_regs(struct pt_regs *regs) { } | |
77 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
78 | { | |
79 | return 0; | |
80 | } | |
81 | ||
82 | #endif /* CONFIG_PPC32 */ | |
83 | ||
84 | /* | |
85 | * Things that are specific to 64-bit implementations. | |
86 | */ | |
87 | #ifdef CONFIG_PPC64 | |
88 | ||
89 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
90 | { | |
91 | unsigned long mmcra = regs->dsisr; | |
92 | ||
93 | if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { | |
94 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; | |
95 | if (slot > 1) | |
96 | return 4 * (slot - 1); | |
97 | } | |
98 | return 0; | |
99 | } | |
100 | ||
98fb1807 PM |
101 | /* |
102 | * The user wants a data address recorded. | |
103 | * If we're not doing instruction sampling, give them the SDAR | |
104 | * (sampled data address). If we are doing instruction sampling, then | |
105 | * only give them the SDAR if it corresponds to the instruction | |
106 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC | |
107 | * bit in MMCRA. | |
108 | */ | |
109 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
110 | { | |
111 | unsigned long mmcra = regs->dsisr; | |
112 | unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? | |
113 | POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; | |
114 | ||
115 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | |
116 | *addrp = mfspr(SPRN_SDAR); | |
117 | } | |
118 | ||
1ce447b9 BH |
119 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
120 | { | |
121 | if (regs->msr & MSR_PR) | |
122 | return PERF_RECORD_MISC_USER; | |
123 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
124 | return PERF_RECORD_MISC_HYPERVISOR; | |
125 | return PERF_RECORD_MISC_KERNEL; | |
126 | } | |
127 | ||
98fb1807 PM |
128 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
129 | { | |
130 | unsigned long mmcra = regs->dsisr; | |
7abb840b MN |
131 | unsigned long sihv = MMCRA_SIHV; |
132 | unsigned long sipr = MMCRA_SIPR; | |
98fb1807 | 133 | |
1ce447b9 | 134 | /* Not a PMU interrupt: Make up flags from regs->msr */ |
98fb1807 | 135 | if (TRAP(regs) != 0xf00) |
1ce447b9 BH |
136 | return perf_flags_from_msr(regs); |
137 | ||
138 | /* | |
139 | * If we don't support continuous sampling and this | |
140 | * is not a marked event, same deal | |
141 | */ | |
142 | if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) && | |
143 | !(mmcra & MMCRA_SAMPLE_ENABLE)) | |
144 | return perf_flags_from_msr(regs); | |
145 | ||
146 | /* | |
147 | * If we don't have flags in MMCRA, rather than using | |
148 | * the MSR, we intuit the flags from the address in | |
149 | * SIAR which should give slightly more reliable | |
150 | * results | |
151 | */ | |
152 | if (ppmu->flags & PPMU_NO_SIPR) { | |
153 | unsigned long siar = mfspr(SPRN_SIAR); | |
154 | if (siar >= PAGE_OFFSET) | |
155 | return PERF_RECORD_MISC_KERNEL; | |
156 | return PERF_RECORD_MISC_USER; | |
157 | } | |
98fb1807 PM |
158 | |
159 | if (ppmu->flags & PPMU_ALT_SIPR) { | |
7abb840b MN |
160 | sihv = POWER6_MMCRA_SIHV; |
161 | sipr = POWER6_MMCRA_SIPR; | |
98fb1807 | 162 | } |
7abb840b MN |
163 | |
164 | /* PR has priority over HV, so order below is important */ | |
165 | if (mmcra & sipr) | |
166 | return PERF_RECORD_MISC_USER; | |
167 | if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 168 | return PERF_RECORD_MISC_HYPERVISOR; |
7abb840b | 169 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
170 | } |
171 | ||
172 | /* | |
173 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
174 | * on each interrupt. | |
175 | */ | |
176 | static inline void perf_read_regs(struct pt_regs *regs) | |
177 | { | |
178 | regs->dsisr = mfspr(SPRN_MMCRA); | |
179 | } | |
180 | ||
181 | /* | |
182 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
183 | * it as an NMI. | |
184 | */ | |
185 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
186 | { | |
187 | return !regs->softe; | |
188 | } | |
189 | ||
190 | #endif /* CONFIG_PPC64 */ | |
191 | ||
cdd6c482 | 192 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 193 | |
cdd6c482 | 194 | void perf_event_print_debug(void) |
4574910e PM |
195 | { |
196 | } | |
197 | ||
4574910e | 198 | /* |
57c0c15b | 199 | * Read one performance monitor counter (PMC). |
4574910e PM |
200 | */ |
201 | static unsigned long read_pmc(int idx) | |
202 | { | |
203 | unsigned long val; | |
204 | ||
205 | switch (idx) { | |
206 | case 1: | |
207 | val = mfspr(SPRN_PMC1); | |
208 | break; | |
209 | case 2: | |
210 | val = mfspr(SPRN_PMC2); | |
211 | break; | |
212 | case 3: | |
213 | val = mfspr(SPRN_PMC3); | |
214 | break; | |
215 | case 4: | |
216 | val = mfspr(SPRN_PMC4); | |
217 | break; | |
218 | case 5: | |
219 | val = mfspr(SPRN_PMC5); | |
220 | break; | |
221 | case 6: | |
222 | val = mfspr(SPRN_PMC6); | |
223 | break; | |
98fb1807 | 224 | #ifdef CONFIG_PPC64 |
4574910e PM |
225 | case 7: |
226 | val = mfspr(SPRN_PMC7); | |
227 | break; | |
228 | case 8: | |
229 | val = mfspr(SPRN_PMC8); | |
230 | break; | |
98fb1807 | 231 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
232 | default: |
233 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
234 | val = 0; | |
235 | } | |
236 | return val; | |
237 | } | |
238 | ||
239 | /* | |
240 | * Write one PMC. | |
241 | */ | |
242 | static void write_pmc(int idx, unsigned long val) | |
243 | { | |
244 | switch (idx) { | |
245 | case 1: | |
246 | mtspr(SPRN_PMC1, val); | |
247 | break; | |
248 | case 2: | |
249 | mtspr(SPRN_PMC2, val); | |
250 | break; | |
251 | case 3: | |
252 | mtspr(SPRN_PMC3, val); | |
253 | break; | |
254 | case 4: | |
255 | mtspr(SPRN_PMC4, val); | |
256 | break; | |
257 | case 5: | |
258 | mtspr(SPRN_PMC5, val); | |
259 | break; | |
260 | case 6: | |
261 | mtspr(SPRN_PMC6, val); | |
262 | break; | |
98fb1807 | 263 | #ifdef CONFIG_PPC64 |
4574910e PM |
264 | case 7: |
265 | mtspr(SPRN_PMC7, val); | |
266 | break; | |
267 | case 8: | |
268 | mtspr(SPRN_PMC8, val); | |
269 | break; | |
98fb1807 | 270 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
271 | default: |
272 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
273 | } | |
274 | } | |
275 | ||
276 | /* | |
277 | * Check if a set of events can all go on the PMU at once. | |
278 | * If they can't, this will look at alternative codes for the events | |
279 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 280 | * The feasible set is returned in event_id[]. |
4574910e | 281 | */ |
cdd6c482 IM |
282 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
283 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 284 | int n_ev) |
4574910e | 285 | { |
448d64f8 | 286 | unsigned long mask, value, nv; |
cdd6c482 IM |
287 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
288 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 289 | int i, j; |
448d64f8 PM |
290 | unsigned long addf = ppmu->add_fields; |
291 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 292 | |
a8f90e90 | 293 | if (n_ev > ppmu->n_counter) |
4574910e PM |
294 | return -1; |
295 | ||
296 | /* First see if the events will go on as-is */ | |
297 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 298 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
299 | && !ppmu->limited_pmc_event(event_id[i])) { |
300 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 301 | cpuhw->alternatives[i]); |
cdd6c482 | 302 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 303 | } |
cdd6c482 | 304 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 305 | &cpuhw->avalues[i][0])) |
4574910e | 306 | return -1; |
4574910e PM |
307 | } |
308 | value = mask = 0; | |
309 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
310 | nv = (value | cpuhw->avalues[i][0]) + |
311 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 312 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
313 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
314 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
315 | break; |
316 | value = nv; | |
e51ee31e | 317 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
318 | } |
319 | if (i == n_ev) | |
320 | return 0; /* all OK */ | |
321 | ||
322 | /* doesn't work, gather alternatives... */ | |
323 | if (!ppmu->get_alternatives) | |
324 | return -1; | |
325 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 326 | choice[i] = 0; |
cdd6c482 | 327 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 328 | cpuhw->alternatives[i]); |
4574910e | 329 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
330 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
331 | &cpuhw->amasks[i][j], | |
332 | &cpuhw->avalues[i][j]); | |
4574910e PM |
333 | } |
334 | ||
335 | /* enumerate all possibilities and see if any will work */ | |
336 | i = 0; | |
337 | j = -1; | |
338 | value = mask = nv = 0; | |
339 | while (i < n_ev) { | |
340 | if (j >= 0) { | |
341 | /* we're backtracking, restore context */ | |
342 | value = svalues[i]; | |
343 | mask = smasks[i]; | |
344 | j = choice[i]; | |
345 | } | |
346 | /* | |
cdd6c482 | 347 | * See if any alternative k for event_id i, |
4574910e PM |
348 | * where k > j, will satisfy the constraints. |
349 | */ | |
350 | while (++j < n_alt[i]) { | |
e51ee31e PM |
351 | nv = (value | cpuhw->avalues[i][j]) + |
352 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 353 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
354 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
355 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
356 | break; |
357 | } | |
358 | if (j >= n_alt[i]) { | |
359 | /* | |
360 | * No feasible alternative, backtrack | |
cdd6c482 | 361 | * to event_id i-1 and continue enumerating its |
4574910e PM |
362 | * alternatives from where we got up to. |
363 | */ | |
364 | if (--i < 0) | |
365 | return -1; | |
366 | } else { | |
367 | /* | |
cdd6c482 IM |
368 | * Found a feasible alternative for event_id i, |
369 | * remember where we got up to with this event_id, | |
370 | * go on to the next event_id, and start with | |
4574910e PM |
371 | * the first alternative for it. |
372 | */ | |
373 | choice[i] = j; | |
374 | svalues[i] = value; | |
375 | smasks[i] = mask; | |
376 | value = nv; | |
e51ee31e | 377 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
378 | ++i; |
379 | j = -1; | |
380 | } | |
381 | } | |
382 | ||
383 | /* OK, we have a feasible combination, tell the caller the solution */ | |
384 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 385 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
386 | return 0; |
387 | } | |
388 | ||
0475f9ea | 389 | /* |
cdd6c482 | 390 | * Check if newly-added events have consistent settings for |
0475f9ea | 391 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 392 | * added events. |
0475f9ea | 393 | */ |
cdd6c482 | 394 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 395 | int n_prev, int n_new) |
0475f9ea | 396 | { |
ab7ef2e5 PM |
397 | int eu = 0, ek = 0, eh = 0; |
398 | int i, n, first; | |
cdd6c482 | 399 | struct perf_event *event; |
0475f9ea PM |
400 | |
401 | n = n_prev + n_new; | |
402 | if (n <= 1) | |
403 | return 0; | |
404 | ||
ab7ef2e5 PM |
405 | first = 1; |
406 | for (i = 0; i < n; ++i) { | |
407 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
408 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
409 | continue; | |
410 | } | |
cdd6c482 | 411 | event = ctrs[i]; |
ab7ef2e5 | 412 | if (first) { |
cdd6c482 IM |
413 | eu = event->attr.exclude_user; |
414 | ek = event->attr.exclude_kernel; | |
415 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 416 | first = 0; |
cdd6c482 IM |
417 | } else if (event->attr.exclude_user != eu || |
418 | event->attr.exclude_kernel != ek || | |
419 | event->attr.exclude_hv != eh) { | |
0475f9ea | 420 | return -EAGAIN; |
ab7ef2e5 | 421 | } |
0475f9ea | 422 | } |
ab7ef2e5 PM |
423 | |
424 | if (eu || ek || eh) | |
425 | for (i = 0; i < n; ++i) | |
426 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
427 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
428 | ||
0475f9ea PM |
429 | return 0; |
430 | } | |
431 | ||
86c74ab3 EM |
432 | static u64 check_and_compute_delta(u64 prev, u64 val) |
433 | { | |
434 | u64 delta = (val - prev) & 0xfffffffful; | |
435 | ||
436 | /* | |
437 | * POWER7 can roll back counter values, if the new value is smaller | |
438 | * than the previous value it will cause the delta and the counter to | |
439 | * have bogus values unless we rolled a counter over. If a coutner is | |
440 | * rolled back, it will be smaller, but within 256, which is the maximum | |
441 | * number of events to rollback at once. If we dectect a rollback | |
442 | * return 0. This can lead to a small lack of precision in the | |
443 | * counters. | |
444 | */ | |
445 | if (prev > val && (prev - val) < 256) | |
446 | delta = 0; | |
447 | ||
448 | return delta; | |
449 | } | |
450 | ||
cdd6c482 | 451 | static void power_pmu_read(struct perf_event *event) |
4574910e | 452 | { |
98fb1807 | 453 | s64 val, delta, prev; |
4574910e | 454 | |
a4eaf7f1 PZ |
455 | if (event->hw.state & PERF_HES_STOPPED) |
456 | return; | |
457 | ||
cdd6c482 | 458 | if (!event->hw.idx) |
4574910e PM |
459 | return; |
460 | /* | |
461 | * Performance monitor interrupts come even when interrupts | |
462 | * are soft-disabled, as long as interrupts are hard-enabled. | |
463 | * Therefore we treat them like NMIs. | |
464 | */ | |
465 | do { | |
e7850595 | 466 | prev = local64_read(&event->hw.prev_count); |
4574910e | 467 | barrier(); |
cdd6c482 | 468 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
469 | delta = check_and_compute_delta(prev, val); |
470 | if (!delta) | |
471 | return; | |
e7850595 | 472 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 473 | |
e7850595 PZ |
474 | local64_add(delta, &event->count); |
475 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
476 | } |
477 | ||
ab7ef2e5 PM |
478 | /* |
479 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
480 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 481 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
482 | */ |
483 | static int is_limited_pmc(int pmcnum) | |
484 | { | |
0bbd0d4b PM |
485 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
486 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
487 | } |
488 | ||
a8f90e90 | 489 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
490 | unsigned long pmc5, unsigned long pmc6) |
491 | { | |
cdd6c482 | 492 | struct perf_event *event; |
ab7ef2e5 PM |
493 | u64 val, prev, delta; |
494 | int i; | |
495 | ||
496 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 497 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 498 | if (!event->hw.idx) |
ab7ef2e5 | 499 | continue; |
cdd6c482 | 500 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 501 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 502 | event->hw.idx = 0; |
86c74ab3 EM |
503 | delta = check_and_compute_delta(prev, val); |
504 | if (delta) | |
505 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
506 | } |
507 | } | |
508 | ||
a8f90e90 | 509 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
510 | unsigned long pmc5, unsigned long pmc6) |
511 | { | |
cdd6c482 | 512 | struct perf_event *event; |
86c74ab3 | 513 | u64 val, prev; |
ab7ef2e5 PM |
514 | int i; |
515 | ||
516 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 517 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
518 | event->hw.idx = cpuhw->limited_hwidx[i]; |
519 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
520 | prev = local64_read(&event->hw.prev_count); |
521 | if (check_and_compute_delta(prev, val)) | |
522 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 523 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
524 | } |
525 | } | |
526 | ||
527 | /* | |
cdd6c482 | 528 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 529 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
530 | * other events. We try to keep the values from the limited |
531 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 532 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
533 | * the limited events as small and consistent as possible. |
534 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
535 | * both, and always in the same order, to minimize variability, |
536 | * and do it inside the same asm that writes MMCR0. | |
537 | */ | |
cdd6c482 | 538 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
539 | { |
540 | unsigned long pmc5, pmc6; | |
541 | ||
542 | if (!cpuhw->n_limited) { | |
543 | mtspr(SPRN_MMCR0, mmcr0); | |
544 | return; | |
545 | } | |
546 | ||
547 | /* | |
548 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
549 | * To ensure we don't get a performance monitor interrupt |
550 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 551 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 552 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
553 | */ |
554 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
555 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
556 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
557 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
558 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
559 | ||
560 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 561 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 562 | else |
a8f90e90 | 563 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
564 | |
565 | /* | |
cdd6c482 | 566 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
567 | * enable bits, if necessary. |
568 | */ | |
569 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
570 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
571 | } |
572 | ||
4574910e | 573 | /* |
cdd6c482 IM |
574 | * Disable all events to prevent PMU interrupts and to allow |
575 | * events to be added or removed. | |
4574910e | 576 | */ |
a4eaf7f1 | 577 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 578 | { |
cdd6c482 | 579 | struct cpu_hw_events *cpuhw; |
4574910e PM |
580 | unsigned long flags; |
581 | ||
f36a1a13 PM |
582 | if (!ppmu) |
583 | return; | |
4574910e | 584 | local_irq_save(flags); |
cdd6c482 | 585 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 586 | |
448d64f8 | 587 | if (!cpuhw->disabled) { |
4574910e PM |
588 | cpuhw->disabled = 1; |
589 | cpuhw->n_added = 0; | |
590 | ||
01d0287f PM |
591 | /* |
592 | * Check if we ever enabled the PMU on this cpu. | |
593 | */ | |
594 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 595 | ppc_enable_pmcs(); |
01d0287f PM |
596 | cpuhw->pmcs_enabled = 1; |
597 | } | |
598 | ||
f708223d PM |
599 | /* |
600 | * Disable instruction sampling if it was enabled | |
601 | */ | |
602 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
603 | mtspr(SPRN_MMCRA, | |
604 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
605 | mb(); | |
606 | } | |
607 | ||
4574910e | 608 | /* |
57c0c15b | 609 | * Set the 'freeze counters' bit. |
4574910e | 610 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 611 | * executed and the PMU has frozen the events |
4574910e PM |
612 | * before we return. |
613 | */ | |
ab7ef2e5 | 614 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
615 | mb(); |
616 | } | |
617 | local_irq_restore(flags); | |
4574910e PM |
618 | } |
619 | ||
620 | /* | |
cdd6c482 IM |
621 | * Re-enable all events if disable == 0. |
622 | * If we were previously disabled and events were added, then | |
4574910e PM |
623 | * put the new config on the PMU. |
624 | */ | |
a4eaf7f1 | 625 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 626 | { |
cdd6c482 IM |
627 | struct perf_event *event; |
628 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
629 | unsigned long flags; |
630 | long i; | |
631 | unsigned long val; | |
632 | s64 left; | |
cdd6c482 | 633 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
634 | int n_lim; |
635 | int idx; | |
4574910e | 636 | |
f36a1a13 PM |
637 | if (!ppmu) |
638 | return; | |
4574910e | 639 | local_irq_save(flags); |
cdd6c482 | 640 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
641 | if (!cpuhw->disabled) { |
642 | local_irq_restore(flags); | |
643 | return; | |
644 | } | |
4574910e PM |
645 | cpuhw->disabled = 0; |
646 | ||
647 | /* | |
cdd6c482 | 648 | * If we didn't change anything, or only removed events, |
4574910e PM |
649 | * no need to recalculate MMCR* settings and reset the PMCs. |
650 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 651 | * (possibly updated for removal of events). |
4574910e PM |
652 | */ |
653 | if (!cpuhw->n_added) { | |
f708223d | 654 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 655 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 656 | if (cpuhw->n_events == 0) |
a6dbf93a | 657 | ppc_set_pmu_inuse(0); |
f708223d | 658 | goto out_enable; |
4574910e PM |
659 | } |
660 | ||
661 | /* | |
cdd6c482 | 662 | * Compute MMCR* values for the new set of events |
4574910e | 663 | */ |
cdd6c482 | 664 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
665 | cpuhw->mmcr)) { |
666 | /* shouldn't ever get here */ | |
667 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
668 | goto out; | |
669 | } | |
670 | ||
0475f9ea PM |
671 | /* |
672 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
673 | * attr.exclude_* bits for the first event. |
674 | * We have already checked that all events have the | |
675 | * same values for these bits as the first event. | |
0475f9ea | 676 | */ |
cdd6c482 IM |
677 | event = cpuhw->event[0]; |
678 | if (event->attr.exclude_user) | |
0475f9ea | 679 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
680 | if (event->attr.exclude_kernel) |
681 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
682 | if (event->attr.exclude_hv) | |
0475f9ea PM |
683 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
684 | ||
4574910e PM |
685 | /* |
686 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
687 | * bit set and set the hardware events to their initial values. |
688 | * Then unfreeze the events. | |
4574910e | 689 | */ |
a6dbf93a | 690 | ppc_set_pmu_inuse(1); |
f708223d | 691 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
692 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
693 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
694 | | MMCR0_FC); | |
695 | ||
696 | /* | |
cdd6c482 | 697 | * Read off any pre-existing events that need to move |
4574910e PM |
698 | * to another PMC. |
699 | */ | |
cdd6c482 IM |
700 | for (i = 0; i < cpuhw->n_events; ++i) { |
701 | event = cpuhw->event[i]; | |
702 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
703 | power_pmu_read(event); | |
704 | write_pmc(event->hw.idx, 0); | |
705 | event->hw.idx = 0; | |
4574910e PM |
706 | } |
707 | } | |
708 | ||
709 | /* | |
cdd6c482 | 710 | * Initialize the PMCs for all the new and moved events. |
4574910e | 711 | */ |
ab7ef2e5 | 712 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
713 | for (i = 0; i < cpuhw->n_events; ++i) { |
714 | event = cpuhw->event[i]; | |
715 | if (event->hw.idx) | |
4574910e | 716 | continue; |
ab7ef2e5 PM |
717 | idx = hwc_index[i] + 1; |
718 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 719 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
720 | cpuhw->limited_hwidx[n_lim] = idx; |
721 | ++n_lim; | |
722 | continue; | |
723 | } | |
4574910e | 724 | val = 0; |
cdd6c482 | 725 | if (event->hw.sample_period) { |
e7850595 | 726 | left = local64_read(&event->hw.period_left); |
4574910e PM |
727 | if (left < 0x80000000L) |
728 | val = 0x80000000L - left; | |
729 | } | |
e7850595 | 730 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 731 | event->hw.idx = idx; |
a4eaf7f1 PZ |
732 | if (event->hw.state & PERF_HES_STOPPED) |
733 | val = 0; | |
ab7ef2e5 | 734 | write_pmc(idx, val); |
cdd6c482 | 735 | perf_event_update_userpage(event); |
4574910e | 736 | } |
ab7ef2e5 | 737 | cpuhw->n_limited = n_lim; |
4574910e | 738 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
739 | |
740 | out_enable: | |
741 | mb(); | |
ab7ef2e5 | 742 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 743 | |
f708223d PM |
744 | /* |
745 | * Enable instruction sampling if necessary | |
746 | */ | |
747 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
748 | mb(); | |
749 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
750 | } | |
751 | ||
4574910e PM |
752 | out: |
753 | local_irq_restore(flags); | |
754 | } | |
755 | ||
cdd6c482 IM |
756 | static int collect_events(struct perf_event *group, int max_count, |
757 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 758 | unsigned int *flags) |
4574910e PM |
759 | { |
760 | int n = 0; | |
cdd6c482 | 761 | struct perf_event *event; |
4574910e | 762 | |
cdd6c482 | 763 | if (!is_software_event(group)) { |
4574910e PM |
764 | if (n >= max_count) |
765 | return -1; | |
766 | ctrs[n] = group; | |
cdd6c482 | 767 | flags[n] = group->hw.event_base; |
4574910e PM |
768 | events[n++] = group->hw.config; |
769 | } | |
a8f90e90 | 770 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
771 | if (!is_software_event(event) && |
772 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
773 | if (n >= max_count) |
774 | return -1; | |
cdd6c482 IM |
775 | ctrs[n] = event; |
776 | flags[n] = event->hw.event_base; | |
777 | events[n++] = event->hw.config; | |
4574910e PM |
778 | } |
779 | } | |
780 | return n; | |
781 | } | |
782 | ||
4574910e | 783 | /* |
cdd6c482 IM |
784 | * Add a event to the PMU. |
785 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 786 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
787 | * actual work of reconfiguring the PMU. |
788 | */ | |
a4eaf7f1 | 789 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 790 | { |
cdd6c482 | 791 | struct cpu_hw_events *cpuhw; |
4574910e | 792 | unsigned long flags; |
4574910e PM |
793 | int n0; |
794 | int ret = -EAGAIN; | |
795 | ||
796 | local_irq_save(flags); | |
33696fc0 | 797 | perf_pmu_disable(event->pmu); |
4574910e PM |
798 | |
799 | /* | |
cdd6c482 | 800 | * Add the event to the list (if there is room) |
4574910e PM |
801 | * and check whether the total set is still feasible. |
802 | */ | |
cdd6c482 IM |
803 | cpuhw = &__get_cpu_var(cpu_hw_events); |
804 | n0 = cpuhw->n_events; | |
a8f90e90 | 805 | if (n0 >= ppmu->n_counter) |
4574910e | 806 | goto out; |
cdd6c482 IM |
807 | cpuhw->event[n0] = event; |
808 | cpuhw->events[n0] = event->hw.config; | |
809 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 810 | |
a4eaf7f1 PZ |
811 | if (!(ef_flags & PERF_EF_START)) |
812 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
813 | ||
8e6d5573 LM |
814 | /* |
815 | * If group events scheduling transaction was started, | |
25985edc | 816 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
817 | * at commit time(->commit_txn) as a whole |
818 | */ | |
8d2cacbb | 819 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
820 | goto nocheck; |
821 | ||
cdd6c482 | 822 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 823 | goto out; |
e51ee31e | 824 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 825 | goto out; |
cdd6c482 | 826 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
827 | |
828 | nocheck: | |
cdd6c482 | 829 | ++cpuhw->n_events; |
4574910e PM |
830 | ++cpuhw->n_added; |
831 | ||
832 | ret = 0; | |
833 | out: | |
33696fc0 | 834 | perf_pmu_enable(event->pmu); |
4574910e PM |
835 | local_irq_restore(flags); |
836 | return ret; | |
837 | } | |
838 | ||
839 | /* | |
cdd6c482 | 840 | * Remove a event from the PMU. |
4574910e | 841 | */ |
a4eaf7f1 | 842 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 843 | { |
cdd6c482 | 844 | struct cpu_hw_events *cpuhw; |
4574910e | 845 | long i; |
4574910e PM |
846 | unsigned long flags; |
847 | ||
848 | local_irq_save(flags); | |
33696fc0 | 849 | perf_pmu_disable(event->pmu); |
4574910e | 850 | |
cdd6c482 IM |
851 | power_pmu_read(event); |
852 | ||
853 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
854 | for (i = 0; i < cpuhw->n_events; ++i) { | |
855 | if (event == cpuhw->event[i]) { | |
219a92a4 | 856 | while (++i < cpuhw->n_events) { |
cdd6c482 | 857 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
858 | cpuhw->events[i-1] = cpuhw->events[i]; |
859 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
860 | } | |
cdd6c482 IM |
861 | --cpuhw->n_events; |
862 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
863 | if (event->hw.idx) { | |
864 | write_pmc(event->hw.idx, 0); | |
865 | event->hw.idx = 0; | |
ab7ef2e5 | 866 | } |
cdd6c482 | 867 | perf_event_update_userpage(event); |
4574910e PM |
868 | break; |
869 | } | |
870 | } | |
ab7ef2e5 | 871 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 872 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
873 | break; |
874 | if (i < cpuhw->n_limited) { | |
875 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 876 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
877 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
878 | } | |
879 | --cpuhw->n_limited; | |
880 | } | |
cdd6c482 IM |
881 | if (cpuhw->n_events == 0) { |
882 | /* disable exceptions if no events are running */ | |
4574910e PM |
883 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
884 | } | |
885 | ||
33696fc0 | 886 | perf_pmu_enable(event->pmu); |
4574910e PM |
887 | local_irq_restore(flags); |
888 | } | |
889 | ||
8a7b8cb9 | 890 | /* |
a4eaf7f1 PZ |
891 | * POWER-PMU does not support disabling individual counters, hence |
892 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 893 | */ |
a4eaf7f1 PZ |
894 | |
895 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 896 | { |
8a7b8cb9 | 897 | unsigned long flags; |
a4eaf7f1 | 898 | s64 left; |
9a45a940 | 899 | unsigned long val; |
8a7b8cb9 | 900 | |
cdd6c482 | 901 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 902 | return; |
a4eaf7f1 PZ |
903 | |
904 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
905 | return; | |
906 | ||
907 | if (ef_flags & PERF_EF_RELOAD) | |
908 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
909 | ||
910 | local_irq_save(flags); | |
911 | perf_pmu_disable(event->pmu); | |
912 | ||
913 | event->hw.state = 0; | |
914 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
915 | |
916 | val = 0; | |
917 | if (left < 0x80000000L) | |
918 | val = 0x80000000L - left; | |
919 | ||
920 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
921 | |
922 | perf_event_update_userpage(event); | |
923 | perf_pmu_enable(event->pmu); | |
924 | local_irq_restore(flags); | |
925 | } | |
926 | ||
927 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
928 | { | |
929 | unsigned long flags; | |
930 | ||
931 | if (!event->hw.idx || !event->hw.sample_period) | |
932 | return; | |
933 | ||
934 | if (event->hw.state & PERF_HES_STOPPED) | |
935 | return; | |
936 | ||
8a7b8cb9 | 937 | local_irq_save(flags); |
33696fc0 | 938 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 939 | |
cdd6c482 | 940 | power_pmu_read(event); |
a4eaf7f1 PZ |
941 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
942 | write_pmc(event->hw.idx, 0); | |
943 | ||
cdd6c482 | 944 | perf_event_update_userpage(event); |
33696fc0 | 945 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
946 | local_irq_restore(flags); |
947 | } | |
948 | ||
8e6d5573 LM |
949 | /* |
950 | * Start group events scheduling transaction | |
951 | * Set the flag to make pmu::enable() not perform the | |
952 | * schedulability test, it will be performed at commit time | |
953 | */ | |
51b0fe39 | 954 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
955 | { |
956 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
957 | ||
33696fc0 | 958 | perf_pmu_disable(pmu); |
8d2cacbb | 959 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
960 | cpuhw->n_txn_start = cpuhw->n_events; |
961 | } | |
962 | ||
963 | /* | |
964 | * Stop group events scheduling transaction | |
965 | * Clear the flag and pmu::enable() will perform the | |
966 | * schedulability test. | |
967 | */ | |
51b0fe39 | 968 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
969 | { |
970 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
971 | ||
8d2cacbb | 972 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 973 | perf_pmu_enable(pmu); |
8e6d5573 LM |
974 | } |
975 | ||
976 | /* | |
977 | * Commit group events scheduling transaction | |
978 | * Perform the group schedulability test as a whole | |
979 | * Return 0 if success | |
980 | */ | |
51b0fe39 | 981 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
982 | { |
983 | struct cpu_hw_events *cpuhw; | |
984 | long i, n; | |
985 | ||
986 | if (!ppmu) | |
987 | return -EAGAIN; | |
988 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
989 | n = cpuhw->n_events; | |
990 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
991 | return -EAGAIN; | |
992 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
993 | if (i < 0) | |
994 | return -EAGAIN; | |
995 | ||
996 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
997 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
998 | ||
8d2cacbb | 999 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1000 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1001 | return 0; |
1002 | } | |
1003 | ||
ab7ef2e5 | 1004 | /* |
cdd6c482 | 1005 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1006 | * or 0 if not. |
cdd6c482 | 1007 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1008 | * that a limited PMC can count, doesn't require interrupts, and |
1009 | * doesn't exclude any processor mode. | |
1010 | */ | |
cdd6c482 | 1011 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1012 | unsigned int flags) |
1013 | { | |
1014 | int n; | |
ef923214 | 1015 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1016 | |
cdd6c482 IM |
1017 | if (event->attr.exclude_user |
1018 | || event->attr.exclude_kernel | |
1019 | || event->attr.exclude_hv | |
1020 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1021 | return 0; |
1022 | ||
1023 | if (ppmu->limited_pmc_event(ev)) | |
1024 | return 1; | |
1025 | ||
1026 | /* | |
cdd6c482 | 1027 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1028 | * see if any alternative code goes on a limited PMC. |
1029 | */ | |
1030 | if (!ppmu->get_alternatives) | |
1031 | return 0; | |
1032 | ||
1033 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1034 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1035 | |
ef923214 | 1036 | return n > 0; |
ab7ef2e5 PM |
1037 | } |
1038 | ||
1039 | /* | |
cdd6c482 IM |
1040 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1041 | * and return the event_id code, or 0 if there is no such alternative. | |
1042 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1043 | */ |
ef923214 | 1044 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1045 | { |
ef923214 | 1046 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1047 | int n; |
1048 | ||
1049 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1050 | n = ppmu->get_alternatives(ev, flags, alt); | |
1051 | if (!n) | |
1052 | return 0; | |
1053 | return alt[0]; | |
1054 | } | |
1055 | ||
cdd6c482 IM |
1056 | /* Number of perf_events counting hardware events */ |
1057 | static atomic_t num_events; | |
7595d63b PM |
1058 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1059 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1060 | ||
1061 | /* | |
cdd6c482 | 1062 | * Release the PMU if this is the last perf_event. |
7595d63b | 1063 | */ |
cdd6c482 | 1064 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1065 | { |
cdd6c482 | 1066 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1067 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1068 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1069 | release_pmc_hardware(); |
1070 | mutex_unlock(&pmc_reserve_mutex); | |
1071 | } | |
1072 | } | |
1073 | ||
106b506c | 1074 | /* |
cdd6c482 | 1075 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1076 | */ |
1077 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1078 | { | |
1079 | unsigned long type, op, result; | |
1080 | int ev; | |
1081 | ||
1082 | if (!ppmu->cache_events) | |
1083 | return -EINVAL; | |
1084 | ||
1085 | /* unpack config */ | |
1086 | type = config & 0xff; | |
1087 | op = (config >> 8) & 0xff; | |
1088 | result = (config >> 16) & 0xff; | |
1089 | ||
1090 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1091 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1092 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1093 | return -EINVAL; | |
1094 | ||
1095 | ev = (*ppmu->cache_events)[type][op][result]; | |
1096 | if (ev == 0) | |
1097 | return -EOPNOTSUPP; | |
1098 | if (ev == -1) | |
1099 | return -EINVAL; | |
1100 | *eventp = ev; | |
1101 | return 0; | |
1102 | } | |
1103 | ||
b0a873eb | 1104 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1105 | { |
ef923214 PM |
1106 | u64 ev; |
1107 | unsigned long flags; | |
cdd6c482 IM |
1108 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1109 | u64 events[MAX_HWEVENTS]; | |
1110 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1111 | int n; |
7595d63b | 1112 | int err; |
cdd6c482 | 1113 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1114 | |
1115 | if (!ppmu) | |
b0a873eb PZ |
1116 | return -ENOENT; |
1117 | ||
2481c5fa SE |
1118 | /* does not support taken branch sampling */ |
1119 | if (has_branch_stack(event)) | |
1120 | return -EOPNOTSUPP; | |
1121 | ||
cdd6c482 | 1122 | switch (event->attr.type) { |
106b506c | 1123 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1124 | ev = event->attr.config; |
9aaa131a | 1125 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1126 | return -EOPNOTSUPP; |
4574910e | 1127 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1128 | break; |
1129 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1130 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1131 | if (err) |
b0a873eb | 1132 | return err; |
106b506c PM |
1133 | break; |
1134 | case PERF_TYPE_RAW: | |
cdd6c482 | 1135 | ev = event->attr.config; |
106b506c | 1136 | break; |
90c8f954 | 1137 | default: |
b0a873eb | 1138 | return -ENOENT; |
4574910e | 1139 | } |
b0a873eb | 1140 | |
cdd6c482 IM |
1141 | event->hw.config_base = ev; |
1142 | event->hw.idx = 0; | |
4574910e | 1143 | |
0475f9ea PM |
1144 | /* |
1145 | * If we are not running on a hypervisor, force the | |
1146 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1147 | * the user set it to. |
0475f9ea PM |
1148 | */ |
1149 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1150 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1151 | |
1152 | /* | |
cdd6c482 | 1153 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1154 | * PM_RUN_* events interchangeably with their non RUN_* |
1155 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1156 | * XXX we should check if the task is an idle task. | |
1157 | */ | |
1158 | flags = 0; | |
57fa7214 | 1159 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1160 | flags |= PPMU_ONLY_COUNT_RUN; |
1161 | ||
1162 | /* | |
cdd6c482 IM |
1163 | * If this machine has limited events, check whether this |
1164 | * event_id could go on a limited event. | |
ab7ef2e5 | 1165 | */ |
0bbd0d4b | 1166 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1167 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1168 | flags |= PPMU_LIMITED_PMC_OK; |
1169 | } else if (ppmu->limited_pmc_event(ev)) { | |
1170 | /* | |
cdd6c482 | 1171 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1172 | * but we can't use a limited PMC; see if any |
1173 | * alternative goes on a normal PMC. | |
1174 | */ | |
1175 | ev = normal_pmc_alternative(ev, flags); | |
1176 | if (!ev) | |
b0a873eb | 1177 | return -EINVAL; |
ab7ef2e5 PM |
1178 | } |
1179 | } | |
1180 | ||
4574910e PM |
1181 | /* |
1182 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1183 | * other hardware events in the group. We assume the event |
4574910e PM |
1184 | * hasn't been linked into its leader's sibling list at this point. |
1185 | */ | |
1186 | n = 0; | |
cdd6c482 | 1187 | if (event->group_leader != event) { |
a8f90e90 | 1188 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1189 | ctrs, events, cflags); |
4574910e | 1190 | if (n < 0) |
b0a873eb | 1191 | return -EINVAL; |
4574910e | 1192 | } |
0475f9ea | 1193 | events[n] = ev; |
cdd6c482 | 1194 | ctrs[n] = event; |
ab7ef2e5 PM |
1195 | cflags[n] = flags; |
1196 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1197 | return -EINVAL; |
e51ee31e | 1198 | |
cdd6c482 | 1199 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1200 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
cdd6c482 | 1201 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1202 | if (err) |
b0a873eb | 1203 | return -EINVAL; |
4574910e | 1204 | |
cdd6c482 IM |
1205 | event->hw.config = events[n]; |
1206 | event->hw.event_base = cflags[n]; | |
1207 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1208 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1209 | |
1210 | /* | |
1211 | * See if we need to reserve the PMU. | |
cdd6c482 | 1212 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1213 | * mutex to ensure that we don't race with another task doing |
1214 | * reserve_pmc_hardware or release_pmc_hardware. | |
1215 | */ | |
1216 | err = 0; | |
cdd6c482 | 1217 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1218 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1219 | if (atomic_read(&num_events) == 0 && |
1220 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1221 | err = -EBUSY; |
1222 | else | |
cdd6c482 | 1223 | atomic_inc(&num_events); |
7595d63b PM |
1224 | mutex_unlock(&pmc_reserve_mutex); |
1225 | } | |
cdd6c482 | 1226 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1227 | |
b0a873eb | 1228 | return err; |
4574910e PM |
1229 | } |
1230 | ||
35edc2a5 PZ |
1231 | static int power_pmu_event_idx(struct perf_event *event) |
1232 | { | |
1233 | return event->hw.idx; | |
1234 | } | |
1235 | ||
b0a873eb | 1236 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1237 | .pmu_enable = power_pmu_enable, |
1238 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1239 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1240 | .add = power_pmu_add, |
1241 | .del = power_pmu_del, | |
1242 | .start = power_pmu_start, | |
1243 | .stop = power_pmu_stop, | |
b0a873eb | 1244 | .read = power_pmu_read, |
b0a873eb PZ |
1245 | .start_txn = power_pmu_start_txn, |
1246 | .cancel_txn = power_pmu_cancel_txn, | |
1247 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1248 | .event_idx = power_pmu_event_idx, |
b0a873eb PZ |
1249 | }; |
1250 | ||
4574910e | 1251 | /* |
57c0c15b | 1252 | * A counter has overflowed; update its count and record |
4574910e PM |
1253 | * things if requested. Note that interrupts are hard-disabled |
1254 | * here so there is no possibility of being interrupted. | |
1255 | */ | |
cdd6c482 | 1256 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1257 | struct pt_regs *regs) |
4574910e | 1258 | { |
cdd6c482 | 1259 | u64 period = event->hw.sample_period; |
4574910e PM |
1260 | s64 prev, delta, left; |
1261 | int record = 0; | |
1262 | ||
a4eaf7f1 PZ |
1263 | if (event->hw.state & PERF_HES_STOPPED) { |
1264 | write_pmc(event->hw.idx, 0); | |
1265 | return; | |
1266 | } | |
1267 | ||
4574910e | 1268 | /* we don't have to worry about interrupts here */ |
e7850595 | 1269 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1270 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1271 | local64_add(delta, &event->count); |
4574910e PM |
1272 | |
1273 | /* | |
cdd6c482 | 1274 | * See if the total period for this event has expired, |
4574910e PM |
1275 | * and update for the next period. |
1276 | */ | |
1277 | val = 0; | |
e7850595 | 1278 | left = local64_read(&event->hw.period_left) - delta; |
60db5e09 | 1279 | if (period) { |
4574910e | 1280 | if (left <= 0) { |
60db5e09 | 1281 | left += period; |
4574910e | 1282 | if (left <= 0) |
60db5e09 | 1283 | left = period; |
4574910e | 1284 | record = 1; |
4bca770e | 1285 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1286 | } |
98fb1807 PM |
1287 | if (left < 0x80000000LL) |
1288 | val = 0x80000000LL - left; | |
4574910e | 1289 | } |
4574910e | 1290 | |
a4eaf7f1 PZ |
1291 | write_pmc(event->hw.idx, val); |
1292 | local64_set(&event->hw.prev_count, val); | |
1293 | local64_set(&event->hw.period_left, left); | |
1294 | perf_event_update_userpage(event); | |
1295 | ||
4574910e PM |
1296 | /* |
1297 | * Finally record data if requested. | |
1298 | */ | |
0bbd0d4b | 1299 | if (record) { |
dc1d628a PZ |
1300 | struct perf_sample_data data; |
1301 | ||
fd0d000b | 1302 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1303 | |
cdd6c482 | 1304 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1305 | perf_get_data_addr(regs, &data.addr); |
1306 | ||
a8b0ca17 | 1307 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1308 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1309 | } |
1310 | } | |
1311 | ||
1312 | /* | |
1313 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1314 | * for an event_id. |
0bbd0d4b PM |
1315 | */ |
1316 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1317 | { | |
98fb1807 | 1318 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1319 | |
98fb1807 PM |
1320 | if (flags) |
1321 | return flags; | |
cdd6c482 IM |
1322 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1323 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1324 | } |
1325 | ||
1326 | /* | |
1327 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1328 | * for an event_id. |
0bbd0d4b PM |
1329 | */ |
1330 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1331 | { | |
1ce447b9 | 1332 | unsigned long mmcra = regs->dsisr; |
0bbd0d4b | 1333 | |
1ce447b9 | 1334 | /* Not a PMU interrupt */ |
0bbd0d4b | 1335 | if (TRAP(regs) != 0xf00) |
1ce447b9 BH |
1336 | return regs->nip; |
1337 | ||
1338 | /* Processor doesn't support sampling non marked events */ | |
1339 | if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) && | |
1340 | !(mmcra & MMCRA_SAMPLE_ENABLE)) | |
1341 | return regs->nip; | |
0bbd0d4b | 1342 | |
1ce447b9 | 1343 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
4574910e PM |
1344 | } |
1345 | ||
0837e324 AB |
1346 | static bool pmc_overflow(unsigned long val) |
1347 | { | |
1348 | if ((int)val < 0) | |
1349 | return true; | |
1350 | ||
1351 | /* | |
1352 | * Events on POWER7 can roll back if a speculative event doesn't | |
1353 | * eventually complete. Unfortunately in some rare cases they will | |
1354 | * raise a performance monitor exception. We need to catch this to | |
1355 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1356 | * cycles from overflow. | |
1357 | * | |
1358 | * We only do this if the first pass fails to find any overflowing | |
1359 | * PMCs because a user might set a period of less than 256 and we | |
1360 | * don't want to mistakenly reset them. | |
1361 | */ | |
1362 | if (__is_processor(PV_POWER7) && ((0x80000000 - val) <= 256)) | |
1363 | return true; | |
1364 | ||
1365 | return false; | |
1366 | } | |
1367 | ||
4574910e PM |
1368 | /* |
1369 | * Performance monitor interrupt stuff | |
1370 | */ | |
cdd6c482 | 1371 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e PM |
1372 | { |
1373 | int i; | |
cdd6c482 IM |
1374 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1375 | struct perf_event *event; | |
98fb1807 | 1376 | unsigned long val; |
925d519a | 1377 | int found = 0; |
ca8f2d7f PM |
1378 | int nmi; |
1379 | ||
ab7ef2e5 | 1380 | if (cpuhw->n_limited) |
a8f90e90 | 1381 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1382 | mfspr(SPRN_PMC6)); |
1383 | ||
98fb1807 | 1384 | perf_read_regs(regs); |
0bbd0d4b | 1385 | |
98fb1807 | 1386 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1387 | if (nmi) |
1388 | nmi_enter(); | |
1389 | else | |
1390 | irq_enter(); | |
4574910e | 1391 | |
cdd6c482 IM |
1392 | for (i = 0; i < cpuhw->n_events; ++i) { |
1393 | event = cpuhw->event[i]; | |
1394 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1395 | continue; |
cdd6c482 | 1396 | val = read_pmc(event->hw.idx); |
4574910e | 1397 | if ((int)val < 0) { |
cdd6c482 | 1398 | /* event has overflowed */ |
4574910e | 1399 | found = 1; |
a8b0ca17 | 1400 | record_and_restart(event, val, regs); |
4574910e PM |
1401 | } |
1402 | } | |
1403 | ||
1404 | /* | |
cdd6c482 IM |
1405 | * In case we didn't find and reset the event that caused |
1406 | * the interrupt, scan all events and reset any that are | |
4574910e PM |
1407 | * negative, to avoid getting continual interrupts. |
1408 | * Any that we processed in the previous loop will not be negative. | |
1409 | */ | |
1410 | if (!found) { | |
a8f90e90 | 1411 | for (i = 0; i < ppmu->n_counter; ++i) { |
ab7ef2e5 PM |
1412 | if (is_limited_pmc(i + 1)) |
1413 | continue; | |
4574910e | 1414 | val = read_pmc(i + 1); |
0837e324 | 1415 | if (pmc_overflow(val)) |
4574910e PM |
1416 | write_pmc(i + 1, 0); |
1417 | } | |
1418 | } | |
1419 | ||
1420 | /* | |
1421 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1422 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1423 | * and thus allow interrupts to occur again. |
cdd6c482 | 1424 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1425 | * we get back out of this interrupt. |
1426 | */ | |
ab7ef2e5 | 1427 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1428 | |
ca8f2d7f PM |
1429 | if (nmi) |
1430 | nmi_exit(); | |
1431 | else | |
db4fb5ac | 1432 | irq_exit(); |
4574910e PM |
1433 | } |
1434 | ||
3f6da390 | 1435 | static void power_pmu_setup(int cpu) |
01d0287f | 1436 | { |
cdd6c482 | 1437 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1438 | |
f36a1a13 PM |
1439 | if (!ppmu) |
1440 | return; | |
01d0287f PM |
1441 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1442 | cpuhw->mmcr[0] = MMCR0_FC; | |
1443 | } | |
1444 | ||
3f6da390 | 1445 | static int __cpuinit |
85cfabbc | 1446 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1447 | { |
1448 | unsigned int cpu = (long)hcpu; | |
1449 | ||
1450 | switch (action & ~CPU_TASKS_FROZEN) { | |
1451 | case CPU_UP_PREPARE: | |
1452 | power_pmu_setup(cpu); | |
1453 | break; | |
1454 | ||
1455 | default: | |
1456 | break; | |
1457 | } | |
1458 | ||
1459 | return NOTIFY_OK; | |
1460 | } | |
1461 | ||
77c2342a | 1462 | int __cpuinit register_power_pmu(struct power_pmu *pmu) |
4574910e | 1463 | { |
079b3c56 PM |
1464 | if (ppmu) |
1465 | return -EBUSY; /* something's already registered */ | |
1466 | ||
1467 | ppmu = pmu; | |
1468 | pr_info("%s performance monitor hardware support registered\n", | |
1469 | pmu->name); | |
d095cd46 | 1470 | |
98fb1807 | 1471 | #ifdef MSR_HV |
d095cd46 PM |
1472 | /* |
1473 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1474 | */ | |
1475 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1476 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1477 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1478 | |
2e80a82a | 1479 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
1480 | perf_cpu_notifier(power_pmu_notifier); |
1481 | ||
4574910e PM |
1482 | return 0; |
1483 | } |