[linux-2.6-block.git] / arch / powerpc / net / bpf_jit32.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * bpf_jit32.h: BPF JIT compiler for PPC
 *
 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
 *
 * Split from bpf_jit.h
 */
#ifndef _BPF_JIT32_H
#define _BPF_JIT32_H

#include <asm/asm-compat.h>
#include "bpf_jit.h"

#ifdef CONFIG_PPC64
#define BPF_PPC_STACK_R3_OFF	48
#define BPF_PPC_STACK_LOCALS	32
#define BPF_PPC_STACK_BASIC	(48+64)
#define BPF_PPC_STACK_SAVE	(18*8)
#define BPF_PPC_STACKFRAME	(BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
				 BPF_PPC_STACK_SAVE)
#define BPF_PPC_SLOWPATH_FRAME	(48+64)
#else
#define BPF_PPC_STACK_R3_OFF	24
#define BPF_PPC_STACK_LOCALS	16
#define BPF_PPC_STACK_BASIC	(24+32)
#define BPF_PPC_STACK_SAVE	(18*4)
#define BPF_PPC_STACKFRAME	(BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
				 BPF_PPC_STACK_SAVE)
#define BPF_PPC_SLOWPATH_FRAME	(24+32)
#endif

#define REG_SZ         (BITS_PER_LONG/8)

/*
 * Generated code register usage:
 *
 * As normal PPC C ABI (e.g. r1=sp, r2=TOC), with:
 *
 * skb		r3	(Entry parameter)
 * A register	r4
 * X register	r5
 * addr param	r6
 * r7-r10	scratch
 * skb->data	r14
 * skb headlen	r15	(skb->len - skb->data_len)
 * m[0]		r16
 * m[...]	...
 * m[15]	r31
 */
#define r_skb		3
#define r_ret		3
#define r_A		4
#define r_X		5
#define r_addr		6
#define r_scratch1	7
#define r_scratch2	8
#define r_D		14
#define r_HL		15
#define r_M		16

#ifndef __ASSEMBLY__

/*
 * Assembly helpers from arch/powerpc/net/bpf_jit.S:
 */
#define DECLARE_LOAD_FUNC(func)	\
	extern u8 func[], func##_negative_offset[], func##_positive_offset[]

DECLARE_LOAD_FUNC(sk_load_word);
DECLARE_LOAD_FUNC(sk_load_half);
DECLARE_LOAD_FUNC(sk_load_byte);
DECLARE_LOAD_FUNC(sk_load_byte_msh);

#define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i);   \
		else {	PPC_ADDIS(r, base, IMM_HA(i));			      \
			PPC_LBZ(r, r, IMM_L(i)); } } while(0)

#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i);     \
		else {	PPC_ADDIS(r, base, IMM_HA(i));			      \
			PPC_LD(r, r, IMM_L(i)); } } while(0)

#define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i);   \
		else {	PPC_ADDIS(r, base, IMM_HA(i));			      \
			PPC_LWZ(r, r, IMM_L(i)); } } while(0)

#define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i);   \
		else {	PPC_ADDIS(r, base, IMM_HA(i));			      \
			PPC_LHZ(r, r, IMM_L(i)); } } while(0)

#ifdef CONFIG_PPC64
#define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0)
#else
#define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0)
#endif

#ifdef CONFIG_SMP
#ifdef CONFIG_PPC64
#define PPC_BPF_LOAD_CPU(r)		\
	do { BUILD_BUG_ON(FIELD_SIZEOF(struct paca_struct, paca_index) != 2);	\
		PPC_LHZ_OFFS(r, 13, offsetof(struct paca_struct, paca_index));	\
	} while (0)
#else
#define PPC_BPF_LOAD_CPU(r)     \
	do { BUILD_BUG_ON(FIELD_SIZEOF(struct task_struct, cpu) != 4);		\
		PPC_LHZ_OFFS(r, 2, offsetof(struct task_struct, cpu));		\
	} while(0)
#endif
#else
#define PPC_BPF_LOAD_CPU(r) do { PPC_LI(r, 0); } while(0)
#endif

#define PPC_LHBRX_OFFS(r, base, i) \
		do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
#ifdef __LITTLE_ENDIAN__
#define PPC_NTOHS_OFFS(r, base, i)	PPC_LHBRX_OFFS(r, base, i)
#else
#define PPC_NTOHS_OFFS(r, base, i)	PPC_LHZ_OFFS(r, base, i)
#endif

#define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0)
#define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0)
#define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0)

#define SEEN_DATAREF 0x10000 /* might call external helpers */
#define SEEN_XREG    0x20000 /* X reg is used */
#define SEEN_MEM     0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary
			      * storage */
#define SEEN_MEM_MSK 0x0ffff

struct codegen_context {
	unsigned int seen;
	unsigned int idx;
	int pc_ret0; /* bpf index of first RET #0 instruction (if any) */
};

#endif

#endif
Commit	Line	Data
b886d83c	1	/* SPDX-License-Identifier: GPL-2.0-only */
6ac0ba5a NR	2	/*
	3	* bpf_jit32.h: BPF JIT compiler for PPC
	4	*
	5	* Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
	6	*
	7	* Split from bpf_jit.h
6ac0ba5a NR	8	*/
	9	#ifndef _BPF_JIT32_H
	10	#define _BPF_JIT32_H
	11
ec0c464c	12	#include <asm/asm-compat.h>
6ac0ba5a NR	13	#include "bpf_jit.h"
	14
	15	#ifdef CONFIG_PPC64
	16	#define BPF_PPC_STACK_R3_OFF 48
	17	#define BPF_PPC_STACK_LOCALS 32
	18	#define BPF_PPC_STACK_BASIC (48+64)
	19	#define BPF_PPC_STACK_SAVE (18*8)
	20	#define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
	21	BPF_PPC_STACK_SAVE)
	22	#define BPF_PPC_SLOWPATH_FRAME (48+64)
	23	#else
	24	#define BPF_PPC_STACK_R3_OFF 24
	25	#define BPF_PPC_STACK_LOCALS 16
	26	#define BPF_PPC_STACK_BASIC (24+32)
	27	#define BPF_PPC_STACK_SAVE (18*4)
	28	#define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
	29	BPF_PPC_STACK_SAVE)
	30	#define BPF_PPC_SLOWPATH_FRAME (24+32)
	31	#endif
	32
	33	#define REG_SZ (BITS_PER_LONG/8)
	34
	35	/*
	36	* Generated code register usage:
	37	*
	38	* As normal PPC C ABI (e.g. r1=sp, r2=TOC), with:
	39	*
	40	* skb r3 (Entry parameter)
	41	* A register r4
	42	* X register r5
	43	* addr param r6
	44	* r7-r10 scratch
	45	* skb->data r14
	46	* skb headlen r15 (skb->len - skb->data_len)
	47	* m[0] r16
	48	* m[...] ...
	49	* m[15] r31
	50	*/
	51	#define r_skb 3
	52	#define r_ret 3
	53	#define r_A 4
	54	#define r_X 5
	55	#define r_addr 6
	56	#define r_scratch1 7
	57	#define r_scratch2 8
	58	#define r_D 14
	59	#define r_HL 15
	60	#define r_M 16
	61
	62	#ifndef __ASSEMBLY__
	63
	64	/*
	65	* Assembly helpers from arch/powerpc/net/bpf_jit.S:
	66	*/
	67	#define DECLARE_LOAD_FUNC(func) \
	68	extern u8 func[], func##_negative_offset[], func##_positive_offset[]
	69
	70	DECLARE_LOAD_FUNC(sk_load_word);
	71	DECLARE_LOAD_FUNC(sk_load_half);
	72	DECLARE_LOAD_FUNC(sk_load_byte);
	73	DECLARE_LOAD_FUNC(sk_load_byte_msh);
	74
	75	#define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i); \
	76	else { PPC_ADDIS(r, base, IMM_HA(i)); \
77	PPC_LBZ(r, r, IMM_L(i)); } } while(0)
78
79	#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \
80	else { PPC_ADDIS(r, base, IMM_HA(i)); \
81	PPC_LD(r, r, IMM_L(i)); } } while(0)
82
83	#define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \
84	else { PPC_ADDIS(r, base, IMM_HA(i)); \
85	PPC_LWZ(r, r, IMM_L(i)); } } while(0)
86
87	#define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \
88	else { PPC_ADDIS(r, base, IMM_HA(i)); \
89	PPC_LHZ(r, r, IMM_L(i)); } } while(0)
90
91	#ifdef CONFIG_PPC64
92	#define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0)
93	#else
94	#define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0)
95	#endif
96
97	#ifdef CONFIG_SMP
98	#ifdef CONFIG_PPC64
99	#define PPC_BPF_LOAD_CPU(r) \
100	do { BUILD_BUG_ON(FIELD_SIZEOF(struct paca_struct, paca_index) != 2); \
101	PPC_LHZ_OFFS(r, 13, offsetof(struct paca_struct, paca_index)); \
102	} while (0)
103	#else
104	#define PPC_BPF_LOAD_CPU(r) \
ed1cd6de CL	105	do { BUILD_BUG_ON(FIELD_SIZEOF(struct task_struct, cpu) != 4); \
ed1cd6de CL	106	PPC_LHZ_OFFS(r, 2, offsetof(struct task_struct, cpu)); \
6ac0ba5a NR	107	} while(0)
	108	#endif
	109	#else
	110	#define PPC_BPF_LOAD_CPU(r) do { PPC_LI(r, 0); } while(0)
	111	#endif
	112
	113	#define PPC_LHBRX_OFFS(r, base, i) \
	114	do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
	115	#ifdef __LITTLE_ENDIAN__
	116	#define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i)
	117	#else
	118	#define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i)
	119	#endif
	120
86be36f6 NR	121	#define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0)
	122	#define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0)
	123	#define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0)
	124
6ac0ba5a NR	125	#define SEEN_DATAREF 0x10000 /* might call external helpers */
	126	#define SEEN_XREG 0x20000 /* X reg is used */
	127	#define SEEN_MEM 0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary
	128	* storage */
	129	#define SEEN_MEM_MSK 0x0ffff
	130
	131	struct codegen_context {
	132	unsigned int seen;
	133	unsigned int idx;
	134	int pc_ret0; /* bpf index of first RET #0 instruction (if any) */
	135	};
	136
	137	#endif
	138
	139	#endif