Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PowerPC64 SLB support. | |
3 | * | |
4 | * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM | |
5cdcd9d6 | 5 | * Based on earlier code written by: |
1da177e4 LT |
6 | * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com |
7 | * Copyright (c) 2001 Dave Engebretsen | |
8 | * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <asm/pgtable.h> |
18 | #include <asm/mmu.h> | |
19 | #include <asm/mmu_context.h> | |
20 | #include <asm/paca.h> | |
21 | #include <asm/cputable.h> | |
3c726f8d | 22 | #include <asm/cacheflush.h> |
2f6093c8 MN |
23 | #include <asm/smp.h> |
24 | #include <linux/compiler.h> | |
f384796c | 25 | #include <linux/context_tracking.h> |
589ee628 IM |
26 | #include <linux/mm_types.h> |
27 | ||
aa39be09 | 28 | #include <asm/udbg.h> |
b68a70c4 | 29 | #include <asm/code-patching.h> |
3c726f8d | 30 | |
1d15010c AK |
31 | enum slb_index { |
32 | LINEAR_INDEX = 0, /* Kernel linear map (0xc000000000000000) */ | |
33 | VMALLOC_INDEX = 1, /* Kernel virtual map (0xd000000000000000) */ | |
34 | KSTACK_INDEX = 2, /* Kernel stack map */ | |
35 | }; | |
1da177e4 | 36 | |
fd88b945 | 37 | extern void slb_allocate(unsigned long ea); |
1da177e4 | 38 | |
3b575064 PM |
39 | #define slb_esid_mask(ssize) \ |
40 | (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T) | |
41 | ||
1189be65 | 42 | static inline unsigned long mk_esid_data(unsigned long ea, int ssize, |
1d15010c | 43 | enum slb_index index) |
1da177e4 | 44 | { |
1d15010c | 45 | return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index; |
1da177e4 LT |
46 | } |
47 | ||
1189be65 PM |
48 | static inline unsigned long mk_vsid_data(unsigned long ea, int ssize, |
49 | unsigned long flags) | |
1da177e4 | 50 | { |
1189be65 PM |
51 | return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags | |
52 | ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT); | |
1da177e4 LT |
53 | } |
54 | ||
1189be65 | 55 | static inline void slb_shadow_update(unsigned long ea, int ssize, |
67439b76 | 56 | unsigned long flags, |
1d15010c | 57 | enum slb_index index) |
1da177e4 | 58 | { |
26cd835e ME |
59 | struct slb_shadow *p = get_slb_shadow(); |
60 | ||
2f6093c8 MN |
61 | /* |
62 | * Clear the ESID first so the entry is not valid while we are | |
00efee7d MN |
63 | * updating it. No write barriers are needed here, provided |
64 | * we only update the current CPU's SLB shadow buffer. | |
2f6093c8 | 65 | */ |
26cd835e ME |
66 | p->save_area[index].esid = 0; |
67 | p->save_area[index].vsid = cpu_to_be64(mk_vsid_data(ea, ssize, flags)); | |
68 | p->save_area[index].esid = cpu_to_be64(mk_esid_data(ea, ssize, index)); | |
2f6093c8 MN |
69 | } |
70 | ||
1d15010c | 71 | static inline void slb_shadow_clear(enum slb_index index) |
2f6093c8 | 72 | { |
1d15010c | 73 | get_slb_shadow()->save_area[index].esid = 0; |
1da177e4 LT |
74 | } |
75 | ||
1189be65 PM |
76 | static inline void create_shadowed_slbe(unsigned long ea, int ssize, |
77 | unsigned long flags, | |
1d15010c | 78 | enum slb_index index) |
175587cc PM |
79 | { |
80 | /* | |
81 | * Updating the shadow buffer before writing the SLB ensures | |
82 | * we don't get a stale entry here if we get preempted by PHYP | |
83 | * between these two statements. | |
84 | */ | |
1d15010c | 85 | slb_shadow_update(ea, ssize, flags, index); |
175587cc PM |
86 | |
87 | asm volatile("slbmte %0,%1" : | |
1189be65 | 88 | : "r" (mk_vsid_data(ea, ssize, flags)), |
1d15010c | 89 | "r" (mk_esid_data(ea, ssize, index)) |
175587cc PM |
90 | : "memory" ); |
91 | } | |
92 | ||
9c1e1052 | 93 | static void __slb_flush_and_rebolt(void) |
1da177e4 LT |
94 | { |
95 | /* If you change this make sure you change SLB_NUM_BOLTED | |
d8d164a9 | 96 | * and PR KVM appropriately too. */ |
bf72aeba | 97 | unsigned long linear_llp, vmalloc_llp, lflags, vflags; |
1189be65 | 98 | unsigned long ksp_esid_data, ksp_vsid_data; |
1da177e4 | 99 | |
3c726f8d | 100 | linear_llp = mmu_psize_defs[mmu_linear_psize].sllp; |
bf72aeba | 101 | vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp; |
3c726f8d | 102 | lflags = SLB_VSID_KERNEL | linear_llp; |
bf72aeba | 103 | vflags = SLB_VSID_KERNEL | vmalloc_llp; |
1da177e4 | 104 | |
1d15010c | 105 | ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, KSTACK_INDEX); |
1189be65 | 106 | if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) { |
1da177e4 | 107 | ksp_esid_data &= ~SLB_ESID_V; |
1189be65 | 108 | ksp_vsid_data = 0; |
1d15010c | 109 | slb_shadow_clear(KSTACK_INDEX); |
edd0622b PM |
110 | } else { |
111 | /* Update stack entry; others don't change */ | |
1d15010c | 112 | slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, KSTACK_INDEX); |
7ffcf8ec | 113 | ksp_vsid_data = |
1d15010c | 114 | be64_to_cpu(get_slb_shadow()->save_area[KSTACK_INDEX].vsid); |
edd0622b | 115 | } |
2f6093c8 | 116 | |
1da177e4 LT |
117 | /* We need to do this all in asm, so we're sure we don't touch |
118 | * the stack between the slbia and rebolting it. */ | |
119 | asm volatile("isync\n" | |
120 | "slbia\n" | |
121 | /* Slot 1 - first VMALLOC segment */ | |
122 | "slbmte %0,%1\n" | |
123 | /* Slot 2 - kernel stack */ | |
124 | "slbmte %2,%3\n" | |
125 | "isync" | |
1189be65 | 126 | :: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)), |
5f812261 | 127 | "r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, VMALLOC_INDEX)), |
1189be65 | 128 | "r"(ksp_vsid_data), |
1da177e4 LT |
129 | "r"(ksp_esid_data) |
130 | : "memory"); | |
131 | } | |
132 | ||
9c1e1052 PM |
133 | void slb_flush_and_rebolt(void) |
134 | { | |
135 | ||
136 | WARN_ON(!irqs_disabled()); | |
137 | ||
138 | /* | |
139 | * We can't take a PMU exception in the following code, so hard | |
140 | * disable interrupts. | |
141 | */ | |
142 | hard_irq_disable(); | |
143 | ||
144 | __slb_flush_and_rebolt(); | |
145 | get_paca()->slb_cache_ptr = 0; | |
146 | } | |
147 | ||
67439b76 MN |
148 | void slb_vmalloc_update(void) |
149 | { | |
150 | unsigned long vflags; | |
151 | ||
152 | vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1d15010c | 153 | slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX); |
67439b76 MN |
154 | slb_flush_and_rebolt(); |
155 | } | |
156 | ||
465ccab9 | 157 | /* Helper function to compare esids. There are four cases to handle. |
158 | * 1. The system is not 1T segment size capable. Use the GET_ESID compare. | |
159 | * 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare. | |
160 | * 3. The system is 1T capable, only one of the two addresses is > 1T. This is not a match. | |
161 | * 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare. | |
162 | */ | |
163 | static inline int esids_match(unsigned long addr1, unsigned long addr2) | |
164 | { | |
165 | int esid_1t_count; | |
166 | ||
167 | /* System is not 1T segment size capable. */ | |
44ae3ab3 | 168 | if (!mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
465ccab9 | 169 | return (GET_ESID(addr1) == GET_ESID(addr2)); |
170 | ||
171 | esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) + | |
172 | ((addr2 >> SID_SHIFT_1T) != 0)); | |
173 | ||
174 | /* both addresses are < 1T */ | |
175 | if (esid_1t_count == 0) | |
176 | return (GET_ESID(addr1) == GET_ESID(addr2)); | |
177 | ||
178 | /* One address < 1T, the other > 1T. Not a match */ | |
179 | if (esid_1t_count == 1) | |
180 | return 0; | |
181 | ||
182 | /* Both addresses are > 1T. */ | |
183 | return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2)); | |
184 | } | |
185 | ||
1da177e4 LT |
186 | /* Flush all user entries from the segment table of the current processor. */ |
187 | void switch_slb(struct task_struct *tsk, struct mm_struct *mm) | |
188 | { | |
9c1e1052 | 189 | unsigned long offset; |
1189be65 | 190 | unsigned long slbie_data = 0; |
1da177e4 LT |
191 | unsigned long pc = KSTK_EIP(tsk); |
192 | unsigned long stack = KSTK_ESP(tsk); | |
de4376c2 | 193 | unsigned long exec_base; |
1da177e4 | 194 | |
9c1e1052 PM |
195 | /* |
196 | * We need interrupts hard-disabled here, not just soft-disabled, | |
197 | * so that a PMU interrupt can't occur, which might try to access | |
198 | * user memory (to get a stack trace) and possible cause an SLB miss | |
199 | * which would update the slb_cache/slb_cache_ptr fields in the PACA. | |
200 | */ | |
201 | hard_irq_disable(); | |
202 | offset = get_paca()->slb_cache_ptr; | |
44ae3ab3 | 203 | if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) && |
f66bce5e | 204 | offset <= SLB_CACHE_ENTRIES) { |
1da177e4 LT |
205 | int i; |
206 | asm volatile("isync" : : : "memory"); | |
207 | for (i = 0; i < offset; i++) { | |
1189be65 PM |
208 | slbie_data = (unsigned long)get_paca()->slb_cache[i] |
209 | << SID_SHIFT; /* EA */ | |
210 | slbie_data |= user_segment_size(slbie_data) | |
211 | << SLBIE_SSIZE_SHIFT; | |
212 | slbie_data |= SLBIE_C; /* C set for user addresses */ | |
213 | asm volatile("slbie %0" : : "r" (slbie_data)); | |
1da177e4 LT |
214 | } |
215 | asm volatile("isync" : : : "memory"); | |
216 | } else { | |
9c1e1052 | 217 | __slb_flush_and_rebolt(); |
1da177e4 LT |
218 | } |
219 | ||
220 | /* Workaround POWER5 < DD2.1 issue */ | |
221 | if (offset == 1 || offset > SLB_CACHE_ENTRIES) | |
1189be65 | 222 | asm volatile("slbie %0" : : "r" (slbie_data)); |
1da177e4 LT |
223 | |
224 | get_paca()->slb_cache_ptr = 0; | |
52b1e665 | 225 | copy_mm_to_paca(mm); |
1da177e4 LT |
226 | |
227 | /* | |
228 | * preload some userspace segments into the SLB. | |
de4376c2 AB |
229 | * Almost all 32 and 64bit PowerPC executables are linked at |
230 | * 0x10000000 so it makes sense to preload this segment. | |
1da177e4 | 231 | */ |
de4376c2 | 232 | exec_base = 0x10000000; |
1da177e4 | 233 | |
5eb9bac0 | 234 | if (is_kernel_addr(pc) || is_kernel_addr(stack) || |
de4376c2 | 235 | is_kernel_addr(exec_base)) |
1da177e4 LT |
236 | return; |
237 | ||
5eb9bac0 | 238 | slb_allocate(pc); |
1da177e4 | 239 | |
5eb9bac0 AB |
240 | if (!esids_match(pc, stack)) |
241 | slb_allocate(stack); | |
1da177e4 | 242 | |
de4376c2 AB |
243 | if (!esids_match(pc, exec_base) && |
244 | !esids_match(stack, exec_base)) | |
245 | slb_allocate(exec_base); | |
1da177e4 LT |
246 | } |
247 | ||
3c726f8d BH |
248 | static inline void patch_slb_encoding(unsigned int *insn_addr, |
249 | unsigned int immed) | |
250 | { | |
79d0be74 AK |
251 | |
252 | /* | |
253 | * This function patches either an li or a cmpldi instruction with | |
254 | * a new immediate value. This relies on the fact that both li | |
255 | * (which is actually addi) and cmpldi both take a 16-bit immediate | |
256 | * value, and it is situated in the same location in the instruction, | |
257 | * ie. bits 16-31 (Big endian bit order) or the lower 16 bits. | |
258 | * The signedness of the immediate operand differs between the two | |
259 | * instructions however this code is only ever patching a small value, | |
260 | * much less than 1 << 15, so we can get away with it. | |
261 | * To patch the value we read the existing instruction, clear the | |
262 | * immediate value, and or in our new value, then write the instruction | |
263 | * back. | |
264 | */ | |
265 | unsigned int insn = (*insn_addr & 0xffff0000) | immed; | |
b68a70c4 | 266 | patch_instruction(insn_addr, insn); |
3c726f8d BH |
267 | } |
268 | ||
b86206e4 AB |
269 | extern u32 slb_miss_kernel_load_linear[]; |
270 | extern u32 slb_miss_kernel_load_io[]; | |
271 | extern u32 slb_compare_rr_to_size[]; | |
272 | extern u32 slb_miss_kernel_load_vmemmap[]; | |
273 | ||
46db2f86 BK |
274 | void slb_set_size(u16 size) |
275 | { | |
46db2f86 BK |
276 | if (mmu_slb_size == size) |
277 | return; | |
278 | ||
279 | mmu_slb_size = size; | |
280 | patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size); | |
281 | } | |
282 | ||
1da177e4 LT |
283 | void slb_initialize(void) |
284 | { | |
bf72aeba | 285 | unsigned long linear_llp, vmalloc_llp, io_llp; |
56291e19 | 286 | unsigned long lflags, vflags; |
3c726f8d | 287 | static int slb_encoding_inited; |
cec08e7a | 288 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
cec08e7a BH |
289 | unsigned long vmemmap_llp; |
290 | #endif | |
3c726f8d BH |
291 | |
292 | /* Prepare our SLB miss handler based on our page size */ | |
293 | linear_llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
bf72aeba PM |
294 | io_llp = mmu_psize_defs[mmu_io_psize].sllp; |
295 | vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
296 | get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp; | |
cec08e7a BH |
297 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
298 | vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp; | |
299 | #endif | |
3c726f8d BH |
300 | if (!slb_encoding_inited) { |
301 | slb_encoding_inited = 1; | |
302 | patch_slb_encoding(slb_miss_kernel_load_linear, | |
303 | SLB_VSID_KERNEL | linear_llp); | |
bf72aeba PM |
304 | patch_slb_encoding(slb_miss_kernel_load_io, |
305 | SLB_VSID_KERNEL | io_llp); | |
584f8b71 MN |
306 | patch_slb_encoding(slb_compare_rr_to_size, |
307 | mmu_slb_size); | |
3c726f8d | 308 | |
651e2dd2 ME |
309 | pr_devel("SLB: linear LLP = %04lx\n", linear_llp); |
310 | pr_devel("SLB: io LLP = %04lx\n", io_llp); | |
cec08e7a BH |
311 | |
312 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
313 | patch_slb_encoding(slb_miss_kernel_load_vmemmap, | |
314 | SLB_VSID_KERNEL | vmemmap_llp); | |
651e2dd2 | 315 | pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp); |
cec08e7a | 316 | #endif |
3c726f8d BH |
317 | } |
318 | ||
56291e19 SR |
319 | get_paca()->stab_rr = SLB_NUM_BOLTED; |
320 | ||
3c726f8d | 321 | lflags = SLB_VSID_KERNEL | linear_llp; |
bf72aeba | 322 | vflags = SLB_VSID_KERNEL | vmalloc_llp; |
1da177e4 | 323 | |
2be682af | 324 | /* Invalidate the entire SLB (even entry 0) & all the ERATS */ |
175587cc PM |
325 | asm volatile("isync":::"memory"); |
326 | asm volatile("slbmte %0,%0"::"r" (0) : "memory"); | |
327 | asm volatile("isync; slbia; isync":::"memory"); | |
1d15010c AK |
328 | create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX); |
329 | create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX); | |
175587cc | 330 | |
3b575064 PM |
331 | /* For the boot cpu, we're running on the stack in init_thread_union, |
332 | * which is in the first segment of the linear mapping, and also | |
333 | * get_paca()->kstack hasn't been initialized yet. | |
334 | * For secondary cpus, we need to bolt the kernel stack entry now. | |
335 | */ | |
1d15010c | 336 | slb_shadow_clear(KSTACK_INDEX); |
3b575064 PM |
337 | if (raw_smp_processor_id() != boot_cpuid && |
338 | (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET) | |
339 | create_shadowed_slbe(get_paca()->kstack, | |
1d15010c | 340 | mmu_kernel_ssize, lflags, KSTACK_INDEX); |
dfbe0d3b | 341 | |
175587cc | 342 | asm volatile("isync":::"memory"); |
1da177e4 | 343 | } |
f384796c AK |
344 | |
345 | static void insert_slb_entry(unsigned long vsid, unsigned long ea, | |
346 | int bpsize, int ssize) | |
347 | { | |
348 | unsigned long flags, vsid_data, esid_data; | |
349 | enum slb_index index; | |
350 | int slb_cache_index; | |
351 | ||
352 | /* | |
353 | * We are irq disabled, hence should be safe to access PACA. | |
354 | */ | |
355 | index = get_paca()->stab_rr; | |
356 | ||
357 | /* | |
358 | * simple round-robin replacement of slb starting at SLB_NUM_BOLTED. | |
359 | */ | |
360 | if (index < (mmu_slb_size - 1)) | |
361 | index++; | |
362 | else | |
363 | index = SLB_NUM_BOLTED; | |
364 | ||
365 | get_paca()->stab_rr = index; | |
366 | ||
367 | flags = SLB_VSID_USER | mmu_psize_defs[bpsize].sllp; | |
368 | vsid_data = (vsid << slb_vsid_shift(ssize)) | flags | | |
369 | ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT); | |
370 | esid_data = mk_esid_data(ea, ssize, index); | |
371 | ||
372 | asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data) | |
373 | : "memory"); | |
374 | ||
375 | /* | |
376 | * Now update slb cache entries | |
377 | */ | |
378 | slb_cache_index = get_paca()->slb_cache_ptr; | |
379 | if (slb_cache_index < SLB_CACHE_ENTRIES) { | |
380 | /* | |
381 | * We have space in slb cache for optimized switch_slb(). | |
382 | * Top 36 bits from esid_data as per ISA | |
383 | */ | |
384 | get_paca()->slb_cache[slb_cache_index++] = esid_data >> 28; | |
385 | get_paca()->slb_cache_ptr++; | |
386 | } else { | |
387 | /* | |
388 | * Our cache is full and the current cache content strictly | |
389 | * doesn't indicate the active SLB conents. Bump the ptr | |
390 | * so that switch_slb() will ignore the cache. | |
391 | */ | |
392 | get_paca()->slb_cache_ptr = SLB_CACHE_ENTRIES + 1; | |
393 | } | |
394 | } | |
395 | ||
396 | static void handle_multi_context_slb_miss(int context_id, unsigned long ea) | |
397 | { | |
398 | struct mm_struct *mm = current->mm; | |
399 | unsigned long vsid; | |
400 | int bpsize; | |
401 | ||
402 | /* | |
403 | * We are always above 1TB, hence use high user segment size. | |
404 | */ | |
405 | vsid = get_vsid(context_id, ea, mmu_highuser_ssize); | |
406 | bpsize = get_slice_psize(mm, ea); | |
407 | insert_slb_entry(vsid, ea, bpsize, mmu_highuser_ssize); | |
408 | } | |
409 | ||
410 | void slb_miss_large_addr(struct pt_regs *regs) | |
411 | { | |
412 | enum ctx_state prev_state = exception_enter(); | |
413 | unsigned long ea = regs->dar; | |
414 | int context; | |
415 | ||
416 | if (REGION_ID(ea) != USER_REGION_ID) | |
417 | goto slb_bad_addr; | |
418 | ||
419 | /* | |
420 | * Are we beyound what the page table layout supports ? | |
421 | */ | |
422 | if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE) | |
423 | goto slb_bad_addr; | |
424 | ||
425 | /* Lower address should have been handled by asm code */ | |
426 | if (ea < (1UL << MAX_EA_BITS_PER_CONTEXT)) | |
427 | goto slb_bad_addr; | |
428 | ||
429 | /* | |
430 | * consider this as bad access if we take a SLB miss | |
431 | * on an address above addr limit. | |
432 | */ | |
433 | if (ea >= current->mm->context.slb_addr_limit) | |
434 | goto slb_bad_addr; | |
435 | ||
436 | context = get_ea_context(¤t->mm->context, ea); | |
437 | if (!context) | |
438 | goto slb_bad_addr; | |
439 | ||
440 | handle_multi_context_slb_miss(context, ea); | |
441 | exception_exit(prev_state); | |
442 | return; | |
443 | ||
444 | slb_bad_addr: | |
445 | if (user_mode(regs)) | |
446 | _exception(SIGSEGV, regs, SEGV_BNDERR, ea); | |
447 | else | |
448 | bad_page_fault(regs, ea, SIGSEGV); | |
449 | exception_exit(prev_state); | |
450 | } |