[linux-block.git] / arch / powerpc / mm / ppc_mmu_32.c

/*
 * This file contains the routines for handling the MMU on those
 * PowerPC implementations where the MMU substantially follows the
 * architecture specification.  This includes the 6xx, 7xx, 7xxx,
 * and 8260 implementations but excludes the 8xx and 4xx.
 *  -- paulus
 *
 *  Derived from arch/ppc/mm/init.c:
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
 *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
 *    Copyright (C) 1996 Paul Mackerras
 *
 *  Derived from "arch/i386/mm/init.c"
 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/highmem.h>
#include <linux/memblock.h>

#include <asm/prom.h>
#include <asm/mmu.h>
#include <asm/machdep.h>
#include <asm/code-patching.h>

#include "mmu_decl.h"

struct hash_pte *Hash, *Hash_end;
unsigned long Hash_size, Hash_mask;
unsigned long _SDR1;

struct ppc_bat BATS[8][2];	/* 8 pairs of IBAT, DBAT */

struct batrange {		/* stores address ranges mapped by BATs */
	unsigned long start;
	unsigned long limit;
	phys_addr_t phys;
} bat_addrs[8];

/*
 * Return PA for this VA if it is mapped by a BAT, or 0
 */
phys_addr_t v_block_mapped(unsigned long va)
{
	int b;
	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
		if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
			return bat_addrs[b].phys + (va - bat_addrs[b].start);
	return 0;
}

/*
 * Return VA for a given PA or 0 if not mapped
 */
unsigned long p_block_mapped(phys_addr_t pa)
{
	int b;
	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
		if (pa >= bat_addrs[b].phys
	    	    && pa < (bat_addrs[b].limit-bat_addrs[b].start)
		              +bat_addrs[b].phys)
			return bat_addrs[b].start+(pa-bat_addrs[b].phys);
	return 0;
}

unsigned long __init mmu_mapin_ram(unsigned long top)
{
	unsigned long tot, bl, done;
	unsigned long max_size = (256<<20);

	if (__map_without_bats) {
		printk(KERN_DEBUG "RAM mapped without BATs\n");
		return 0;
	}

	/* Set up BAT2 and if necessary BAT3 to cover RAM. */

	/* Make sure we don't map a block larger than the
	   smallest alignment of the physical address. */
	tot = top;
	for (bl = 128<<10; bl < max_size; bl <<= 1) {
		if (bl * 2 > tot)
			break;
	}

	setbat(2, PAGE_OFFSET, 0, bl, PAGE_KERNEL_X);
	done = (unsigned long)bat_addrs[2].limit - PAGE_OFFSET + 1;
	if ((done < tot) && !bat_addrs[3].limit) {
		/* use BAT3 to cover a bit more */
		tot -= done;
		for (bl = 128<<10; bl < max_size; bl <<= 1)
			if (bl * 2 > tot)
				break;
		setbat(3, PAGE_OFFSET+done, done, bl, PAGE_KERNEL_X);
		done = (unsigned long)bat_addrs[3].limit - PAGE_OFFSET + 1;
	}

	return done;
}

/*
 * Set up one of the I/D BAT (block address translation) register pairs.
 * The parameters are not checked; in particular size must be a power
 * of 2 between 128k and 256M.
 */
void __init setbat(int index, unsigned long virt, phys_addr_t phys,
		   unsigned int size, pgprot_t prot)
{
	unsigned int bl;
	int wimgxpp;
	struct ppc_bat *bat = BATS[index];
	unsigned long flags = pgprot_val(prot);

	if ((flags & _PAGE_NO_CACHE) ||
	    (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
		flags &= ~_PAGE_COHERENT;

	bl = (size >> 17) - 1;
	if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
		/* 603, 604, etc. */
		/* Do DBAT first */
		wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
				   | _PAGE_COHERENT | _PAGE_GUARDED);
		wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
		bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
		bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
		if (flags & _PAGE_USER)
			bat[1].batu |= 1; 	/* Vp = 1 */
		if (flags & _PAGE_GUARDED) {
			/* G bit must be zero in IBATs */
			bat[0].batu = bat[0].batl = 0;
		} else {
			/* make IBAT same as DBAT */
			bat[0] = bat[1];
		}
	} else {
		/* 601 cpu */
		if (bl > BL_8M)
			bl = BL_8M;
		wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
				   | _PAGE_COHERENT);
		wimgxpp |= (flags & _PAGE_RW)?
			((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
		bat->batu = virt | wimgxpp | 4;	/* Ks=0, Ku=1 */
		bat->batl = phys | bl | 0x40;	/* V=1 */
	}

	bat_addrs[index].start = virt;
	bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
	bat_addrs[index].phys = phys;
}

/*
 * Preload a translation in the hash table
 */
void hash_preload(struct mm_struct *mm, unsigned long ea,
		  bool is_exec, unsigned long trap)
{
	pmd_t *pmd;

	if (!Hash)
		return;
	pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
	if (!pmd_none(*pmd))
		add_hash_page(mm->context.id, ea, pmd_val(*pmd));
}

/*
 * Initialize the hash table and patch the instructions in hashtable.S.
 */
void __init MMU_init_hw(void)
{
	unsigned int hmask, mb, mb2;
	unsigned int n_hpteg, lg_n_hpteg;

	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
		return;

	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);

#define LG_HPTEG_SIZE	6		/* 64 bytes per HPTEG */
#define SDR1_LOW_BITS	((n_hpteg - 1) >> 10)
#define MIN_N_HPTEG	1024		/* min 64kB hash table */

	/*
	 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
	 * This is less than the recommended amount, but then
	 * Linux ain't AIX.
	 */
	n_hpteg = total_memory / (PAGE_SIZE * 8);
	if (n_hpteg < MIN_N_HPTEG)
		n_hpteg = MIN_N_HPTEG;
	lg_n_hpteg = __ilog2(n_hpteg);
	if (n_hpteg & (n_hpteg - 1)) {
		++lg_n_hpteg;		/* round up if not power of 2 */
		n_hpteg = 1 << lg_n_hpteg;
	}
	Hash_size = n_hpteg << LG_HPTEG_SIZE;

	/*
	 * Find some memory for the hash table.
	 */
	if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
	Hash = __va(memblock_phys_alloc(Hash_size, Hash_size));
	memset(Hash, 0, Hash_size);
	_SDR1 = __pa(Hash) | SDR1_LOW_BITS;

	Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);

	printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
	       (unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);


	/*
	 * Patch up the instructions in hashtable.S:create_hpte
	 */
	if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
	Hash_mask = n_hpteg - 1;
	hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
	mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
	if (lg_n_hpteg > 16)
		mb2 = 16 - LG_HPTEG_SIZE;

	modify_instruction_site(&patch__hash_page_A0, 0xffff, (unsigned int)Hash >> 16);
	modify_instruction_site(&patch__hash_page_A1, 0x7c0, mb << 6);
	modify_instruction_site(&patch__hash_page_A2, 0x7c0, mb2 << 6);
	modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
	modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);

	/*
	 * Patch up the instructions in hashtable.S:flush_hash_page
	 */
	modify_instruction_site(&patch__flush_hash_A0, 0xffff, (unsigned int)Hash >> 16);
	modify_instruction_site(&patch__flush_hash_A1, 0x7c0, mb << 6);
	modify_instruction_site(&patch__flush_hash_A2, 0x7c0, mb2 << 6);
	modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);

	if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
}

void setup_initial_memory_limit(phys_addr_t first_memblock_base,
				phys_addr_t first_memblock_size)
{
	/* We don't currently support the first MEMBLOCK not mapping 0
	 * physical on those processors
	 */
	BUG_ON(first_memblock_base != 0);

	/* 601 can only access 16MB at the moment */
	if (PVR_VER(mfspr(SPRN_PVR)) == 1)
		memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01000000));
	else /* Anything else has 256M mapped */
		memblock_set_current_limit(min_t(u64, first_memblock_size, 0x10000000));
}
Commit	Line	Data
14cf11af PM	1	/*
	2	* This file contains the routines for handling the MMU on those
	3	* PowerPC implementations where the MMU substantially follows the
	4	* architecture specification. This includes the 6xx, 7xx, 7xxx,
0f369103	5	* and 8260 implementations but excludes the 8xx and 4xx.
14cf11af PM	6	* -- paulus
	7	*
	8	* Derived from arch/ppc/mm/init.c:
	9	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	10	*
	11	* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
	12	* and Cort Dougan (PReP) (cort@cs.nmt.edu)
	13	* Copyright (C) 1996 Paul Mackerras
14cf11af PM	14	*
	15	* Derived from "arch/i386/mm/init.c"
	16	* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*
	23	*/
	24
14cf11af PM	25	#include <linux/kernel.h>
	26	#include <linux/mm.h>
	27	#include <linux/init.h>
	28	#include <linux/highmem.h>
95f72d1e	29	#include <linux/memblock.h>
14cf11af PM	30
	31	#include <asm/prom.h>
	32	#include <asm/mmu.h>
	33	#include <asm/machdep.h>
9efc74ff	34	#include <asm/code-patching.h>
14cf11af PM	35
14cf11af PM	36	#include "mmu_decl.h"
14cf11af	37
8e561e7e	38	struct hash_pte Hash, Hash_end;
14cf11af PM	39	unsigned long Hash_size, Hash_mask;
	40	unsigned long _SDR1;
	41
316a4058	42	struct ppc_bat BATS[8][2]; /* 8 pairs of IBAT, DBAT */
14cf11af PM	43
	44	struct batrange { /* stores address ranges mapped by BATs */
	45	unsigned long start;
	46	unsigned long limit;
7c5c4325	47	phys_addr_t phys;
ee0339f2	48	} bat_addrs[8];
14cf11af PM	49
	50	/*
	51	* Return PA for this VA if it is mapped by a BAT, or 0
	52	*/
3084cdb7	53	phys_addr_t v_block_mapped(unsigned long va)
14cf11af PM	54	{
14cf11af PM	55	int b;
e93ba1b7	56	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
14cf11af PM	57	if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
	58	return bat_addrs[b].phys + (va - bat_addrs[b].start);
	59	return 0;
	60	}
	61
	62	/*
	63	* Return VA for a given PA or 0 if not mapped
	64	*/
3084cdb7	65	unsigned long p_block_mapped(phys_addr_t pa)
14cf11af PM	66	{
14cf11af PM	67	int b;
e93ba1b7	68	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
14cf11af PM	69	if (pa >= bat_addrs[b].phys
	70	&& pa < (bat_addrs[b].limit-bat_addrs[b].start)
	71	+bat_addrs[b].phys)
	72	return bat_addrs[b].start+(pa-bat_addrs[b].phys);
	73	return 0;
	74	}
	75
de32400d	76	unsigned long __init mmu_mapin_ram(unsigned long top)
14cf11af	77	{
14cf11af PM	78	unsigned long tot, bl, done;
14cf11af PM	79	unsigned long max_size = (256<<20);
14cf11af	80
88df6e90 BH	81	if (__map_without_bats) {
88df6e90 BH	82	printk(KERN_DEBUG "RAM mapped without BATs\n");
14cf11af	83	return 0;
88df6e90	84	}
14cf11af PM	85
	86	/* Set up BAT2 and if necessary BAT3 to cover RAM. */
	87
	88	/* Make sure we don't map a block larger than the
	89	smallest alignment of the physical address. */
de32400d	90	tot = top;
14cf11af PM	91	for (bl = 128<<10; bl < max_size; bl <<= 1) {
	92	if (bl * 2 > tot)
	93	break;
	94	}
	95
8d1cf34e	96	setbat(2, PAGE_OFFSET, 0, bl, PAGE_KERNEL_X);
ccdcef72	97	done = (unsigned long)bat_addrs[2].limit - PAGE_OFFSET + 1;
14cf11af PM	98	if ((done < tot) && !bat_addrs[3].limit) {
	99	/* use BAT3 to cover a bit more */
	100	tot -= done;
	101	for (bl = 128<<10; bl < max_size; bl <<= 1)
	102	if (bl * 2 > tot)
	103	break;
8d1cf34e	104	setbat(3, PAGE_OFFSET+done, done, bl, PAGE_KERNEL_X);
ccdcef72	105	done = (unsigned long)bat_addrs[3].limit - PAGE_OFFSET + 1;
14cf11af PM	106	}
	107
	108	return done;
14cf11af PM	109	}
	110
	111	/*
	112	* Set up one of the I/D BAT (block address translation) register pairs.
	113	* The parameters are not checked; in particular size must be a power
	114	* of 2 between 128k and 256M.
	115	*/
7c5c4325	116	void __init setbat(int index, unsigned long virt, phys_addr_t phys,
5dd4e4f6	117	unsigned int size, pgprot_t prot)
14cf11af PM	118	{
	119	unsigned int bl;
	120	int wimgxpp;
316a4058	121	struct ppc_bat *bat = BATS[index];
5dd4e4f6	122	unsigned long flags = pgprot_val(prot);
14cf11af	123
4c456a67 GP	124	if ((flags & _PAGE_NO_CACHE) \|\|
	125	(cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
	126	flags &= ~_PAGE_COHERENT;
14cf11af PM	127
	128	bl = (size >> 17) - 1;
	129	if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
	130	/* 603, 604, etc. */
	131	/* Do DBAT first */
	132	wimgxpp = flags & (_PAGE_WRITETHRU \| _PAGE_NO_CACHE
	133	\| _PAGE_COHERENT \| _PAGE_GUARDED);
	134	wimgxpp \|= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
316a4058 BB	135	bat[1].batu = virt \| (bl << 2) \| 2; /* Vs=1, Vp=0 */
316a4058 BB	136	bat[1].batl = BAT_PHYS_ADDR(phys) \| wimgxpp;
14cf11af	137	if (flags & _PAGE_USER)
316a4058	138	bat[1].batu \|= 1; /* Vp = 1 */
14cf11af PM	139	if (flags & _PAGE_GUARDED) {
14cf11af PM	140	/* G bit must be zero in IBATs */
316a4058	141	bat[0].batu = bat[0].batl = 0;
14cf11af PM	142	} else {
	143	/* make IBAT same as DBAT */
	144	bat[0] = bat[1];
	145	}
	146	} else {
	147	/* 601 cpu */
	148	if (bl > BL_8M)
	149	bl = BL_8M;
	150	wimgxpp = flags & (_PAGE_WRITETHRU \| _PAGE_NO_CACHE
	151	\| _PAGE_COHERENT);
	152	wimgxpp \|= (flags & _PAGE_RW)?
	153	((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
316a4058 BB	154	bat->batu = virt \| wimgxpp \| 4; /* Ks=0, Ku=1 */
316a4058 BB	155	bat->batl = phys \| bl \| 0x40; /* V=1 */
14cf11af PM	156	}
	157
	158	bat_addrs[index].start = virt;
	159	bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
	160	bat_addrs[index].phys = phys;
	161	}
	162
3c726f8d BH	163	/*
	164	* Preload a translation in the hash table
	165	*/
	166	void hash_preload(struct mm_struct *mm, unsigned long ea,
34eb138e	167	bool is_exec, unsigned long trap)
3c726f8d BH	168	{
	169	pmd_t *pmd;
	170
d8731527	171	if (!Hash)
3c726f8d	172	return;
f1a1eb29	173	pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
3c726f8d	174	if (!pmd_none(*pmd))
6218a761	175	add_hash_page(mm->context.id, ea, pmd_val(*pmd));
3c726f8d BH	176	}
3c726f8d BH	177
14cf11af PM	178	/*
	179	* Initialize the hash table and patch the instructions in hashtable.S.
	180	*/
	181	void __init MMU_init_hw(void)
	182	{
	183	unsigned int hmask, mb, mb2;
	184	unsigned int n_hpteg, lg_n_hpteg;
	185
4a3a224c	186	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
14cf11af	187	return;
14cf11af PM	188
	189	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
	190
14cf11af PM	191	#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
	192	#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
	193	#define MIN_N_HPTEG 1024 /* min 64kB hash table */
14cf11af	194
14cf11af PM	195	/*
	196	* Allow 1 HPTE (1/8 HPTEG) for each page of memory.
	197	* This is less than the recommended amount, but then
	198	* Linux ain't AIX.
	199	*/
	200	n_hpteg = total_memory / (PAGE_SIZE * 8);
	201	if (n_hpteg < MIN_N_HPTEG)
	202	n_hpteg = MIN_N_HPTEG;
	203	lg_n_hpteg = __ilog2(n_hpteg);
	204	if (n_hpteg & (n_hpteg - 1)) {
	205	++lg_n_hpteg; /* round up if not power of 2 */
	206	n_hpteg = 1 << lg_n_hpteg;
	207	}
	208	Hash_size = n_hpteg << LG_HPTEG_SIZE;
	209
	210	/*
	211	* Find some memory for the hash table.
	212	*/
	213	if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
9a8dd708	214	Hash = __va(memblock_phys_alloc(Hash_size, Hash_size));
b05ae4ee	215	memset(Hash, 0, Hash_size);
14cf11af	216	_SDR1 = __pa(Hash) \| SDR1_LOW_BITS;
14cf11af	217
8e561e7e	218	Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
14cf11af	219
c7c8eede TB	220	printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
c7c8eede TB	221	(unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
14cf11af PM	222
	223
	224	/*
	225	* Patch up the instructions in hashtable.S:create_hpte
	226	*/
	227	if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
	228	Hash_mask = n_hpteg - 1;
	229	hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
	230	mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
	231	if (lg_n_hpteg > 16)
	232	mb2 = 16 - LG_HPTEG_SIZE;
	233
9efc74ff CL	234	modify_instruction_site(&patch__hash_page_A0, 0xffff, (unsigned int)Hash >> 16);
	235	modify_instruction_site(&patch__hash_page_A1, 0x7c0, mb << 6);
	236	modify_instruction_site(&patch__hash_page_A2, 0x7c0, mb2 << 6);
	237	modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
	238	modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);
14cf11af PM	239
	240	/*
	241	* Patch up the instructions in hashtable.S:flush_hash_page
	242	*/
9efc74ff CL	243	modify_instruction_site(&patch__flush_hash_A0, 0xffff, (unsigned int)Hash >> 16);
	244	modify_instruction_site(&patch__flush_hash_A1, 0x7c0, mb << 6);
	245	modify_instruction_site(&patch__flush_hash_A2, 0x7c0, mb2 << 6);
	246	modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
14cf11af PM	247
	248	if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
	249	}
cd3db0c4 BH	250
	251	void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	252	phys_addr_t first_memblock_size)
	253	{
	254	/* We don't currently support the first MEMBLOCK not mapping 0
	255	* physical on those processors
	256	*/
	257	BUG_ON(first_memblock_base != 0);
	258
	259	/* 601 can only access 16MB at the moment */
	260	if (PVR_VER(mfspr(SPRN_PVR)) == 1)
	261	memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01000000));
	262	else /* Anything else has 256M mapped */
	263	memblock_set_current_limit(min_t(u64, first_memblock_size, 0x10000000));
	264	}