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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
0186f47e KG |
2 | /* |
3 | * This file contains common routines for dealing with free of page tables | |
8d30c14c | 4 | * Along with common page table handling code |
0186f47e KG |
5 | * |
6 | * Derived from arch/powerpc/mm/tlb_64.c: | |
7 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
8 | * | |
9 | * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) | |
10 | * and Cort Dougan (PReP) (cort@cs.nmt.edu) | |
11 | * Copyright (C) 1996 Paul Mackerras | |
12 | * | |
13 | * Derived from "arch/i386/mm/init.c" | |
14 | * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds | |
15 | * | |
16 | * Dave Engebretsen <engebret@us.ibm.com> | |
17 | * Rework for PPC64 port. | |
0186f47e KG |
18 | */ |
19 | ||
20 | #include <linux/kernel.h> | |
5a0e3ad6 | 21 | #include <linux/gfp.h> |
0186f47e | 22 | #include <linux/mm.h> |
0186f47e KG |
23 | #include <linux/percpu.h> |
24 | #include <linux/hardirq.h> | |
41151e77 | 25 | #include <linux/hugetlb.h> |
0186f47e KG |
26 | #include <asm/tlbflush.h> |
27 | #include <asm/tlb.h> | |
0caed4de | 28 | #include <asm/hugetlb.h> |
d25da505 | 29 | #include <asm/pte-walk.h> |
0186f47e | 30 | |
3018fbc6 ME |
31 | #ifdef CONFIG_PPC64 |
32 | #define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD) | |
33 | #else | |
34 | #define PGD_ALIGN PAGE_SIZE | |
35 | #endif | |
36 | ||
37 | pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN); | |
e72421a0 | 38 | |
8d30c14c BH |
39 | static inline int is_exec_fault(void) |
40 | { | |
41 | return current->thread.regs && TRAP(current->thread.regs) == 0x400; | |
42 | } | |
43 | ||
44 | /* We only try to do i/d cache coherency on stuff that looks like | |
45 | * reasonably "normal" PTEs. We currently require a PTE to be present | |
30bda41a | 46 | * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that |
ea3cc330 | 47 | * on userspace PTEs |
8d30c14c BH |
48 | */ |
49 | static inline int pte_looks_normal(pte_t pte) | |
50 | { | |
ac29c640 | 51 | |
26973fa5 | 52 | if (pte_present(pte) && !pte_special(pte)) { |
30bda41a AK |
53 | if (pte_ci(pte)) |
54 | return 0; | |
ac29c640 AK |
55 | if (pte_user(pte)) |
56 | return 1; | |
57 | } | |
58 | return 0; | |
8d30c14c BH |
59 | } |
60 | ||
9fee28ba | 61 | static struct folio *maybe_pte_to_folio(pte_t pte) |
ea3cc330 BH |
62 | { |
63 | unsigned long pfn = pte_pfn(pte); | |
64 | struct page *page; | |
65 | ||
66 | if (unlikely(!pfn_valid(pfn))) | |
67 | return NULL; | |
68 | page = pfn_to_page(pfn); | |
69 | if (PageReserved(page)) | |
70 | return NULL; | |
9fee28ba | 71 | return page_folio(page); |
ea3cc330 BH |
72 | } |
73 | ||
d81e6f8b | 74 | #ifdef CONFIG_PPC_BOOK3S |
ea3cc330 | 75 | |
8d30c14c | 76 | /* Server-style MMU handles coherency when hashing if HW exec permission |
ea3cc330 BH |
77 | * is supposed per page (currently 64-bit only). If not, then, we always |
78 | * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec | |
79 | * support falls into the same category. | |
8d30c14c | 80 | */ |
ea3cc330 | 81 | |
385e89d5 | 82 | static pte_t set_pte_filter_hash(pte_t pte) |
8d30c14c | 83 | { |
ea3cc330 BH |
84 | pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); |
85 | if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) || | |
86 | cpu_has_feature(CPU_FTR_NOEXECUTE))) { | |
9fee28ba MWO |
87 | struct folio *folio = maybe_pte_to_folio(pte); |
88 | if (!folio) | |
ea3cc330 | 89 | return pte; |
9fee28ba MWO |
90 | if (!test_bit(PG_dcache_clean, &folio->flags)) { |
91 | flush_dcache_icache_folio(folio); | |
92 | set_bit(PG_dcache_clean, &folio->flags); | |
ea3cc330 BH |
93 | } |
94 | } | |
95 | return pte; | |
8d30c14c | 96 | } |
ea3cc330 | 97 | |
d81e6f8b | 98 | #else /* CONFIG_PPC_BOOK3S */ |
ea3cc330 | 99 | |
385e89d5 CL |
100 | static pte_t set_pte_filter_hash(pte_t pte) { return pte; } |
101 | ||
102 | #endif /* CONFIG_PPC_BOOK3S */ | |
103 | ||
ea3cc330 BH |
104 | /* Embedded type MMU with HW exec support. This is a bit more complicated |
105 | * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so | |
106 | * instead we "filter out" the exec permission for non clean pages. | |
8d30c14c | 107 | */ |
b12c07a4 | 108 | static inline pte_t set_pte_filter(pte_t pte) |
8d30c14c | 109 | { |
9fee28ba | 110 | struct folio *folio; |
ea3cc330 | 111 | |
af3a0ea4 NP |
112 | if (radix_enabled()) |
113 | return pte; | |
114 | ||
385e89d5 CL |
115 | if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) |
116 | return set_pte_filter_hash(pte); | |
117 | ||
ea3cc330 | 118 | /* No exec permission in the first place, move on */ |
26973fa5 | 119 | if (!pte_exec(pte) || !pte_looks_normal(pte)) |
ea3cc330 BH |
120 | return pte; |
121 | ||
122 | /* If you set _PAGE_EXEC on weird pages you're on your own */ | |
9fee28ba MWO |
123 | folio = maybe_pte_to_folio(pte); |
124 | if (unlikely(!folio)) | |
ea3cc330 BH |
125 | return pte; |
126 | ||
127 | /* If the page clean, we move on */ | |
9fee28ba | 128 | if (test_bit(PG_dcache_clean, &folio->flags)) |
ea3cc330 BH |
129 | return pte; |
130 | ||
131 | /* If it's an exec fault, we flush the cache and make it clean */ | |
132 | if (is_exec_fault()) { | |
9fee28ba MWO |
133 | flush_dcache_icache_folio(folio); |
134 | set_bit(PG_dcache_clean, &folio->flags); | |
ea3cc330 BH |
135 | return pte; |
136 | } | |
137 | ||
138 | /* Else, we filter out _PAGE_EXEC */ | |
26973fa5 | 139 | return pte_exprotect(pte); |
8d30c14c | 140 | } |
ea3cc330 BH |
141 | |
142 | static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma, | |
143 | int dirty) | |
144 | { | |
9fee28ba | 145 | struct folio *folio; |
ea3cc330 | 146 | |
af3a0ea4 NP |
147 | if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) |
148 | return pte; | |
149 | ||
385e89d5 CL |
150 | if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) |
151 | return pte; | |
152 | ||
ea3cc330 BH |
153 | /* So here, we only care about exec faults, as we use them |
154 | * to recover lost _PAGE_EXEC and perform I$/D$ coherency | |
155 | * if necessary. Also if _PAGE_EXEC is already set, same deal, | |
156 | * we just bail out | |
157 | */ | |
26973fa5 | 158 | if (dirty || pte_exec(pte) || !is_exec_fault()) |
ea3cc330 BH |
159 | return pte; |
160 | ||
161 | #ifdef CONFIG_DEBUG_VM | |
162 | /* So this is an exec fault, _PAGE_EXEC is not set. If it was | |
163 | * an error we would have bailed out earlier in do_page_fault() | |
164 | * but let's make sure of it | |
165 | */ | |
166 | if (WARN_ON(!(vma->vm_flags & VM_EXEC))) | |
167 | return pte; | |
168 | #endif /* CONFIG_DEBUG_VM */ | |
169 | ||
170 | /* If you set _PAGE_EXEC on weird pages you're on your own */ | |
9fee28ba MWO |
171 | folio = maybe_pte_to_folio(pte); |
172 | if (unlikely(!folio)) | |
ea3cc330 BH |
173 | goto bail; |
174 | ||
175 | /* If the page is already clean, we move on */ | |
9fee28ba | 176 | if (test_bit(PG_dcache_clean, &folio->flags)) |
ea3cc330 BH |
177 | goto bail; |
178 | ||
ec94b9b2 | 179 | /* Clean the page and set PG_dcache_clean */ |
9fee28ba MWO |
180 | flush_dcache_icache_folio(folio); |
181 | set_bit(PG_dcache_clean, &folio->flags); | |
ea3cc330 BH |
182 | |
183 | bail: | |
26973fa5 | 184 | return pte_mkexec(pte); |
ea3cc330 BH |
185 | } |
186 | ||
8d30c14c BH |
187 | /* |
188 | * set_pte stores a linux PTE into the linux page table. | |
189 | */ | |
9fee28ba MWO |
190 | void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep, |
191 | pte_t pte, unsigned int nr) | |
8d30c14c | 192 | { |
8a0516ed | 193 | /* |
da7ad366 AK |
194 | * Make sure hardware valid bit is not set. We don't do |
195 | * tlb flush for this update. | |
8a0516ed | 196 | */ |
dd0e144a | 197 | VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep)); |
c7d54842 | 198 | |
8d30c14c BH |
199 | /* Note: mm->context.id might not yet have been assigned as |
200 | * this context might not have been activated yet when this | |
201 | * is called. | |
202 | */ | |
79df1b37 | 203 | pte = set_pte_filter(pte); |
8d30c14c BH |
204 | |
205 | /* Perform the setting of the PTE */ | |
9fee28ba MWO |
206 | arch_enter_lazy_mmu_mode(); |
207 | for (;;) { | |
208 | __set_pte_at(mm, addr, ptep, pte, 0); | |
209 | if (--nr == 0) | |
210 | break; | |
211 | ptep++; | |
212 | pte = __pte(pte_val(pte) + (1UL << PTE_RPN_SHIFT)); | |
213 | addr += PAGE_SIZE; | |
214 | } | |
215 | arch_leave_lazy_mmu_mode(); | |
8d30c14c BH |
216 | } |
217 | ||
aec98260 CL |
218 | void unmap_kernel_page(unsigned long va) |
219 | { | |
220 | pmd_t *pmdp = pmd_off_k(va); | |
221 | pte_t *ptep = pte_offset_kernel(pmdp, va); | |
222 | ||
223 | pte_clear(&init_mm, va, ptep); | |
224 | flush_tlb_kernel_range(va, va + PAGE_SIZE); | |
225 | } | |
226 | ||
8d30c14c BH |
227 | /* |
228 | * This is called when relaxing access to a PTE. It's also called in the page | |
229 | * fault path when we don't hit any of the major fault cases, ie, a minor | |
230 | * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have | |
231 | * handled those two for us, we additionally deal with missing execute | |
232 | * permission here on some processors | |
233 | */ | |
234 | int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, | |
235 | pte_t *ptep, pte_t entry, int dirty) | |
236 | { | |
237 | int changed; | |
ea3cc330 | 238 | entry = set_access_flags_filter(entry, vma, dirty); |
8d30c14c BH |
239 | changed = !pte_same(*(ptep), entry); |
240 | if (changed) { | |
f069ff39 | 241 | assert_pte_locked(vma->vm_mm, address); |
e4c1112c AK |
242 | __ptep_set_access_flags(vma, ptep, entry, |
243 | address, mmu_virtual_psize); | |
8d30c14c BH |
244 | } |
245 | return changed; | |
246 | } | |
247 | ||
f069ff39 | 248 | #ifdef CONFIG_HUGETLB_PAGE |
bce85a16 BL |
249 | int huge_ptep_set_access_flags(struct vm_area_struct *vma, |
250 | unsigned long addr, pte_t *ptep, | |
251 | pte_t pte, int dirty) | |
f069ff39 AK |
252 | { |
253 | #ifdef HUGETLB_NEED_PRELOAD | |
254 | /* | |
255 | * The "return 1" forces a call of update_mmu_cache, which will write a | |
256 | * TLB entry. Without this, platforms that don't do a write of the TLB | |
257 | * entry in the TLB miss handler asm will fault ad infinitum. | |
258 | */ | |
259 | ptep_set_access_flags(vma, addr, ptep, pte, dirty); | |
260 | return 1; | |
261 | #else | |
e4c1112c | 262 | int changed, psize; |
f069ff39 AK |
263 | |
264 | pte = set_access_flags_filter(pte, vma, dirty); | |
265 | changed = !pte_same(*(ptep), pte); | |
266 | if (changed) { | |
e4c1112c AK |
267 | |
268 | #ifdef CONFIG_PPC_BOOK3S_64 | |
ed515b68 AK |
269 | struct hstate *h = hstate_vma(vma); |
270 | ||
271 | psize = hstate_get_psize(h); | |
272 | #ifdef CONFIG_DEBUG_VM | |
273 | assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep)); | |
274 | #endif | |
275 | ||
e4c1112c AK |
276 | #else |
277 | /* | |
b12c07a4 CL |
278 | * Not used on non book3s64 platforms. |
279 | * 8xx compares it with mmu_virtual_psize to | |
280 | * know if it is a huge page or not. | |
e4c1112c | 281 | */ |
b12c07a4 | 282 | psize = MMU_PAGE_COUNT; |
f069ff39 | 283 | #endif |
e4c1112c | 284 | __ptep_set_access_flags(vma, ptep, pte, addr, psize); |
f069ff39 AK |
285 | } |
286 | return changed; | |
287 | #endif | |
288 | } | |
b12c07a4 CL |
289 | |
290 | #if defined(CONFIG_PPC_8xx) | |
935d4f0c RR |
291 | void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, |
292 | pte_t pte, unsigned long sz) | |
b12c07a4 | 293 | { |
78c24f7b | 294 | pmd_t *pmd = pmd_off(mm, addr); |
b250c8c0 | 295 | pte_basic_t val; |
c7d19189 | 296 | pte_basic_t *entry = (pte_basic_t *)ptep; |
175a9999 | 297 | int num, i; |
b250c8c0 | 298 | |
b12c07a4 CL |
299 | /* |
300 | * Make sure hardware valid bit is not set. We don't do | |
301 | * tlb flush for this update. | |
302 | */ | |
303 | VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep)); | |
304 | ||
b12c07a4 CL |
305 | pte = set_pte_filter(pte); |
306 | ||
b250c8c0 | 307 | val = pte_val(pte); |
175a9999 CL |
308 | |
309 | num = number_of_cells_per_pte(pmd, val, 1); | |
310 | ||
b250c8c0 CL |
311 | for (i = 0; i < num; i++, entry++, val += SZ_4K) |
312 | *entry = val; | |
b12c07a4 CL |
313 | } |
314 | #endif | |
f069ff39 AK |
315 | #endif /* CONFIG_HUGETLB_PAGE */ |
316 | ||
8d30c14c BH |
317 | #ifdef CONFIG_DEBUG_VM |
318 | void assert_pte_locked(struct mm_struct *mm, unsigned long addr) | |
319 | { | |
320 | pgd_t *pgd; | |
2fb47060 | 321 | p4d_t *p4d; |
8d30c14c BH |
322 | pud_t *pud; |
323 | pmd_t *pmd; | |
3d140215 HD |
324 | pte_t *pte; |
325 | spinlock_t *ptl; | |
8d30c14c BH |
326 | |
327 | if (mm == &init_mm) | |
328 | return; | |
329 | pgd = mm->pgd + pgd_index(addr); | |
330 | BUG_ON(pgd_none(*pgd)); | |
2fb47060 MR |
331 | p4d = p4d_offset(pgd, addr); |
332 | BUG_ON(p4d_none(*p4d)); | |
333 | pud = pud_offset(p4d, addr); | |
8d30c14c BH |
334 | BUG_ON(pud_none(*pud)); |
335 | pmd = pmd_offset(pud, addr); | |
a00e7bea AK |
336 | /* |
337 | * khugepaged to collapse normal pages to hugepage, first set | |
c1e8d7c6 | 338 | * pmd to none to force page fault/gup to take mmap_lock. After |
a00e7bea AK |
339 | * pmd is set to none, we do a pte_clear which does this assertion |
340 | * so if we find pmd none, return. | |
341 | */ | |
342 | if (pmd_none(*pmd)) | |
343 | return; | |
3d140215 HD |
344 | pte = pte_offset_map_nolock(mm, pmd, addr, &ptl); |
345 | BUG_ON(!pte); | |
346 | assert_spin_locked(ptl); | |
347 | pte_unmap(pte); | |
8d30c14c BH |
348 | } |
349 | #endif /* CONFIG_DEBUG_VM */ | |
350 | ||
e9ab1a1c AK |
351 | unsigned long vmalloc_to_phys(void *va) |
352 | { | |
353 | unsigned long pfn = vmalloc_to_pfn(va); | |
354 | ||
355 | BUG_ON(!pfn); | |
356 | return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va); | |
357 | } | |
358 | EXPORT_SYMBOL_GPL(vmalloc_to_phys); | |
0caed4de CL |
359 | |
360 | /* | |
361 | * We have 4 cases for pgds and pmds: | |
362 | * (1) invalid (all zeroes) | |
363 | * (2) pointer to next table, as normal; bottom 6 bits == 0 | |
364 | * (3) leaf pte for huge page _PAGE_PTE set | |
365 | * (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table | |
366 | * | |
367 | * So long as we atomically load page table pointers we are safe against teardown, | |
87c78b61 | 368 | * we can follow the address down to the page and take a ref on it. |
0caed4de CL |
369 | * This function need to be called with interrupts disabled. We use this variant |
370 | * when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED | |
371 | */ | |
372 | pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea, | |
373 | bool *is_thp, unsigned *hpage_shift) | |
374 | { | |
2fb47060 MR |
375 | pgd_t *pgdp; |
376 | p4d_t p4d, *p4dp; | |
0caed4de CL |
377 | pud_t pud, *pudp; |
378 | pmd_t pmd, *pmdp; | |
379 | pte_t *ret_pte; | |
380 | hugepd_t *hpdp = NULL; | |
2fb47060 | 381 | unsigned pdshift; |
0caed4de CL |
382 | |
383 | if (hpage_shift) | |
384 | *hpage_shift = 0; | |
385 | ||
386 | if (is_thp) | |
387 | *is_thp = false; | |
388 | ||
0caed4de CL |
389 | /* |
390 | * Always operate on the local stack value. This make sure the | |
391 | * value don't get updated by a parallel THP split/collapse, | |
392 | * page fault or a page unmap. The return pte_t * is still not | |
393 | * stable. So should be checked there for above conditions. | |
2fb47060 | 394 | * Top level is an exception because it is folded into p4d. |
0caed4de | 395 | */ |
2fb47060 MR |
396 | pgdp = pgdir + pgd_index(ea); |
397 | p4dp = p4d_offset(pgdp, ea); | |
398 | p4d = READ_ONCE(*p4dp); | |
399 | pdshift = P4D_SHIFT; | |
400 | ||
401 | if (p4d_none(p4d)) | |
0caed4de | 402 | return NULL; |
fab9a116 | 403 | |
2fb47060 MR |
404 | if (p4d_is_leaf(p4d)) { |
405 | ret_pte = (pte_t *)p4dp; | |
0caed4de | 406 | goto out; |
fab9a116 | 407 | } |
d6eacedd | 408 | |
2fb47060 MR |
409 | if (is_hugepd(__hugepd(p4d_val(p4d)))) { |
410 | hpdp = (hugepd_t *)&p4d; | |
fab9a116 CL |
411 | goto out_huge; |
412 | } | |
0caed4de | 413 | |
26e66b08 CL |
414 | /* |
415 | * Even if we end up with an unmap, the pgtable will not | |
416 | * be freed, because we do an rcu free and here we are | |
417 | * irq disabled | |
418 | */ | |
419 | pdshift = PUD_SHIFT; | |
2fb47060 | 420 | pudp = pud_offset(&p4d, ea); |
26e66b08 | 421 | pud = READ_ONCE(*pudp); |
fab9a116 | 422 | |
26e66b08 CL |
423 | if (pud_none(pud)) |
424 | return NULL; | |
e2fb2511 | 425 | |
d6eacedd | 426 | if (pud_is_leaf(pud)) { |
26e66b08 CL |
427 | ret_pte = (pte_t *)pudp; |
428 | goto out; | |
0caed4de | 429 | } |
d6eacedd | 430 | |
26e66b08 CL |
431 | if (is_hugepd(__hugepd(pud_val(pud)))) { |
432 | hpdp = (hugepd_t *)&pud; | |
433 | goto out_huge; | |
434 | } | |
d6eacedd | 435 | |
26e66b08 CL |
436 | pdshift = PMD_SHIFT; |
437 | pmdp = pmd_offset(&pud, ea); | |
438 | pmd = READ_ONCE(*pmdp); | |
a00196a2 | 439 | |
26e66b08 | 440 | /* |
a00196a2 NP |
441 | * A hugepage collapse is captured by this condition, see |
442 | * pmdp_collapse_flush. | |
26e66b08 CL |
443 | */ |
444 | if (pmd_none(pmd)) | |
445 | return NULL; | |
446 | ||
a00196a2 NP |
447 | #ifdef CONFIG_PPC_BOOK3S_64 |
448 | /* | |
449 | * A hugepage split is captured by this condition, see | |
450 | * pmdp_invalidate. | |
451 | * | |
452 | * Huge page modification can be caught here too. | |
453 | */ | |
454 | if (pmd_is_serializing(pmd)) | |
455 | return NULL; | |
456 | #endif | |
457 | ||
26e66b08 CL |
458 | if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) { |
459 | if (is_thp) | |
460 | *is_thp = true; | |
461 | ret_pte = (pte_t *)pmdp; | |
462 | goto out; | |
463 | } | |
d6eacedd AK |
464 | |
465 | if (pmd_is_leaf(pmd)) { | |
26e66b08 CL |
466 | ret_pte = (pte_t *)pmdp; |
467 | goto out; | |
468 | } | |
d6eacedd | 469 | |
26e66b08 CL |
470 | if (is_hugepd(__hugepd(pmd_val(pmd)))) { |
471 | hpdp = (hugepd_t *)&pmd; | |
472 | goto out_huge; | |
473 | } | |
474 | ||
475 | return pte_offset_kernel(&pmd, ea); | |
476 | ||
fab9a116 | 477 | out_huge: |
0caed4de CL |
478 | if (!hpdp) |
479 | return NULL; | |
480 | ||
481 | ret_pte = hugepte_offset(*hpdp, ea, pdshift); | |
482 | pdshift = hugepd_shift(*hpdp); | |
483 | out: | |
484 | if (hpage_shift) | |
485 | *hpage_shift = pdshift; | |
486 | return ret_pte; | |
487 | } | |
488 | EXPORT_SYMBOL_GPL(__find_linux_pte); | |
6eac1eaf AK |
489 | |
490 | /* Note due to the way vm flags are laid out, the bits are XWR */ | |
491 | const pgprot_t protection_map[16] = { | |
492 | [VM_NONE] = PAGE_NONE, | |
493 | [VM_READ] = PAGE_READONLY, | |
494 | [VM_WRITE] = PAGE_COPY, | |
495 | [VM_WRITE | VM_READ] = PAGE_COPY, | |
496 | [VM_EXEC] = PAGE_READONLY_X, | |
497 | [VM_EXEC | VM_READ] = PAGE_READONLY_X, | |
498 | [VM_EXEC | VM_WRITE] = PAGE_COPY_X, | |
499 | [VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_X, | |
500 | [VM_SHARED] = PAGE_NONE, | |
501 | [VM_SHARED | VM_READ] = PAGE_READONLY, | |
502 | [VM_SHARED | VM_WRITE] = PAGE_SHARED, | |
503 | [VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED, | |
504 | [VM_SHARED | VM_EXEC] = PAGE_READONLY_X, | |
505 | [VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_X, | |
506 | [VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED_X, | |
507 | [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_X | |
508 | }; | |
509 | ||
510 | #ifndef CONFIG_PPC_BOOK3S_64 | |
511 | DECLARE_VM_GET_PAGE_PROT | |
512 | #endif |