Commit | Line | Data |
---|---|---|
14cf11af PM |
1 | /* |
2 | * Declarations of procedures and variables shared between files | |
3 | * in arch/ppc/mm/. | |
4 | * | |
5 | * Derived from arch/ppc/mm/init.c: | |
6 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
7 | * | |
8 | * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) | |
9 | * and Cort Dougan (PReP) (cort@cs.nmt.edu) | |
10 | * Copyright (C) 1996 Paul Mackerras | |
14cf11af PM |
11 | * |
12 | * Derived from "arch/i386/mm/init.c" | |
13 | * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | * | |
20 | */ | |
62102307 | 21 | #include <linux/mm.h> |
14cf11af PM |
22 | #include <asm/mmu.h> |
23 | ||
2a4aca11 | 24 | #ifdef CONFIG_PPC_MMU_NOHASH |
cf4a6085 | 25 | #include <asm/trace.h> |
2a4aca11 BH |
26 | |
27 | /* | |
28 | * On 40x and 8xx, we directly inline tlbia and tlbivax | |
29 | */ | |
968159c0 | 30 | #if defined(CONFIG_40x) || defined(CONFIG_PPC_8xx) |
2a4aca11 BH |
31 | static inline void _tlbil_all(void) |
32 | { | |
4a082682 | 33 | asm volatile ("sync; tlbia; isync" : : : "memory"); |
8114c36e | 34 | trace_tlbia(MMU_NO_CONTEXT); |
2a4aca11 BH |
35 | } |
36 | static inline void _tlbil_pid(unsigned int pid) | |
37 | { | |
4a082682 | 38 | asm volatile ("sync; tlbia; isync" : : : "memory"); |
8114c36e | 39 | trace_tlbia(pid); |
2a4aca11 | 40 | } |
d4e167da BH |
41 | #define _tlbil_pid_noind(pid) _tlbil_pid(pid) |
42 | ||
968159c0 | 43 | #else /* CONFIG_40x || CONFIG_PPC_8xx */ |
2a4aca11 BH |
44 | extern void _tlbil_all(void); |
45 | extern void _tlbil_pid(unsigned int pid); | |
25d21ad6 BH |
46 | #ifdef CONFIG_PPC_BOOK3E |
47 | extern void _tlbil_pid_noind(unsigned int pid); | |
48 | #else | |
d4e167da | 49 | #define _tlbil_pid_noind(pid) _tlbil_pid(pid) |
25d21ad6 | 50 | #endif |
968159c0 | 51 | #endif /* !(CONFIG_40x || CONFIG_PPC_8xx) */ |
2a4aca11 BH |
52 | |
53 | /* | |
54 | * On 8xx, we directly inline tlbie, on others, it's extern | |
55 | */ | |
968159c0 | 56 | #ifdef CONFIG_PPC_8xx |
d4e167da BH |
57 | static inline void _tlbil_va(unsigned long address, unsigned int pid, |
58 | unsigned int tsize, unsigned int ind) | |
2a4aca11 | 59 | { |
4a082682 | 60 | asm volatile ("tlbie %0; sync" : : "r" (address) : "memory"); |
cf4a6085 | 61 | trace_tlbie(0, 0, address, pid, 0, 0, 0); |
2a4aca11 | 62 | } |
25d21ad6 BH |
63 | #elif defined(CONFIG_PPC_BOOK3E) |
64 | extern void _tlbil_va(unsigned long address, unsigned int pid, | |
65 | unsigned int tsize, unsigned int ind); | |
66 | #else | |
d4e167da BH |
67 | extern void __tlbil_va(unsigned long address, unsigned int pid); |
68 | static inline void _tlbil_va(unsigned long address, unsigned int pid, | |
69 | unsigned int tsize, unsigned int ind) | |
70 | { | |
71 | __tlbil_va(address, pid); | |
72 | } | |
968159c0 | 73 | #endif /* CONFIG_PPC_8xx */ |
2a4aca11 | 74 | |
e7f75ad0 | 75 | #if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_PPC_47x) |
25d21ad6 BH |
76 | extern void _tlbivax_bcast(unsigned long address, unsigned int pid, |
77 | unsigned int tsize, unsigned int ind); | |
78 | #else | |
d4e167da BH |
79 | static inline void _tlbivax_bcast(unsigned long address, unsigned int pid, |
80 | unsigned int tsize, unsigned int ind) | |
2a4aca11 BH |
81 | { |
82 | BUG(); | |
83 | } | |
25d21ad6 | 84 | #endif |
2a4aca11 BH |
85 | |
86 | #else /* CONFIG_PPC_MMU_NOHASH */ | |
87 | ||
ee4f2ea4 | 88 | extern void hash_preload(struct mm_struct *mm, unsigned long ea, |
34eb138e | 89 | bool is_exec, unsigned long trap); |
ee4f2ea4 BH |
90 | |
91 | ||
2a4aca11 BH |
92 | extern void _tlbie(unsigned long address); |
93 | extern void _tlbia(void); | |
94 | ||
95 | #endif /* CONFIG_PPC_MMU_NOHASH */ | |
96 | ||
ab1f9dac | 97 | #ifdef CONFIG_PPC32 |
19f5465e | 98 | |
14cf11af | 99 | extern void mapin_ram(void); |
7c5c4325 | 100 | extern void setbat(int index, unsigned long virt, phys_addr_t phys, |
5dd4e4f6 | 101 | unsigned int size, pgprot_t prot); |
14cf11af PM |
102 | |
103 | extern int __map_without_bats; | |
14cf11af PM |
104 | extern unsigned int rtas_data, rtas_size; |
105 | ||
8e561e7e DG |
106 | struct hash_pte; |
107 | extern struct hash_pte *Hash, *Hash_end; | |
14cf11af | 108 | extern unsigned long Hash_size, Hash_mask; |
215b8237 | 109 | extern u8 early_hash[]; |
32a74949 BH |
110 | |
111 | #endif /* CONFIG_PPC32 */ | |
112 | ||
800fc3ee | 113 | extern unsigned long ioremap_bot; |
ab1f9dac | 114 | extern unsigned long __max_low_memory; |
09b5e63f | 115 | extern phys_addr_t __initial_memory_limit_addr; |
2bf3016f SR |
116 | extern phys_addr_t total_memory; |
117 | extern phys_addr_t total_lowmem; | |
99c62dd7 | 118 | extern phys_addr_t memstart_addr; |
d7917ba7 | 119 | extern phys_addr_t lowmem_end_addr; |
14cf11af | 120 | |
de32400d AH |
121 | #ifdef CONFIG_WII |
122 | extern unsigned long wii_hole_start; | |
123 | extern unsigned long wii_hole_size; | |
124 | ||
125 | extern unsigned long wii_mmu_mapin_mem2(unsigned long top); | |
126 | extern void wii_memory_fixups(void); | |
127 | #endif | |
128 | ||
14cf11af PM |
129 | /* ...and now those things that may be slightly different between processor |
130 | * architectures. -- Dan | |
131 | */ | |
a372acfa | 132 | #ifdef CONFIG_PPC32 |
14cf11af | 133 | extern void MMU_init_hw(void); |
72f208c6 | 134 | void MMU_init_hw_patch(void); |
14e609d6 | 135 | unsigned long mmu_mapin_ram(unsigned long base, unsigned long top); |
a372acfa | 136 | #endif |
14cf11af | 137 | |
a372acfa | 138 | #ifdef CONFIG_PPC_FSL_BOOK3E |
eba5de8d SW |
139 | extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx, |
140 | bool dryrun); | |
1dc91c3e KG |
141 | extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, |
142 | phys_addr_t phys); | |
55fd766b | 143 | #ifdef CONFIG_PPC32 |
14cf11af | 144 | extern void adjust_total_lowmem(void); |
78a235ef | 145 | extern int switch_to_as1(void); |
0be7d969 | 146 | extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu); |
55fd766b | 147 | #endif |
78f62237 | 148 | extern void loadcam_entry(unsigned int index); |
d9e1831a | 149 | extern void loadcam_multi(int first_idx, int num, int tmp_idx); |
78f62237 KG |
150 | |
151 | struct tlbcam { | |
152 | u32 MAS0; | |
153 | u32 MAS1; | |
154 | unsigned long MAS2; | |
155 | u32 MAS3; | |
156 | u32 MAS7; | |
157 | }; | |
14cf11af | 158 | #endif |
3084cdb7 | 159 | |
d7cceda9 | 160 | #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_FSL_BOOKE) || defined(CONFIG_PPC_8xx) |
3084cdb7 CL |
161 | /* 6xx have BATS */ |
162 | /* FSL_BOOKE have TLBCAM */ | |
4badd43a | 163 | /* 8xx have LTLB */ |
3084cdb7 CL |
164 | phys_addr_t v_block_mapped(unsigned long va); |
165 | unsigned long p_block_mapped(phys_addr_t pa); | |
166 | #else | |
167 | static inline phys_addr_t v_block_mapped(unsigned long va) { return 0; } | |
168 | static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; } | |
169 | #endif | |
63b2bc61 | 170 | |
d5f17ee9 | 171 | #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx) |
63b2bc61 CL |
172 | void mmu_mark_initmem_nx(void); |
173 | void mmu_mark_rodata_ro(void); | |
174 | #else | |
175 | static inline void mmu_mark_initmem_nx(void) { } | |
176 | static inline void mmu_mark_rodata_ro(void) { } | |
177 | #endif |