powerpc/mm: Move slb_addr_linit to early_init_mmu
[linux-2.6-block.git] / arch / powerpc / mm / hugetlbpage-hash64.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
883a3e52
DG
2/*
3 * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later)
4 *
5 * Copyright (C) 2003 David Gibson, IBM Corporation.
6 *
7 * Based on the IA-32 version:
8 * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
9 */
10
11#include <linux/mm.h>
12#include <linux/hugetlb.h>
13#include <asm/pgtable.h>
14#include <asm/pgalloc.h>
15#include <asm/cacheflush.h>
16#include <asm/machdep.h>
17
b170bd3d
LZ
18extern long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
19 unsigned long pa, unsigned long rlags,
20 unsigned long vflags, int psize, int ssize);
21
883a3e52 22int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
aefa5688
AK
23 pte_t *ptep, unsigned long trap, unsigned long flags,
24 int ssize, unsigned int shift, unsigned int mmu_psize)
883a3e52 25{
bf9a95f9 26 real_pte_t rpte;
5524a27d 27 unsigned long vpn;
883a3e52 28 unsigned long old_pte, new_pte;
8132cf11 29 unsigned long rflags, pa;
ff31e105 30 long slot, offset;
883a3e52
DG
31
32 BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
33
34 /* Search the Linux page table for a match with va */
5524a27d 35 vpn = hpt_vpn(ea, vsid, ssize);
883a3e52 36
171aa2ca 37 /* At this point, we have a pte (old_pte) which can be used to build
883a3e52
DG
38 * or update an HPTE. There are 2 cases:
39 *
40 * 1. There is a valid (present) pte with no associated HPTE (this is
41 * the most common case)
42 * 2. There is a valid (present) pte with an associated HPTE. The
43 * current values of the pp bits in the HPTE prevent access
44 * because we are doing software DIRTY bit management and the
45 * page is currently not DIRTY.
46 */
47
48
49 do {
50 old_pte = pte_val(*ptep);
171aa2ca 51 /* If PTE busy, retry the access */
945537df 52 if (unlikely(old_pte & H_PAGE_BUSY))
171aa2ca
BH
53 return 0;
54 /* If PTE permissions don't match, take page fault */
ac29c640 55 if (unlikely(!check_pte_access(access, old_pte)))
171aa2ca 56 return 1;
ac29c640 57
171aa2ca
BH
58 /* Try to lock the PTE, add ACCESSED and DIRTY if it was
59 * a write access */
945537df 60 new_pte = old_pte | H_PAGE_BUSY | _PAGE_ACCESSED;
c7d54842 61 if (access & _PAGE_WRITE)
171aa2ca 62 new_pte |= _PAGE_DIRTY;
3910a7f4
ME
63 } while(!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
64
75646c48
AK
65 /* Make sure this is a hugetlb entry */
66 if (old_pte & (H_PAGE_THP_HUGE | _PAGE_DEVMAP))
67 return 0;
68
c6a3c495 69 rflags = htab_convert_pte_flags(new_pte);
ff31e105
AK
70 if (unlikely(mmu_psize == MMU_PAGE_16G))
71 offset = PTRS_PER_PUD;
72 else
73 offset = PTRS_PER_PMD;
74 rpte = __real_pte(__pte(old_pte), ptep, offset);
883a3e52 75
883a3e52
DG
76 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
77 /* No CPU has hugepages but lacks no execute, so we
78 * don't need to worry about that case */
0895ecda 79 rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
883a3e52
DG
80
81 /* Check if pte already has an hpte (case 2) */
945537df 82 if (unlikely(old_pte & H_PAGE_HASHPTE)) {
883a3e52 83 /* There MIGHT be an HPTE for this pte */
bf9a95f9 84 unsigned long gslot;
883a3e52 85
bf9a95f9
RP
86 gslot = pte_get_hash_gslot(vpn, shift, ssize, rpte, 0);
87 if (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, mmu_psize,
7025776e 88 mmu_psize, ssize, flags) == -1)
883a3e52
DG
89 old_pte &= ~_PAGE_HPTEFLAGS;
90 }
91
945537df 92 if (likely(!(old_pte & H_PAGE_HASHPTE))) {
5524a27d 93 unsigned long hash = hpt_hash(vpn, shift, ssize);
883a3e52
DG
94
95 pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
96
883a3e52 97 /* clear HPTE slot informations in new PTE */
945537df 98 new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;
bf680d51 99
b170bd3d
LZ
100 slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,
101 mmu_psize, ssize);
883a3e52 102
b1623e7e
AB
103 /*
104 * Hypervisor failure. Restore old pte and return -1
105 * similar to __hash_page_*
106 */
107 if (unlikely(slot == -2)) {
108 *ptep = __pte(old_pte);
4b8692c0 109 hash_failure_debug(ea, access, vsid, trap, ssize,
d8139ebf 110 mmu_psize, mmu_psize, old_pte);
171aa2ca 111 return -1;
b1623e7e 112 }
883a3e52 113
ff31e105 114 new_pte |= pte_set_hidx(ptep, rpte, 0, slot, offset);
883a3e52
DG
115 }
116
117 /*
118 * No need to use ldarx/stdcx here
119 */
945537df 120 *ptep = __pte(new_pte & ~H_PAGE_BUSY);
171aa2ca 121 return 0;
883a3e52 122}
8ef5cbde
AK
123
124pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma,
125 unsigned long addr, pte_t *ptep)
126{
127 unsigned long pte_val;
128 /*
129 * Clear the _PAGE_PRESENT so that no hardware parallel update is
130 * possible. Also keep the pte_present true so that we don't take
131 * wrong fault.
132 */
133 pte_val = pte_update(vma->vm_mm, addr, ptep,
134 _PAGE_PRESENT, _PAGE_INVALID, 1);
135
136 return __pte(pte_val);
137}
138
139void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr,
140 pte_t *ptep, pte_t old_pte, pte_t pte)
141{
142
143 if (radix_enabled())
144 return radix__huge_ptep_modify_prot_commit(vma, addr, ptep,
145 old_pte, pte);
146 set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
147}