Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 LT |
23 | |
24 | #include <linux/config.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/proc_fs.h> | |
29 | #include <linux/stat.h> | |
30 | #include <linux/sysctl.h> | |
31 | #include <linux/ctype.h> | |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
35 | ||
1da177e4 LT |
36 | #include <asm/processor.h> |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/mmu.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/page.h> | |
41 | #include <asm/types.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/uaccess.h> | |
44 | #include <asm/machdep.h> | |
45 | #include <asm/lmb.h> | |
46 | #include <asm/abs_addr.h> | |
47 | #include <asm/tlbflush.h> | |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
53 | #include <asm/abs_addr.h> | |
54 | #include <asm/sections.h> | |
55 | ||
56 | #ifdef DEBUG | |
57 | #define DBG(fmt...) udbg_printf(fmt) | |
58 | #else | |
59 | #define DBG(fmt...) | |
60 | #endif | |
61 | ||
3c726f8d BH |
62 | #ifdef DEBUG_LOW |
63 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
64 | #else | |
65 | #define DBG_LOW(fmt...) | |
66 | #endif | |
67 | ||
68 | #define KB (1024) | |
69 | #define MB (1024*KB) | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * Note: pte --> Linux PTE | |
73 | * HPTE --> PowerPC Hashed Page Table Entry | |
74 | * | |
75 | * Execution context: | |
76 | * htab_initialize is called with the MMU off (of course), but | |
77 | * the kernel has been copied down to zero so it can directly | |
78 | * reference global data. At this point it is very difficult | |
79 | * to print debug info. | |
80 | * | |
81 | */ | |
82 | ||
83 | #ifdef CONFIG_U3_DART | |
84 | extern unsigned long dart_tablebase; | |
85 | #endif /* CONFIG_U3_DART */ | |
86 | ||
799d6046 PM |
87 | static unsigned long _SDR1; |
88 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
89 | ||
96e28449 DG |
90 | hpte_t *htab_address; |
91 | unsigned long htab_hash_mask; | |
3c726f8d BH |
92 | int mmu_linear_psize = MMU_PAGE_4K; |
93 | int mmu_virtual_psize = MMU_PAGE_4K; | |
94 | #ifdef CONFIG_HUGETLB_PAGE | |
95 | int mmu_huge_psize = MMU_PAGE_16M; | |
96 | unsigned int HPAGE_SHIFT; | |
97 | #endif | |
1da177e4 | 98 | |
3c726f8d BH |
99 | /* There are definitions of page sizes arrays to be used when none |
100 | * is provided by the firmware. | |
101 | */ | |
1da177e4 | 102 | |
3c726f8d BH |
103 | /* Pre-POWER4 CPUs (4k pages only) |
104 | */ | |
105 | struct mmu_psize_def mmu_psize_defaults_old[] = { | |
106 | [MMU_PAGE_4K] = { | |
107 | .shift = 12, | |
108 | .sllp = 0, | |
109 | .penc = 0, | |
110 | .avpnm = 0, | |
111 | .tlbiel = 0, | |
112 | }, | |
113 | }; | |
114 | ||
115 | /* POWER4, GPUL, POWER5 | |
116 | * | |
117 | * Support for 16Mb large pages | |
118 | */ | |
119 | struct mmu_psize_def mmu_psize_defaults_gp[] = { | |
120 | [MMU_PAGE_4K] = { | |
121 | .shift = 12, | |
122 | .sllp = 0, | |
123 | .penc = 0, | |
124 | .avpnm = 0, | |
125 | .tlbiel = 1, | |
126 | }, | |
127 | [MMU_PAGE_16M] = { | |
128 | .shift = 24, | |
129 | .sllp = SLB_VSID_L, | |
130 | .penc = 0, | |
131 | .avpnm = 0x1UL, | |
132 | .tlbiel = 0, | |
133 | }, | |
134 | }; | |
135 | ||
136 | ||
137 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
138 | unsigned long pstart, unsigned long mode, int psize) | |
1da177e4 | 139 | { |
3c726f8d BH |
140 | unsigned long vaddr, paddr; |
141 | unsigned int step, shift; | |
1da177e4 | 142 | unsigned long tmp_mode; |
3c726f8d | 143 | int ret = 0; |
1da177e4 | 144 | |
3c726f8d BH |
145 | shift = mmu_psize_defs[psize].shift; |
146 | step = 1 << shift; | |
1da177e4 | 147 | |
3c726f8d BH |
148 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
149 | vaddr += step, paddr += step) { | |
1da177e4 | 150 | unsigned long vpn, hash, hpteg; |
3c726f8d BH |
151 | unsigned long vsid = get_kernel_vsid(vaddr); |
152 | unsigned long va = (vsid << 28) | (vaddr & 0x0fffffff); | |
1da177e4 | 153 | |
3c726f8d | 154 | vpn = va >> shift; |
1da177e4 LT |
155 | tmp_mode = mode; |
156 | ||
157 | /* Make non-kernel text non-executable */ | |
3c726f8d BH |
158 | if (!in_kernel_text(vaddr)) |
159 | tmp_mode = mode | HPTE_R_N; | |
1da177e4 | 160 | |
3c726f8d | 161 | hash = hpt_hash(va, shift); |
1da177e4 LT |
162 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
163 | ||
3c726f8d BH |
164 | /* The crap below can be cleaned once ppd_md.probe() can |
165 | * set up the hash callbacks, thus we can just used the | |
166 | * normal insert callback here. | |
167 | */ | |
4c55130b | 168 | #ifdef CONFIG_PPC_ISERIES |
799d6046 | 169 | if (_machine == PLATFORM_ISERIES_LPAR) |
3c726f8d BH |
170 | ret = iSeries_hpte_insert(hpteg, va, |
171 | virt_to_abs(paddr), | |
172 | tmp_mode, | |
173 | HPTE_V_BOLTED, | |
174 | psize); | |
4c55130b ME |
175 | else |
176 | #endif | |
1da177e4 | 177 | #ifdef CONFIG_PPC_PSERIES |
799d6046 | 178 | if (_machine & PLATFORM_LPAR) |
1da177e4 | 179 | ret = pSeries_lpar_hpte_insert(hpteg, va, |
3c726f8d BH |
180 | virt_to_abs(paddr), |
181 | tmp_mode, | |
182 | HPTE_V_BOLTED, | |
183 | psize); | |
1da177e4 | 184 | else |
4c55130b ME |
185 | #endif |
186 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1da177e4 | 187 | ret = native_hpte_insert(hpteg, va, |
3c726f8d BH |
188 | virt_to_abs(paddr), |
189 | tmp_mode, HPTE_V_BOLTED, | |
190 | psize); | |
4c55130b | 191 | #endif |
3c726f8d BH |
192 | if (ret < 0) |
193 | break; | |
194 | } | |
195 | return ret < 0 ? ret : 0; | |
196 | } | |
1da177e4 | 197 | |
3c726f8d BH |
198 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
199 | const char *uname, int depth, | |
200 | void *data) | |
201 | { | |
202 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
203 | u32 *prop; | |
204 | unsigned long size = 0; | |
205 | ||
206 | /* We are scanning "cpu" nodes only */ | |
207 | if (type == NULL || strcmp(type, "cpu") != 0) | |
208 | return 0; | |
209 | ||
210 | prop = (u32 *)of_get_flat_dt_prop(node, | |
211 | "ibm,segment-page-sizes", &size); | |
212 | if (prop != NULL) { | |
213 | DBG("Page sizes from device-tree:\n"); | |
214 | size /= 4; | |
215 | cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE); | |
216 | while(size > 0) { | |
217 | unsigned int shift = prop[0]; | |
218 | unsigned int slbenc = prop[1]; | |
219 | unsigned int lpnum = prop[2]; | |
220 | unsigned int lpenc = 0; | |
221 | struct mmu_psize_def *def; | |
222 | int idx = -1; | |
223 | ||
224 | size -= 3; prop += 3; | |
225 | while(size > 0 && lpnum) { | |
226 | if (prop[0] == shift) | |
227 | lpenc = prop[1]; | |
228 | prop += 2; size -= 2; | |
229 | lpnum--; | |
230 | } | |
231 | switch(shift) { | |
232 | case 0xc: | |
233 | idx = MMU_PAGE_4K; | |
234 | break; | |
235 | case 0x10: | |
236 | idx = MMU_PAGE_64K; | |
237 | break; | |
238 | case 0x14: | |
239 | idx = MMU_PAGE_1M; | |
240 | break; | |
241 | case 0x18: | |
242 | idx = MMU_PAGE_16M; | |
243 | cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE; | |
244 | break; | |
245 | case 0x22: | |
246 | idx = MMU_PAGE_16G; | |
247 | break; | |
248 | } | |
249 | if (idx < 0) | |
250 | continue; | |
251 | def = &mmu_psize_defs[idx]; | |
252 | def->shift = shift; | |
253 | if (shift <= 23) | |
254 | def->avpnm = 0; | |
255 | else | |
256 | def->avpnm = (1 << (shift - 23)) - 1; | |
257 | def->sllp = slbenc; | |
258 | def->penc = lpenc; | |
259 | /* We don't know for sure what's up with tlbiel, so | |
260 | * for now we only set it for 4K and 64K pages | |
261 | */ | |
262 | if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K) | |
263 | def->tlbiel = 1; | |
264 | else | |
265 | def->tlbiel = 0; | |
266 | ||
267 | DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, " | |
268 | "tlbiel=%d, penc=%d\n", | |
269 | idx, shift, def->sllp, def->avpnm, def->tlbiel, | |
270 | def->penc); | |
1da177e4 | 271 | } |
3c726f8d BH |
272 | return 1; |
273 | } | |
274 | return 0; | |
275 | } | |
276 | ||
277 | ||
278 | static void __init htab_init_page_sizes(void) | |
279 | { | |
280 | int rc; | |
281 | ||
282 | /* Default to 4K pages only */ | |
283 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
284 | sizeof(mmu_psize_defaults_old)); | |
285 | ||
286 | /* | |
287 | * Try to find the available page sizes in the device-tree | |
288 | */ | |
289 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
290 | if (rc != 0) /* Found */ | |
291 | goto found; | |
292 | ||
293 | /* | |
294 | * Not in the device-tree, let's fallback on known size | |
295 | * list for 16M capable GP & GR | |
296 | */ | |
799d6046 | 297 | if ((_machine != PLATFORM_ISERIES_LPAR) && |
3c726f8d BH |
298 | cpu_has_feature(CPU_FTR_16M_PAGE)) |
299 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, | |
300 | sizeof(mmu_psize_defaults_gp)); | |
301 | found: | |
302 | /* | |
303 | * Pick a size for the linear mapping. Currently, we only support | |
304 | * 16M, 1M and 4K which is the default | |
305 | */ | |
306 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
307 | mmu_linear_psize = MMU_PAGE_16M; | |
308 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
309 | mmu_linear_psize = MMU_PAGE_1M; | |
310 | ||
311 | /* | |
312 | * Pick a size for the ordinary pages. Default is 4K, we support | |
313 | * 64K if cache inhibited large pages are supported by the | |
314 | * processor | |
315 | */ | |
316 | #ifdef CONFIG_PPC_64K_PAGES | |
317 | if (mmu_psize_defs[MMU_PAGE_64K].shift && | |
318 | cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) | |
319 | mmu_virtual_psize = MMU_PAGE_64K; | |
320 | #endif | |
321 | ||
322 | printk(KERN_INFO "Page orders: linear mapping = %d, others = %d\n", | |
323 | mmu_psize_defs[mmu_linear_psize].shift, | |
324 | mmu_psize_defs[mmu_virtual_psize].shift); | |
325 | ||
326 | #ifdef CONFIG_HUGETLB_PAGE | |
327 | /* Init large page size. Currently, we pick 16M or 1M depending | |
328 | * on what is available | |
329 | */ | |
330 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
331 | mmu_huge_psize = MMU_PAGE_16M; | |
7d24f0b8 DG |
332 | /* With 4k/4level pagetables, we can't (for now) cope with a |
333 | * huge page size < PMD_SIZE */ | |
3c726f8d BH |
334 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) |
335 | mmu_huge_psize = MMU_PAGE_1M; | |
336 | ||
337 | /* Calculate HPAGE_SHIFT and sanity check it */ | |
7d24f0b8 DG |
338 | if (mmu_psize_defs[mmu_huge_psize].shift > MIN_HUGEPTE_SHIFT && |
339 | mmu_psize_defs[mmu_huge_psize].shift < SID_SHIFT) | |
3c726f8d BH |
340 | HPAGE_SHIFT = mmu_psize_defs[mmu_huge_psize].shift; |
341 | else | |
342 | HPAGE_SHIFT = 0; /* No huge pages dude ! */ | |
343 | #endif /* CONFIG_HUGETLB_PAGE */ | |
344 | } | |
345 | ||
346 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
347 | const char *uname, int depth, | |
348 | void *data) | |
349 | { | |
350 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
351 | u32 *prop; | |
352 | ||
353 | /* We are scanning "cpu" nodes only */ | |
354 | if (type == NULL || strcmp(type, "cpu") != 0) | |
355 | return 0; | |
356 | ||
357 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL); | |
358 | if (prop != NULL) { | |
359 | /* pft_size[0] is the NUMA CEC cookie */ | |
360 | ppc64_pft_size = prop[1]; | |
361 | return 1; | |
1da177e4 | 362 | } |
3c726f8d | 363 | return 0; |
1da177e4 LT |
364 | } |
365 | ||
3c726f8d | 366 | static unsigned long __init htab_get_table_size(void) |
3eac8c69 | 367 | { |
799d6046 | 368 | unsigned long mem_size, rnd_mem_size, pteg_count; |
3eac8c69 | 369 | |
3c726f8d BH |
370 | /* If hash size isn't already provided by the platform, we try to |
371 | * retreive it from the device-tree. If it's not there neither, we | |
372 | * calculate it now based on the total RAM size | |
3eac8c69 | 373 | */ |
3c726f8d BH |
374 | if (ppc64_pft_size == 0) |
375 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
376 | if (ppc64_pft_size) |
377 | return 1UL << ppc64_pft_size; | |
378 | ||
379 | /* round mem_size up to next power of 2 */ | |
799d6046 PM |
380 | mem_size = lmb_phys_mem_size(); |
381 | rnd_mem_size = 1UL << __ilog2(mem_size); | |
382 | if (rnd_mem_size < mem_size) | |
3eac8c69 PM |
383 | rnd_mem_size <<= 1; |
384 | ||
385 | /* # pages / 2 */ | |
386 | pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11); | |
387 | ||
388 | return pteg_count << 7; | |
389 | } | |
390 | ||
54b79248 MK |
391 | #ifdef CONFIG_MEMORY_HOTPLUG |
392 | void create_section_mapping(unsigned long start, unsigned long end) | |
393 | { | |
394 | BUG_ON(htab_bolt_mapping(start, end, start, | |
395 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX, | |
396 | mmu_linear_psize)); | |
397 | } | |
398 | #endif /* CONFIG_MEMORY_HOTPLUG */ | |
399 | ||
1da177e4 LT |
400 | void __init htab_initialize(void) |
401 | { | |
402 | unsigned long table, htab_size_bytes; | |
403 | unsigned long pteg_count; | |
404 | unsigned long mode_rw; | |
1da177e4 | 405 | unsigned long base = 0, size = 0; |
3c726f8d BH |
406 | int i; |
407 | ||
1da177e4 LT |
408 | extern unsigned long tce_alloc_start, tce_alloc_end; |
409 | ||
410 | DBG(" -> htab_initialize()\n"); | |
411 | ||
3c726f8d BH |
412 | /* Initialize page sizes */ |
413 | htab_init_page_sizes(); | |
414 | ||
1da177e4 LT |
415 | /* |
416 | * Calculate the required size of the htab. We want the number of | |
417 | * PTEGs to equal one half the number of real pages. | |
418 | */ | |
3c726f8d | 419 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
420 | pteg_count = htab_size_bytes >> 7; |
421 | ||
1da177e4 LT |
422 | htab_hash_mask = pteg_count - 1; |
423 | ||
799d6046 | 424 | if (platform_is_lpar()) { |
1da177e4 LT |
425 | /* Using a hypervisor which owns the htab */ |
426 | htab_address = NULL; | |
427 | _SDR1 = 0; | |
428 | } else { | |
429 | /* Find storage for the HPT. Must be contiguous in | |
430 | * the absolute address space. | |
431 | */ | |
432 | table = lmb_alloc(htab_size_bytes, htab_size_bytes); | |
3c726f8d | 433 | BUG_ON(table == 0); |
1da177e4 LT |
434 | |
435 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
436 | htab_size_bytes); | |
437 | ||
1da177e4 LT |
438 | htab_address = abs_to_virt(table); |
439 | ||
440 | /* htab absolute addr + encoded htabsize */ | |
441 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
442 | ||
443 | /* Initialize the HPT with no entries */ | |
444 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 PM |
445 | |
446 | /* Set SDR1 */ | |
447 | mtspr(SPRN_SDR1, _SDR1); | |
1da177e4 LT |
448 | } |
449 | ||
515bae9c | 450 | mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX; |
1da177e4 LT |
451 | |
452 | /* On U3 based machines, we need to reserve the DART area and | |
453 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
454 | * cacheable later on | |
455 | */ | |
1da177e4 LT |
456 | |
457 | /* create bolted the linear mapping in the hash table */ | |
458 | for (i=0; i < lmb.memory.cnt; i++) { | |
180379dc | 459 | base = lmb.memory.region[i].base + KERNELBASE; |
1da177e4 LT |
460 | size = lmb.memory.region[i].size; |
461 | ||
462 | DBG("creating mapping for region: %lx : %lx\n", base, size); | |
463 | ||
464 | #ifdef CONFIG_U3_DART | |
465 | /* Do not map the DART space. Fortunately, it will be aligned | |
3c726f8d BH |
466 | * in such a way that it will not cross two lmb regions and |
467 | * will fit within a single 16Mb page. | |
468 | * The DART space is assumed to be a full 16Mb region even if | |
469 | * we only use 2Mb of that space. We will use more of it later | |
470 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
471 | */ |
472 | DBG("DART base: %lx\n", dart_tablebase); | |
473 | ||
474 | if (dart_tablebase != 0 && dart_tablebase >= base | |
475 | && dart_tablebase < (base + size)) { | |
476 | if (base != dart_tablebase) | |
3c726f8d BH |
477 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
478 | base, mode_rw, | |
479 | mmu_linear_psize)); | |
1da177e4 | 480 | if ((base + size) > (dart_tablebase + 16*MB)) |
3c726f8d BH |
481 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
482 | base + size, | |
483 | dart_tablebase+16*MB, | |
484 | mode_rw, | |
485 | mmu_linear_psize)); | |
1da177e4 LT |
486 | continue; |
487 | } | |
488 | #endif /* CONFIG_U3_DART */ | |
3c726f8d BH |
489 | BUG_ON(htab_bolt_mapping(base, base + size, base, |
490 | mode_rw, mmu_linear_psize)); | |
491 | } | |
1da177e4 LT |
492 | |
493 | /* | |
494 | * If we have a memory_limit and we've allocated TCEs then we need to | |
495 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
496 | * case that the TCEs start below memory_limit. | |
497 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
498 | * for either 4K or 16MB pages. | |
499 | */ | |
500 | if (tce_alloc_start) { | |
501 | tce_alloc_start += KERNELBASE; | |
502 | tce_alloc_end += KERNELBASE; | |
503 | ||
504 | if (base + size >= tce_alloc_start) | |
505 | tce_alloc_start = base + size + 1; | |
506 | ||
3c726f8d BH |
507 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
508 | tce_alloc_start, mode_rw, | |
509 | mmu_linear_psize)); | |
1da177e4 LT |
510 | } |
511 | ||
512 | DBG(" <- htab_initialize()\n"); | |
513 | } | |
514 | #undef KB | |
515 | #undef MB | |
1da177e4 | 516 | |
e597cb32 | 517 | void htab_initialize_secondary(void) |
799d6046 PM |
518 | { |
519 | if (!platform_is_lpar()) | |
520 | mtspr(SPRN_SDR1, _SDR1); | |
521 | } | |
522 | ||
1da177e4 LT |
523 | /* |
524 | * Called by asm hashtable.S for doing lazy icache flush | |
525 | */ | |
526 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
527 | { | |
528 | struct page *page; | |
529 | ||
76c8e25b BH |
530 | if (!pfn_valid(pte_pfn(pte))) |
531 | return pp; | |
532 | ||
1da177e4 LT |
533 | page = pte_page(pte); |
534 | ||
535 | /* page is dirty */ | |
536 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
537 | if (trap == 0x400) { | |
538 | __flush_dcache_icache(page_address(page)); | |
539 | set_bit(PG_arch_1, &page->flags); | |
540 | } else | |
3c726f8d | 541 | pp |= HPTE_R_N; |
1da177e4 LT |
542 | } |
543 | return pp; | |
544 | } | |
545 | ||
546 | /* Result code is: | |
547 | * 0 - handled | |
548 | * 1 - normal page fault | |
549 | * -1 - critical hash insertion error | |
550 | */ | |
551 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap) | |
552 | { | |
553 | void *pgdir; | |
554 | unsigned long vsid; | |
555 | struct mm_struct *mm; | |
556 | pte_t *ptep; | |
1da177e4 | 557 | cpumask_t tmp; |
3c726f8d | 558 | int rc, user_region = 0, local = 0; |
1da177e4 | 559 | |
3c726f8d BH |
560 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
561 | ea, access, trap); | |
1f8d419e | 562 | |
3c726f8d BH |
563 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) { |
564 | DBG_LOW(" out of pgtable range !\n"); | |
565 | return 1; | |
566 | } | |
567 | ||
568 | /* Get region & vsid */ | |
1da177e4 LT |
569 | switch (REGION_ID(ea)) { |
570 | case USER_REGION_ID: | |
571 | user_region = 1; | |
572 | mm = current->mm; | |
3c726f8d BH |
573 | if (! mm) { |
574 | DBG_LOW(" user region with no mm !\n"); | |
1da177e4 | 575 | return 1; |
3c726f8d | 576 | } |
1da177e4 LT |
577 | vsid = get_vsid(mm->context.id, ea); |
578 | break; | |
1da177e4 | 579 | case VMALLOC_REGION_ID: |
1da177e4 LT |
580 | mm = &init_mm; |
581 | vsid = get_kernel_vsid(ea); | |
582 | break; | |
1da177e4 LT |
583 | default: |
584 | /* Not a valid range | |
585 | * Send the problem up to do_page_fault | |
586 | */ | |
587 | return 1; | |
1da177e4 | 588 | } |
3c726f8d | 589 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 590 | |
3c726f8d | 591 | /* Get pgdir */ |
1da177e4 | 592 | pgdir = mm->pgd; |
1da177e4 LT |
593 | if (pgdir == NULL) |
594 | return 1; | |
595 | ||
3c726f8d | 596 | /* Check CPU locality */ |
1da177e4 LT |
597 | tmp = cpumask_of_cpu(smp_processor_id()); |
598 | if (user_region && cpus_equal(mm->cpu_vm_mask, tmp)) | |
599 | local = 1; | |
600 | ||
3c726f8d BH |
601 | /* Handle hugepage regions */ |
602 | if (unlikely(in_hugepage_area(mm->context, ea))) { | |
603 | DBG_LOW(" -> huge page !\n"); | |
cbf52afd | 604 | return hash_huge_page(mm, access, ea, vsid, local, trap); |
3c726f8d BH |
605 | } |
606 | ||
607 | /* Get PTE and page size from page tables */ | |
608 | ptep = find_linux_pte(pgdir, ea); | |
609 | if (ptep == NULL || !pte_present(*ptep)) { | |
610 | DBG_LOW(" no PTE !\n"); | |
611 | return 1; | |
612 | } | |
613 | ||
614 | #ifndef CONFIG_PPC_64K_PAGES | |
615 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
616 | #else | |
617 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
618 | pte_val(*(ptep + PTRS_PER_PTE))); | |
619 | #endif | |
620 | /* Pre-check access permissions (will be re-checked atomically | |
621 | * in __hash_page_XX but this pre-check is a fast path | |
622 | */ | |
623 | if (access & ~pte_val(*ptep)) { | |
624 | DBG_LOW(" no access !\n"); | |
625 | return 1; | |
1da177e4 LT |
626 | } |
627 | ||
3c726f8d BH |
628 | /* Do actual hashing */ |
629 | #ifndef CONFIG_PPC_64K_PAGES | |
630 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, local); | |
631 | #else | |
632 | if (mmu_virtual_psize == MMU_PAGE_64K) | |
633 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local); | |
634 | else | |
635 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, local); | |
636 | #endif /* CONFIG_PPC_64K_PAGES */ | |
637 | ||
638 | #ifndef CONFIG_PPC_64K_PAGES | |
639 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
640 | #else | |
641 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
642 | pte_val(*(ptep + PTRS_PER_PTE))); | |
643 | #endif | |
644 | DBG_LOW(" -> rc=%d\n", rc); | |
645 | return rc; | |
1da177e4 LT |
646 | } |
647 | ||
3c726f8d BH |
648 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
649 | unsigned long access, unsigned long trap) | |
1da177e4 | 650 | { |
3c726f8d BH |
651 | unsigned long vsid; |
652 | void *pgdir; | |
653 | pte_t *ptep; | |
654 | cpumask_t mask; | |
655 | unsigned long flags; | |
656 | int local = 0; | |
657 | ||
658 | /* We don't want huge pages prefaulted for now | |
659 | */ | |
660 | if (unlikely(in_hugepage_area(mm->context, ea))) | |
661 | return; | |
662 | ||
663 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
664 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 665 | |
3c726f8d BH |
666 | /* Get PTE, VSID, access mask */ |
667 | pgdir = mm->pgd; | |
668 | if (pgdir == NULL) | |
669 | return; | |
670 | ptep = find_linux_pte(pgdir, ea); | |
671 | if (!ptep) | |
672 | return; | |
673 | vsid = get_vsid(mm->context.id, ea); | |
674 | ||
675 | /* Hash it in */ | |
676 | local_irq_save(flags); | |
677 | mask = cpumask_of_cpu(smp_processor_id()); | |
678 | if (cpus_equal(mm->cpu_vm_mask, mask)) | |
679 | local = 1; | |
680 | #ifndef CONFIG_PPC_64K_PAGES | |
681 | __hash_page_4K(ea, access, vsid, ptep, trap, local); | |
682 | #else | |
683 | if (mmu_virtual_psize == MMU_PAGE_64K) | |
684 | __hash_page_64K(ea, access, vsid, ptep, trap, local); | |
1da177e4 | 685 | else |
3c726f8d BH |
686 | __hash_page_4K(ea, access, vsid, ptep, trap, local); |
687 | #endif /* CONFIG_PPC_64K_PAGES */ | |
688 | local_irq_restore(flags); | |
689 | } | |
690 | ||
691 | void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int local) | |
692 | { | |
693 | unsigned long hash, index, shift, hidx, slot; | |
694 | ||
695 | DBG_LOW("flush_hash_page(va=%016x)\n", va); | |
696 | pte_iterate_hashed_subpages(pte, psize, va, index, shift) { | |
697 | hash = hpt_hash(va, shift); | |
698 | hidx = __rpte_to_hidx(pte, index); | |
699 | if (hidx & _PTEIDX_SECONDARY) | |
700 | hash = ~hash; | |
701 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
702 | slot += hidx & _PTEIDX_GROUP_IX; | |
703 | DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx); | |
704 | ppc_md.hpte_invalidate(slot, va, psize, local); | |
705 | } pte_iterate_hashed_end(); | |
1da177e4 LT |
706 | } |
707 | ||
61b1a942 | 708 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 709 | { |
3c726f8d | 710 | if (ppc_md.flush_hash_range) |
61b1a942 | 711 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 712 | else { |
1da177e4 | 713 | int i; |
61b1a942 BH |
714 | struct ppc64_tlb_batch *batch = |
715 | &__get_cpu_var(ppc64_tlb_batch); | |
1da177e4 LT |
716 | |
717 | for (i = 0; i < number; i++) | |
3c726f8d BH |
718 | flush_hash_page(batch->vaddr[i], batch->pte[i], |
719 | batch->psize, local); | |
1da177e4 LT |
720 | } |
721 | } | |
722 | ||
723 | static inline void make_bl(unsigned int *insn_addr, void *func) | |
724 | { | |
725 | unsigned long funcp = *((unsigned long *)func); | |
726 | int offset = funcp - (unsigned long)insn_addr; | |
727 | ||
728 | *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc)); | |
729 | flush_icache_range((unsigned long)insn_addr, 4+ | |
730 | (unsigned long)insn_addr); | |
731 | } | |
732 | ||
733 | /* | |
734 | * low_hash_fault is called when we the low level hash code failed | |
735 | * to instert a PTE due to an hypervisor error | |
736 | */ | |
737 | void low_hash_fault(struct pt_regs *regs, unsigned long address) | |
738 | { | |
739 | if (user_mode(regs)) { | |
740 | siginfo_t info; | |
741 | ||
742 | info.si_signo = SIGBUS; | |
743 | info.si_errno = 0; | |
744 | info.si_code = BUS_ADRERR; | |
745 | info.si_addr = (void __user *)address; | |
746 | force_sig_info(SIGBUS, &info, current); | |
747 | return; | |
748 | } | |
749 | bad_page_fault(regs, address, SIGBUS); | |
750 | } | |
751 | ||
752 | void __init htab_finish_init(void) | |
753 | { | |
754 | extern unsigned int *htab_call_hpte_insert1; | |
755 | extern unsigned int *htab_call_hpte_insert2; | |
756 | extern unsigned int *htab_call_hpte_remove; | |
757 | extern unsigned int *htab_call_hpte_updatepp; | |
758 | ||
3c726f8d BH |
759 | #ifdef CONFIG_PPC_64K_PAGES |
760 | extern unsigned int *ht64_call_hpte_insert1; | |
761 | extern unsigned int *ht64_call_hpte_insert2; | |
762 | extern unsigned int *ht64_call_hpte_remove; | |
763 | extern unsigned int *ht64_call_hpte_updatepp; | |
764 | ||
765 | make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert); | |
766 | make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert); | |
767 | make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove); | |
768 | make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
769 | #endif /* CONFIG_PPC_64K_PAGES */ | |
770 | ||
1da177e4 LT |
771 | make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert); |
772 | make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert); | |
773 | make_bl(htab_call_hpte_remove, ppc_md.hpte_remove); | |
774 | make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
775 | } |