Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
7f142661 | 24 | #define pr_fmt(fmt) "hash-mmu: " fmt |
1da177e4 LT |
25 | #include <linux/spinlock.h> |
26 | #include <linux/errno.h> | |
589ee628 | 27 | #include <linux/sched/mm.h> |
1da177e4 LT |
28 | #include <linux/proc_fs.h> |
29 | #include <linux/stat.h> | |
30 | #include <linux/sysctl.h> | |
66b15db6 | 31 | #include <linux/export.h> |
1da177e4 LT |
32 | #include <linux/ctype.h> |
33 | #include <linux/cache.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/signal.h> | |
95f72d1e | 36 | #include <linux/memblock.h> |
ba12eede | 37 | #include <linux/context_tracking.h> |
5556ecf5 | 38 | #include <linux/libfdt.h> |
1da177e4 | 39 | |
7644d581 | 40 | #include <asm/debugfs.h> |
1da177e4 LT |
41 | #include <asm/processor.h> |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/mmu.h> | |
44 | #include <asm/mmu_context.h> | |
45 | #include <asm/page.h> | |
46 | #include <asm/types.h> | |
7c0f6ba6 | 47 | #include <linux/uaccess.h> |
1da177e4 | 48 | #include <asm/machdep.h> |
d9b2b2a2 | 49 | #include <asm/prom.h> |
1da177e4 LT |
50 | #include <asm/tlbflush.h> |
51 | #include <asm/io.h> | |
52 | #include <asm/eeh.h> | |
53 | #include <asm/tlb.h> | |
54 | #include <asm/cacheflush.h> | |
55 | #include <asm/cputable.h> | |
1da177e4 | 56 | #include <asm/sections.h> |
be3ebfe8 | 57 | #include <asm/copro.h> |
aa39be09 | 58 | #include <asm/udbg.h> |
b68a70c4 | 59 | #include <asm/code-patching.h> |
3ccc00a7 | 60 | #include <asm/fadump.h> |
f5339277 | 61 | #include <asm/firmware.h> |
bc2a9408 | 62 | #include <asm/tm.h> |
cfcb3d80 | 63 | #include <asm/trace.h> |
166dd7d3 | 64 | #include <asm/ps3.h> |
94171b19 | 65 | #include <asm/pte-walk.h> |
1da177e4 LT |
66 | |
67 | #ifdef DEBUG | |
68 | #define DBG(fmt...) udbg_printf(fmt) | |
69 | #else | |
70 | #define DBG(fmt...) | |
71 | #endif | |
72 | ||
3c726f8d BH |
73 | #ifdef DEBUG_LOW |
74 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
75 | #else | |
76 | #define DBG_LOW(fmt...) | |
77 | #endif | |
78 | ||
79 | #define KB (1024) | |
80 | #define MB (1024*KB) | |
658013e9 | 81 | #define GB (1024L*MB) |
3c726f8d | 82 | |
1da177e4 LT |
83 | /* |
84 | * Note: pte --> Linux PTE | |
85 | * HPTE --> PowerPC Hashed Page Table Entry | |
86 | * | |
87 | * Execution context: | |
88 | * htab_initialize is called with the MMU off (of course), but | |
89 | * the kernel has been copied down to zero so it can directly | |
90 | * reference global data. At this point it is very difficult | |
91 | * to print debug info. | |
92 | * | |
93 | */ | |
94 | ||
799d6046 PM |
95 | static unsigned long _SDR1; |
96 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 97 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 98 | |
0eeede0c PM |
99 | u8 hpte_page_sizes[1 << LP_BITS]; |
100 | EXPORT_SYMBOL_GPL(hpte_page_sizes); | |
101 | ||
8e561e7e | 102 | struct hash_pte *htab_address; |
337a7128 | 103 | unsigned long htab_size_bytes; |
96e28449 | 104 | unsigned long htab_hash_mask; |
4ab79aa8 | 105 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 106 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 107 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 108 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 109 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
110 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
111 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
112 | #endif | |
bf72aeba | 113 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 114 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 115 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 116 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 117 | u16 mmu_slb_size = 64; |
4ab79aa8 | 118 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
119 | #ifdef CONFIG_PPC_64K_PAGES |
120 | int mmu_ci_restrictions; | |
121 | #endif | |
370a908d BH |
122 | #ifdef CONFIG_DEBUG_PAGEALLOC |
123 | static u8 *linear_map_hash_slots; | |
124 | static unsigned long linear_map_hash_count; | |
ed166692 | 125 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 126 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
7025776e BH |
127 | struct mmu_hash_ops mmu_hash_ops; |
128 | EXPORT_SYMBOL(mmu_hash_ops); | |
1da177e4 | 129 | |
3c726f8d BH |
130 | /* There are definitions of page sizes arrays to be used when none |
131 | * is provided by the firmware. | |
132 | */ | |
1da177e4 | 133 | |
3c726f8d BH |
134 | /* Pre-POWER4 CPUs (4k pages only) |
135 | */ | |
09de9ff8 | 136 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
137 | [MMU_PAGE_4K] = { |
138 | .shift = 12, | |
139 | .sllp = 0, | |
b1022fbd | 140 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
141 | .avpnm = 0, |
142 | .tlbiel = 0, | |
143 | }, | |
144 | }; | |
145 | ||
146 | /* POWER4, GPUL, POWER5 | |
147 | * | |
148 | * Support for 16Mb large pages | |
149 | */ | |
09de9ff8 | 150 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
151 | [MMU_PAGE_4K] = { |
152 | .shift = 12, | |
153 | .sllp = 0, | |
b1022fbd | 154 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
155 | .avpnm = 0, |
156 | .tlbiel = 1, | |
157 | }, | |
158 | [MMU_PAGE_16M] = { | |
159 | .shift = 24, | |
160 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
161 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
162 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
163 | .avpnm = 0x1UL, |
164 | .tlbiel = 0, | |
165 | }, | |
166 | }; | |
167 | ||
dc47c0c1 AK |
168 | /* |
169 | * 'R' and 'C' update notes: | |
170 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
171 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
172 | * that we use in that case will not update C | |
173 | * - The above is however not a problem, because we also don't do that | |
174 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
175 | * do the right thing and thus we don't have the race I described earlier | |
176 | * | |
177 | * - Under bare metal, we do have the race, so we need R and C set | |
178 | * - We make sure R is always set and never lost | |
179 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
180 | */ | |
c6a3c495 | 181 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 182 | { |
c6a3c495 | 183 | unsigned long rflags = 0; |
bc033b63 BH |
184 | |
185 | /* _PAGE_EXEC -> NOEXEC */ | |
186 | if ((pteflags & _PAGE_EXEC) == 0) | |
187 | rflags |= HPTE_R_N; | |
c6a3c495 | 188 | /* |
e58e87ad | 189 | * PPP bits: |
1ec3f937 | 190 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
191 | * kernel RW areas are mapped with PPP=0b000 |
192 | * User area is mapped with PPP=0b010 for read/write | |
193 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 194 | */ |
e58e87ad AK |
195 | if (pteflags & _PAGE_PRIVILEGED) { |
196 | /* | |
197 | * Kernel read only mapped with ppp bits 0b110 | |
198 | */ | |
984d7a1e AK |
199 | if (!(pteflags & _PAGE_WRITE)) { |
200 | if (mmu_has_feature(MMU_FTR_KERNEL_RO)) | |
201 | rflags |= (HPTE_R_PP0 | 0x2); | |
202 | else | |
203 | rflags |= 0x3; | |
204 | } | |
e58e87ad | 205 | } else { |
c7d54842 AK |
206 | if (pteflags & _PAGE_RWX) |
207 | rflags |= 0x2; | |
208 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
209 | rflags |= 0x1; |
210 | } | |
c8c06f5a | 211 | /* |
dc47c0c1 AK |
212 | * We can't allow hardware to update hpte bits. Hence always |
213 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 214 | */ |
e568006b | 215 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
216 | |
217 | if (pteflags & _PAGE_DIRTY) | |
218 | rflags |= HPTE_R_C; | |
40e8550a AK |
219 | /* |
220 | * Add in WIG bits | |
221 | */ | |
30bda41a AK |
222 | |
223 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 224 | rflags |= HPTE_R_I; |
e568006b | 225 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 226 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
227 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
228 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
229 | else | |
230 | /* | |
231 | * Add memory coherence if cache inhibited is not set | |
232 | */ | |
233 | rflags |= HPTE_R_M; | |
40e8550a AK |
234 | |
235 | return rflags; | |
bc033b63 | 236 | } |
3c726f8d BH |
237 | |
238 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 239 | unsigned long pstart, unsigned long prot, |
1189be65 | 240 | int psize, int ssize) |
1da177e4 | 241 | { |
3c726f8d BH |
242 | unsigned long vaddr, paddr; |
243 | unsigned int step, shift; | |
3c726f8d | 244 | int ret = 0; |
1da177e4 | 245 | |
3c726f8d BH |
246 | shift = mmu_psize_defs[psize].shift; |
247 | step = 1 << shift; | |
1da177e4 | 248 | |
bc033b63 BH |
249 | prot = htab_convert_pte_flags(prot); |
250 | ||
251 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
252 | vstart, vend, pstart, prot, psize, ssize); | |
253 | ||
3c726f8d BH |
254 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
255 | vaddr += step, paddr += step) { | |
370a908d | 256 | unsigned long hash, hpteg; |
1189be65 | 257 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 258 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
259 | unsigned long tprot = prot; |
260 | ||
c60ac569 AK |
261 | /* |
262 | * If we hit a bad address return error. | |
263 | */ | |
264 | if (!vsid) | |
265 | return -1; | |
9e88ba4e | 266 | /* Make kernel text executable */ |
549e8152 | 267 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 268 | tprot &= ~HPTE_R_N; |
1da177e4 | 269 | |
b18db0b8 AG |
270 | /* Make kvm guest trampolines executable */ |
271 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
272 | tprot &= ~HPTE_R_N; | |
273 | ||
429d2e83 MS |
274 | /* |
275 | * If relocatable, check if it overlaps interrupt vectors that | |
276 | * are copied down to real 0. For relocatable kernel | |
277 | * (e.g. kdump case) we copy interrupt vectors down to real | |
278 | * address 0. Mark that region as executable. This is | |
279 | * because on p8 system with relocation on exception feature | |
280 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
281 | * in order to execute the interrupt handlers in virtual | |
282 | * mode the vector region need to be marked as executable. | |
283 | */ | |
284 | if ((PHYSICAL_START > MEMORY_START) && | |
285 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
286 | tprot &= ~HPTE_R_N; | |
287 | ||
5524a27d | 288 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
289 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
290 | ||
7025776e BH |
291 | BUG_ON(!mmu_hash_ops.hpte_insert); |
292 | ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, | |
293 | HPTE_V_BOLTED, psize, psize, | |
294 | ssize); | |
c30a4df3 | 295 | |
3c726f8d BH |
296 | if (ret < 0) |
297 | break; | |
e7df0d88 | 298 | |
370a908d | 299 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
300 | if (debug_pagealloc_enabled() && |
301 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
302 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
303 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
304 | } |
305 | return ret < 0 ? ret : 0; | |
306 | } | |
1da177e4 | 307 | |
ed5694a8 | 308 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
309 | int psize, int ssize) |
310 | { | |
311 | unsigned long vaddr; | |
312 | unsigned int step, shift; | |
27828f98 DG |
313 | int rc; |
314 | int ret = 0; | |
f8c8803b BP |
315 | |
316 | shift = mmu_psize_defs[psize].shift; | |
317 | step = 1 << shift; | |
318 | ||
7025776e | 319 | if (!mmu_hash_ops.hpte_removebolted) |
abd0a0e7 | 320 | return -ENODEV; |
f8c8803b | 321 | |
27828f98 | 322 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
7025776e | 323 | rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); |
27828f98 DG |
324 | if (rc == -ENOENT) { |
325 | ret = -ENOENT; | |
326 | continue; | |
327 | } | |
328 | if (rc < 0) | |
329 | return rc; | |
330 | } | |
52db9b44 | 331 | |
27828f98 | 332 | return ret; |
f8c8803b BP |
333 | } |
334 | ||
faf78829 OH |
335 | static bool disable_1tb_segments = false; |
336 | ||
337 | static int __init parse_disable_1tb_segments(char *p) | |
338 | { | |
339 | disable_1tb_segments = true; | |
340 | return 0; | |
341 | } | |
342 | early_param("disable_1tb_segments", parse_disable_1tb_segments); | |
343 | ||
1189be65 PM |
344 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
345 | const char *uname, int depth, | |
346 | void *data) | |
347 | { | |
9d0c4dfe RH |
348 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
349 | const __be32 *prop; | |
350 | int size = 0; | |
1189be65 PM |
351 | |
352 | /* We are scanning "cpu" nodes only */ | |
353 | if (type == NULL || strcmp(type, "cpu") != 0) | |
354 | return 0; | |
355 | ||
12f04f2b | 356 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
357 | if (prop == NULL) |
358 | return 0; | |
359 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 360 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 361 | DBG("1T segment support detected\n"); |
faf78829 OH |
362 | |
363 | if (disable_1tb_segments) { | |
364 | DBG("1T segments disabled by command line\n"); | |
365 | break; | |
366 | } | |
367 | ||
44ae3ab3 | 368 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 369 | return 1; |
1189be65 | 370 | } |
1189be65 | 371 | } |
44ae3ab3 | 372 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
373 | return 0; |
374 | } | |
375 | ||
b1022fbd AK |
376 | static int __init get_idx_from_shift(unsigned int shift) |
377 | { | |
378 | int idx = -1; | |
379 | ||
380 | switch (shift) { | |
381 | case 0xc: | |
382 | idx = MMU_PAGE_4K; | |
383 | break; | |
384 | case 0x10: | |
385 | idx = MMU_PAGE_64K; | |
386 | break; | |
387 | case 0x14: | |
388 | idx = MMU_PAGE_1M; | |
389 | break; | |
390 | case 0x18: | |
391 | idx = MMU_PAGE_16M; | |
392 | break; | |
393 | case 0x22: | |
394 | idx = MMU_PAGE_16G; | |
395 | break; | |
396 | } | |
397 | return idx; | |
398 | } | |
399 | ||
3c726f8d BH |
400 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
401 | const char *uname, int depth, | |
402 | void *data) | |
403 | { | |
9d0c4dfe RH |
404 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
405 | const __be32 *prop; | |
406 | int size = 0; | |
3c726f8d BH |
407 | |
408 | /* We are scanning "cpu" nodes only */ | |
409 | if (type == NULL || strcmp(type, "cpu") != 0) | |
410 | return 0; | |
411 | ||
12f04f2b | 412 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
413 | if (!prop) |
414 | return 0; | |
415 | ||
416 | pr_info("Page sizes from device-tree:\n"); | |
417 | size /= 4; | |
418 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
419 | while(size > 0) { | |
420 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
421 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
422 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
423 | struct mmu_psize_def *def; | |
424 | int idx, base_idx; | |
425 | ||
426 | size -= 3; prop += 3; | |
427 | base_idx = get_idx_from_shift(base_shift); | |
428 | if (base_idx < 0) { | |
429 | /* skip the pte encoding also */ | |
430 | prop += lpnum * 2; size -= lpnum * 2; | |
431 | continue; | |
432 | } | |
433 | def = &mmu_psize_defs[base_idx]; | |
434 | if (base_idx == MMU_PAGE_16M) | |
435 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
436 | ||
437 | def->shift = base_shift; | |
438 | if (base_shift <= 23) | |
439 | def->avpnm = 0; | |
440 | else | |
441 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
442 | def->sllp = slbenc; | |
443 | /* | |
444 | * We don't know for sure what's up with tlbiel, so | |
445 | * for now we only set it for 4K and 64K pages | |
446 | */ | |
447 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
448 | def->tlbiel = 1; | |
449 | else | |
450 | def->tlbiel = 0; | |
451 | ||
452 | while (size > 0 && lpnum) { | |
453 | unsigned int shift = be32_to_cpu(prop[0]); | |
454 | int penc = be32_to_cpu(prop[1]); | |
455 | ||
456 | prop += 2; size -= 2; | |
457 | lpnum--; | |
458 | ||
459 | idx = get_idx_from_shift(shift); | |
460 | if (idx < 0) | |
b1022fbd | 461 | continue; |
9e34992a ME |
462 | |
463 | if (penc == -1) | |
464 | pr_err("Invalid penc for base_shift=%d " | |
465 | "shift=%d\n", base_shift, shift); | |
466 | ||
467 | def->penc[idx] = penc; | |
468 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
469 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
470 | base_shift, shift, def->sllp, | |
471 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 472 | } |
3c726f8d | 473 | } |
9e34992a ME |
474 | |
475 | return 1; | |
3c726f8d BH |
476 | } |
477 | ||
e16a9c09 | 478 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
479 | /* Scan for 16G memory blocks that have been set aside for huge pages |
480 | * and reserve those blocks for 16G huge pages. | |
481 | */ | |
482 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
483 | const char *uname, int depth, | |
484 | void *data) { | |
9d0c4dfe RH |
485 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
486 | const __be64 *addr_prop; | |
487 | const __be32 *page_count_prop; | |
658013e9 JT |
488 | unsigned int expected_pages; |
489 | long unsigned int phys_addr; | |
490 | long unsigned int block_size; | |
491 | ||
492 | /* We are scanning "memory" nodes only */ | |
493 | if (type == NULL || strcmp(type, "memory") != 0) | |
494 | return 0; | |
495 | ||
496 | /* This property is the log base 2 of the number of virtual pages that | |
497 | * will represent this memory block. */ | |
498 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
499 | if (page_count_prop == NULL) | |
500 | return 0; | |
12f04f2b | 501 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
502 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
503 | if (addr_prop == NULL) | |
504 | return 0; | |
12f04f2b AB |
505 | phys_addr = be64_to_cpu(addr_prop[0]); |
506 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
507 | if (block_size != (16 * GB)) |
508 | return 0; | |
509 | printk(KERN_INFO "Huge page(16GB) memory: " | |
510 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
511 | phys_addr, block_size, expected_pages); | |
23493c12 | 512 | if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { |
95f72d1e | 513 | memblock_reserve(phys_addr, block_size * expected_pages); |
79cc38de | 514 | pseries_add_gpage(phys_addr, block_size, expected_pages); |
4792adba | 515 | } |
658013e9 JT |
516 | return 0; |
517 | } | |
e16a9c09 | 518 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 519 | |
b1022fbd AK |
520 | static void mmu_psize_set_default_penc(void) |
521 | { | |
522 | int bpsize, apsize; | |
523 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
524 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
525 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
526 | } | |
527 | ||
9048e648 AG |
528 | #ifdef CONFIG_PPC_64K_PAGES |
529 | ||
530 | static bool might_have_hea(void) | |
531 | { | |
532 | /* | |
533 | * The HEA ethernet adapter requires awareness of the | |
534 | * GX bus. Without that awareness we can easily assume | |
535 | * we will never see an HEA ethernet device. | |
536 | */ | |
537 | #ifdef CONFIG_IBMEBUS | |
2b4e3ad8 | 538 | return !cpu_has_feature(CPU_FTR_ARCH_207S) && |
08bf75ba | 539 | firmware_has_feature(FW_FEATURE_SPLPAR); |
9048e648 AG |
540 | #else |
541 | return false; | |
542 | #endif | |
543 | } | |
544 | ||
545 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
546 | ||
bacf9cf8 | 547 | static void __init htab_scan_page_sizes(void) |
3c726f8d BH |
548 | { |
549 | int rc; | |
550 | ||
b1022fbd AK |
551 | /* se the invalid penc to -1 */ |
552 | mmu_psize_set_default_penc(); | |
553 | ||
3c726f8d BH |
554 | /* Default to 4K pages only */ |
555 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
556 | sizeof(mmu_psize_defaults_old)); | |
557 | ||
558 | /* | |
559 | * Try to find the available page sizes in the device-tree | |
560 | */ | |
561 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
b8f1b4f8 | 562 | if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { |
bacf9cf8 ME |
563 | /* |
564 | * Nothing in the device-tree, but the CPU supports 16M pages, | |
565 | * so let's fallback on a known size list for 16M capable CPUs. | |
566 | */ | |
3c726f8d BH |
567 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
568 | sizeof(mmu_psize_defaults_gp)); | |
bacf9cf8 ME |
569 | } |
570 | ||
571 | #ifdef CONFIG_HUGETLB_PAGE | |
572 | /* Reserve 16G huge page memory sections for huge pages */ | |
573 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
574 | #endif /* CONFIG_HUGETLB_PAGE */ | |
575 | } | |
576 | ||
0eeede0c PM |
577 | /* |
578 | * Fill in the hpte_page_sizes[] array. | |
579 | * We go through the mmu_psize_defs[] array looking for all the | |
580 | * supported base/actual page size combinations. Each combination | |
581 | * has a unique pagesize encoding (penc) value in the low bits of | |
582 | * the LP field of the HPTE. For actual page sizes less than 1MB, | |
583 | * some of the upper LP bits are used for RPN bits, meaning that | |
584 | * we need to fill in several entries in hpte_page_sizes[]. | |
585 | * | |
586 | * In diagrammatic form, with r = RPN bits and z = page size bits: | |
587 | * PTE LP actual page size | |
588 | * rrrr rrrz >=8KB | |
589 | * rrrr rrzz >=16KB | |
590 | * rrrr rzzz >=32KB | |
591 | * rrrr zzzz >=64KB | |
592 | * ... | |
593 | * | |
594 | * The zzzz bits are implementation-specific but are chosen so that | |
595 | * no encoding for a larger page size uses the same value in its | |
596 | * low-order N bits as the encoding for the 2^(12+N) byte page size | |
597 | * (if it exists). | |
598 | */ | |
599 | static void init_hpte_page_sizes(void) | |
600 | { | |
601 | long int ap, bp; | |
602 | long int shift, penc; | |
603 | ||
604 | for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { | |
605 | if (!mmu_psize_defs[bp].shift) | |
606 | continue; /* not a supported page size */ | |
607 | for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { | |
608 | penc = mmu_psize_defs[bp].penc[ap]; | |
609 | if (penc == -1) | |
610 | continue; | |
611 | shift = mmu_psize_defs[ap].shift - LP_SHIFT; | |
612 | if (shift <= 0) | |
613 | continue; /* should never happen */ | |
614 | /* | |
615 | * For page sizes less than 1MB, this loop | |
616 | * replicates the entry for all possible values | |
617 | * of the rrrr bits. | |
618 | */ | |
619 | while (penc < (1 << LP_BITS)) { | |
620 | hpte_page_sizes[penc] = (ap << 4) | bp; | |
621 | penc += 1 << shift; | |
622 | } | |
623 | } | |
624 | } | |
625 | } | |
626 | ||
bacf9cf8 ME |
627 | static void __init htab_init_page_sizes(void) |
628 | { | |
0eeede0c PM |
629 | init_hpte_page_sizes(); |
630 | ||
e7df0d88 JK |
631 | if (!debug_pagealloc_enabled()) { |
632 | /* | |
633 | * Pick a size for the linear mapping. Currently, we only | |
634 | * support 16M, 1M and 4K which is the default | |
635 | */ | |
636 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
637 | mmu_linear_psize = MMU_PAGE_16M; | |
638 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
639 | mmu_linear_psize = MMU_PAGE_1M; | |
640 | } | |
3c726f8d | 641 | |
bf72aeba | 642 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
643 | /* |
644 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
645 | * 64K for user mappings and vmalloc if supported by the processor. |
646 | * We only use 64k for ioremap if the processor | |
647 | * (and firmware) support cache-inhibited large pages. | |
648 | * If not, we use 4k and set mmu_ci_restrictions so that | |
649 | * hash_page knows to switch processes that use cache-inhibited | |
650 | * mappings to 4k pages. | |
3c726f8d | 651 | */ |
bf72aeba | 652 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 653 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 654 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
655 | if (mmu_linear_psize == MMU_PAGE_4K) |
656 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 657 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 658 | /* |
9048e648 AG |
659 | * When running on pSeries using 64k pages for ioremap |
660 | * would stop us accessing the HEA ethernet. So if we | |
661 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 662 | */ |
2b4e3ad8 | 663 | if (!might_have_hea()) |
cfe666b1 PM |
664 | mmu_io_psize = MMU_PAGE_64K; |
665 | } else | |
bf72aeba PM |
666 | mmu_ci_restrictions = 1; |
667 | } | |
370a908d | 668 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 669 | |
cec08e7a BH |
670 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
671 | /* We try to use 16M pages for vmemmap if that is supported | |
672 | * and we have at least 1G of RAM at boot | |
673 | */ | |
674 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 675 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
676 | mmu_vmemmap_psize = MMU_PAGE_16M; |
677 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
678 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
679 | else | |
680 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
681 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
682 | ||
bf72aeba | 683 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
684 | "virtual = %d, io = %d" |
685 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
686 | ", vmemmap = %d" | |
687 | #endif | |
688 | "\n", | |
3c726f8d | 689 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 690 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
691 | mmu_psize_defs[mmu_io_psize].shift |
692 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
693 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
694 | #endif | |
695 | ); | |
3c726f8d BH |
696 | } |
697 | ||
698 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
699 | const char *uname, int depth, | |
700 | void *data) | |
701 | { | |
9d0c4dfe RH |
702 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
703 | const __be32 *prop; | |
3c726f8d BH |
704 | |
705 | /* We are scanning "cpu" nodes only */ | |
706 | if (type == NULL || strcmp(type, "cpu") != 0) | |
707 | return 0; | |
708 | ||
12f04f2b | 709 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
710 | if (prop != NULL) { |
711 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 712 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 713 | return 1; |
1da177e4 | 714 | } |
3c726f8d | 715 | return 0; |
1da177e4 LT |
716 | } |
717 | ||
5c3c7ede | 718 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 719 | { |
5c3c7ede DG |
720 | unsigned memshift = __ilog2(mem_size); |
721 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
722 | unsigned pteg_shift; | |
723 | ||
724 | /* round mem_size up to next power of 2 */ | |
725 | if ((1UL << memshift) < mem_size) | |
726 | memshift += 1; | |
3eac8c69 | 727 | |
5c3c7ede DG |
728 | /* aim for 2 pages / pteg */ |
729 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 730 | |
5c3c7ede DG |
731 | /* |
732 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
733 | * size permitted by the architecture. | |
734 | */ | |
735 | return max(pteg_shift + 7, 18U); | |
736 | } | |
737 | ||
738 | static unsigned long __init htab_get_table_size(void) | |
739 | { | |
3c726f8d | 740 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 741 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 742 | * calculate it now based on the total RAM size |
3eac8c69 | 743 | */ |
3c726f8d BH |
744 | if (ppc64_pft_size == 0) |
745 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
746 | if (ppc64_pft_size) |
747 | return 1UL << ppc64_pft_size; | |
748 | ||
5c3c7ede | 749 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
750 | } |
751 | ||
54b79248 | 752 | #ifdef CONFIG_MEMORY_HOTPLUG |
438cc81a DG |
753 | void resize_hpt_for_hotplug(unsigned long new_mem_size) |
754 | { | |
755 | unsigned target_hpt_shift; | |
756 | ||
757 | if (!mmu_hash_ops.resize_hpt) | |
758 | return; | |
759 | ||
760 | target_hpt_shift = htab_shift_for_mem_size(new_mem_size); | |
761 | ||
762 | /* | |
763 | * To avoid lots of HPT resizes if memory size is fluctuating | |
764 | * across a boundary, we deliberately have some hysterisis | |
765 | * here: we immediately increase the HPT size if the target | |
766 | * shift exceeds the current shift, but we won't attempt to | |
767 | * reduce unless the target shift is at least 2 below the | |
768 | * current shift | |
769 | */ | |
770 | if ((target_hpt_shift > ppc64_pft_size) | |
771 | || (target_hpt_shift < (ppc64_pft_size - 1))) { | |
772 | int rc; | |
773 | ||
774 | rc = mmu_hash_ops.resize_hpt(target_hpt_shift); | |
775 | if (rc) | |
776 | printk(KERN_WARNING | |
777 | "Unable to resize hash page table to target order %d: %d\n", | |
778 | target_hpt_shift, rc); | |
779 | } | |
780 | } | |
781 | ||
32b53c01 | 782 | int hash__create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 783 | { |
1dace6c6 DG |
784 | int rc = htab_bolt_mapping(start, end, __pa(start), |
785 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
786 | mmu_kernel_ssize); | |
787 | ||
788 | if (rc < 0) { | |
789 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
790 | mmu_kernel_ssize); | |
791 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
792 | } | |
793 | return rc; | |
54b79248 | 794 | } |
f8c8803b | 795 | |
32b53c01 | 796 | int hash__remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 797 | { |
abd0a0e7 DG |
798 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
799 | mmu_kernel_ssize); | |
800 | WARN_ON(rc < 0); | |
801 | return rc; | |
f8c8803b | 802 | } |
54b79248 MK |
803 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
804 | ||
ad410674 AK |
805 | static void update_hid_for_hash(void) |
806 | { | |
807 | unsigned long hid0; | |
808 | unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */ | |
809 | ||
810 | asm volatile("ptesync": : :"memory"); | |
811 | /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */ | |
812 | asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) | |
813 | : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory"); | |
814 | asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory"); | |
0428491c BS |
815 | trace_tlbie(0, 0, rb, 0, 2, 0, 0); |
816 | ||
ad410674 AK |
817 | /* |
818 | * now switch the HID | |
819 | */ | |
820 | hid0 = mfspr(SPRN_HID0); | |
821 | hid0 &= ~HID0_POWER9_RADIX; | |
822 | mtspr(SPRN_HID0, hid0); | |
823 | asm volatile("isync": : :"memory"); | |
824 | ||
825 | /* Wait for it to happen */ | |
826 | while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX)) | |
827 | cpu_relax(); | |
828 | } | |
829 | ||
50de596d | 830 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
4b7a3504 | 831 | unsigned long htab_size) |
50de596d | 832 | { |
9d661958 | 833 | mmu_partition_table_init(); |
50de596d AK |
834 | |
835 | /* | |
9d661958 PM |
836 | * PS field (VRMA page size) is not used for LPID 0, hence set to 0. |
837 | * For now, UPRT is 0 and we have no segment table. | |
50de596d | 838 | */ |
4b7a3504 | 839 | htab_size = __ilog2(htab_size) - 18; |
9d661958 | 840 | mmu_partition_table_set_entry(0, hash_table | htab_size, 0); |
56547411 | 841 | pr_info("Partition table %p\n", partition_tb); |
ad410674 AK |
842 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) |
843 | update_hid_for_hash(); | |
50de596d AK |
844 | } |
845 | ||
757c74d2 | 846 | static void __init htab_initialize(void) |
1da177e4 | 847 | { |
337a7128 | 848 | unsigned long table; |
1da177e4 | 849 | unsigned long pteg_count; |
9e88ba4e | 850 | unsigned long prot; |
5556ecf5 | 851 | unsigned long base = 0, size = 0; |
28be7072 | 852 | struct memblock_region *reg; |
3c726f8d | 853 | |
1da177e4 LT |
854 | DBG(" -> htab_initialize()\n"); |
855 | ||
44ae3ab3 | 856 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
857 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
858 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
859 | printk(KERN_INFO "Using 1TB segments\n"); | |
860 | } | |
861 | ||
1da177e4 LT |
862 | /* |
863 | * Calculate the required size of the htab. We want the number of | |
864 | * PTEGs to equal one half the number of real pages. | |
865 | */ | |
3c726f8d | 866 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
867 | pteg_count = htab_size_bytes >> 7; |
868 | ||
1da177e4 LT |
869 | htab_hash_mask = pteg_count - 1; |
870 | ||
5556ecf5 BH |
871 | if (firmware_has_feature(FW_FEATURE_LPAR) || |
872 | firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
1da177e4 LT |
873 | /* Using a hypervisor which owns the htab */ |
874 | htab_address = NULL; | |
875 | _SDR1 = 0; | |
3ccc00a7 MS |
876 | #ifdef CONFIG_FA_DUMP |
877 | /* | |
878 | * If firmware assisted dump is active firmware preserves | |
879 | * the contents of htab along with entire partition memory. | |
880 | * Clear the htab if firmware assisted dump is active so | |
881 | * that we dont end up using old mappings. | |
882 | */ | |
7025776e BH |
883 | if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) |
884 | mmu_hash_ops.hpte_clear_all(); | |
3ccc00a7 | 885 | #endif |
1da177e4 | 886 | } else { |
5556ecf5 BH |
887 | unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; |
888 | ||
889 | #ifdef CONFIG_PPC_CELL | |
890 | /* | |
891 | * Cell may require the hash table down low when using the | |
892 | * Axon IOMMU in order to fit the dynamic region over it, see | |
893 | * comments in cell/iommu.c | |
1da177e4 | 894 | */ |
5556ecf5 | 895 | if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { |
31bf1119 | 896 | limit = 0x80000000; |
5556ecf5 BH |
897 | pr_info("Hash table forced below 2G for Axon IOMMU\n"); |
898 | } | |
899 | #endif /* CONFIG_PPC_CELL */ | |
41d824bf | 900 | |
5556ecf5 BH |
901 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, |
902 | limit); | |
1da177e4 LT |
903 | |
904 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
905 | htab_size_bytes); | |
906 | ||
70267a7f | 907 | htab_address = __va(table); |
1da177e4 LT |
908 | |
909 | /* htab absolute addr + encoded htabsize */ | |
4b7a3504 | 910 | _SDR1 = table + __ilog2(htab_size_bytes) - 18; |
1da177e4 LT |
911 | |
912 | /* Initialize the HPT with no entries */ | |
913 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 914 | |
50de596d AK |
915 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
916 | /* Set SDR1 */ | |
917 | mtspr(SPRN_SDR1, _SDR1); | |
918 | else | |
4b7a3504 | 919 | hash_init_partition_table(table, htab_size_bytes); |
1da177e4 LT |
920 | } |
921 | ||
f5ea64dc | 922 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 923 | |
370a908d | 924 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
925 | if (debug_pagealloc_enabled()) { |
926 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
927 | linear_map_hash_slots = __va(memblock_alloc_base( | |
928 | linear_map_hash_count, 1, ppc64_rma_size)); | |
929 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
930 | } | |
370a908d BH |
931 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
932 | ||
1da177e4 | 933 | /* create bolted the linear mapping in the hash table */ |
28be7072 BH |
934 | for_each_memblock(memory, reg) { |
935 | base = (unsigned long)__va(reg->base); | |
936 | size = reg->size; | |
1da177e4 | 937 | |
5c339919 | 938 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 939 | base, size, prot); |
1da177e4 | 940 | |
caf80e57 | 941 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 942 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
943 | } |
944 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
945 | |
946 | /* | |
947 | * If we have a memory_limit and we've allocated TCEs then we need to | |
948 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
949 | * case that the TCEs start below memory_limit. | |
950 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
951 | * for either 4K or 16MB pages. | |
952 | */ | |
953 | if (tce_alloc_start) { | |
b5666f70 ME |
954 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
955 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
956 | |
957 | if (base + size >= tce_alloc_start) | |
958 | tce_alloc_start = base + size + 1; | |
959 | ||
caf80e57 | 960 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 961 | __pa(tce_alloc_start), prot, |
1189be65 | 962 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
963 | } |
964 | ||
7d0daae4 | 965 | |
1da177e4 LT |
966 | DBG(" <- htab_initialize()\n"); |
967 | } | |
968 | #undef KB | |
969 | #undef MB | |
1da177e4 | 970 | |
bacf9cf8 ME |
971 | void __init hash__early_init_devtree(void) |
972 | { | |
973 | /* Initialize segment sizes */ | |
974 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
975 | ||
976 | /* Initialize page sizes */ | |
977 | htab_scan_page_sizes(); | |
978 | } | |
979 | ||
756d08d1 | 980 | void __init hash__early_init_mmu(void) |
799d6046 | 981 | { |
9d2edb18 | 982 | #ifndef CONFIG_PPC_64K_PAGES |
6aa59f51 | 983 | /* |
9d2edb18 | 984 | * We have code in __hash_page_4K() and elsewhere, which assumes it can |
6aa59f51 AK |
985 | * do the following: |
986 | * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); | |
987 | * | |
988 | * Where the slot number is between 0-15, and values of 8-15 indicate | |
989 | * the secondary bucket. For that code to work H_PAGE_F_SECOND and | |
990 | * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and | |
991 | * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here | |
992 | * with a BUILD_BUG_ON(). | |
993 | */ | |
994 | BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); | |
9d2edb18 | 995 | #endif /* CONFIG_PPC_64K_PAGES */ |
6aa59f51 | 996 | |
bacf9cf8 ME |
997 | htab_init_page_sizes(); |
998 | ||
dd1842a2 AK |
999 | /* |
1000 | * initialize page table size | |
1001 | */ | |
5ed7ecd0 AK |
1002 | __pte_frag_nr = H_PTE_FRAG_NR; |
1003 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
1004 | ||
dd1842a2 AK |
1005 | __pte_index_size = H_PTE_INDEX_SIZE; |
1006 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
1007 | __pud_index_size = H_PUD_INDEX_SIZE; | |
1008 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
1009 | __pmd_cache_index = H_PMD_CACHE_INDEX; | |
1010 | __pte_table_size = H_PTE_TABLE_SIZE; | |
1011 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
1012 | __pud_table_size = H_PUD_TABLE_SIZE; | |
1013 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
1014 | /* |
1015 | * 4k use hugepd format, so for hash set then to | |
1016 | * zero | |
1017 | */ | |
1018 | __pmd_val_bits = 0; | |
1019 | __pud_val_bits = 0; | |
1020 | __pgd_val_bits = 0; | |
d6a9996e AK |
1021 | |
1022 | __kernel_virt_start = H_KERN_VIRT_START; | |
1023 | __kernel_virt_size = H_KERN_VIRT_SIZE; | |
1024 | __vmalloc_start = H_VMALLOC_START; | |
1025 | __vmalloc_end = H_VMALLOC_END; | |
63ee9b2f | 1026 | __kernel_io_start = H_KERN_IO_START; |
d6a9996e AK |
1027 | vmemmap = (struct page *)H_VMEMMAP_BASE; |
1028 | ioremap_bot = IOREMAP_BASE; | |
1029 | ||
bfa37087 DS |
1030 | #ifdef CONFIG_PCI |
1031 | pci_io_base = ISA_IO_BASE; | |
1032 | #endif | |
1033 | ||
166dd7d3 BH |
1034 | /* Select appropriate backend */ |
1035 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
1036 | ps3_early_mm_init(); | |
1037 | else if (firmware_has_feature(FW_FEATURE_LPAR)) | |
6364e84e | 1038 | hpte_init_pseries(); |
fbef66f0 | 1039 | else if (IS_ENABLED(CONFIG_PPC_NATIVE)) |
166dd7d3 BH |
1040 | hpte_init_native(); |
1041 | ||
7353644f ME |
1042 | if (!mmu_hash_ops.hpte_insert) |
1043 | panic("hash__early_init_mmu: No MMU hash ops defined!\n"); | |
1044 | ||
757c74d2 | 1045 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
1046 | * of memory. Has to be done before SLB initialization as this is |
1047 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
1048 | */ |
1049 | htab_initialize(); | |
1050 | ||
56547411 | 1051 | pr_info("Initializing hash mmu with SLB\n"); |
376af594 | 1052 | /* Initialize SLB management */ |
13b3d13b | 1053 | slb_initialize(); |
d4748276 NP |
1054 | |
1055 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1056 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1057 | tlbiel_all(); | |
757c74d2 BH |
1058 | } |
1059 | ||
1060 | #ifdef CONFIG_SMP | |
756d08d1 | 1061 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
1062 | { |
1063 | /* Initialize hash table for that CPU */ | |
b5dcc609 | 1064 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
cac4a185 AK |
1065 | |
1066 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | |
1067 | update_hid_for_hash(); | |
1068 | ||
b5dcc609 AK |
1069 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
1070 | mtspr(SPRN_SDR1, _SDR1); | |
1071 | else | |
1072 | mtspr(SPRN_PTCR, | |
1073 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
1074 | } | |
376af594 | 1075 | /* Initialize SLB */ |
13b3d13b | 1076 | slb_initialize(); |
d4748276 NP |
1077 | |
1078 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1079 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1080 | tlbiel_all(); | |
799d6046 | 1081 | } |
757c74d2 | 1082 | #endif /* CONFIG_SMP */ |
799d6046 | 1083 | |
1da177e4 LT |
1084 | /* |
1085 | * Called by asm hashtable.S for doing lazy icache flush | |
1086 | */ | |
1087 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
1088 | { | |
1089 | struct page *page; | |
1090 | ||
76c8e25b BH |
1091 | if (!pfn_valid(pte_pfn(pte))) |
1092 | return pp; | |
1093 | ||
1da177e4 LT |
1094 | page = pte_page(pte); |
1095 | ||
1096 | /* page is dirty */ | |
1097 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
1098 | if (trap == 0x400) { | |
0895ecda | 1099 | flush_dcache_icache_page(page); |
1da177e4 LT |
1100 | set_bit(PG_arch_1, &page->flags); |
1101 | } else | |
3c726f8d | 1102 | pp |= HPTE_R_N; |
1da177e4 LT |
1103 | } |
1104 | return pp; | |
1105 | } | |
1106 | ||
3a8247cc | 1107 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 1108 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1109 | { |
7aa0727f AK |
1110 | u64 lpsizes; |
1111 | unsigned char *hpsizes; | |
1112 | unsigned long index, mask_index; | |
3a8247cc PM |
1113 | |
1114 | if (addr < SLICE_LOW_TOP) { | |
2fc251a8 | 1115 | lpsizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 1116 | index = GET_LOW_SLICE_INDEX(addr); |
7aa0727f | 1117 | return (lpsizes >> (index * 4)) & 0xF; |
3a8247cc | 1118 | } |
2fc251a8 | 1119 | hpsizes = get_paca()->mm_ctx_high_slices_psize; |
7aa0727f AK |
1120 | index = GET_HIGH_SLICE_INDEX(addr); |
1121 | mask_index = index & 0x1; | |
1122 | return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF; | |
3a8247cc PM |
1123 | } |
1124 | ||
1125 | #else | |
1126 | unsigned int get_paca_psize(unsigned long addr) | |
1127 | { | |
c33e54fa | 1128 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
1129 | } |
1130 | #endif | |
1131 | ||
721151d0 PM |
1132 | /* |
1133 | * Demote a segment to using 4k pages. | |
1134 | * For now this makes the whole process use 4k pages. | |
1135 | */ | |
721151d0 | 1136 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1137 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1138 | { |
3a8247cc | 1139 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1140 | return; |
3a8247cc | 1141 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1142 | copro_flush_all_slbs(mm); |
a1dca346 | 1143 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
c395465d | 1144 | |
52b1e665 | 1145 | copy_mm_to_paca(mm); |
fa28237c PM |
1146 | slb_flush_and_rebolt(); |
1147 | } | |
721151d0 | 1148 | } |
16f1c746 | 1149 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1150 | |
fa28237c PM |
1151 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1152 | /* | |
1153 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1154 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1155 | * | |
1156 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1157 | * _PAGE_RWX: no access. |
fa28237c | 1158 | */ |
d28513bc | 1159 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1160 | { |
d28513bc | 1161 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
1162 | u32 spp = 0; |
1163 | u32 **sbpm, *sbpp; | |
1164 | ||
1165 | if (ea >= spt->maxaddr) | |
1166 | return 0; | |
b0d436c7 | 1167 | if (ea < 0x100000000UL) { |
fa28237c PM |
1168 | /* addresses below 4GB use spt->low_prot */ |
1169 | sbpm = spt->low_prot; | |
1170 | } else { | |
1171 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1172 | if (!sbpm) | |
1173 | return 0; | |
1174 | } | |
1175 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1176 | if (!sbpp) | |
1177 | return 0; | |
1178 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1179 | ||
1180 | /* extract 2-bit bitfield for this 4k subpage */ | |
1181 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1182 | ||
73a1441a AK |
1183 | /* |
1184 | * 0 -> full premission | |
1185 | * 1 -> Read only | |
1186 | * 2 -> no access. | |
1187 | * We return the flag that need to be cleared. | |
1188 | */ | |
1189 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1190 | return spp; |
1191 | } | |
1192 | ||
1193 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1194 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1195 | { |
1196 | return 0; | |
1197 | } | |
1198 | #endif | |
1199 | ||
4b8692c0 BH |
1200 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1201 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1202 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1203 | { |
1204 | if (!printk_ratelimit()) | |
1205 | return; | |
1206 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1207 | ea, access, current->comm); | |
d8139ebf AK |
1208 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1209 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1210 | } |
1211 | ||
09567e7f ME |
1212 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1213 | int psize, bool user_region) | |
1214 | { | |
1215 | if (user_region) { | |
1216 | if (psize != get_paca_psize(ea)) { | |
52b1e665 | 1217 | copy_mm_to_paca(mm); |
09567e7f ME |
1218 | slb_flush_and_rebolt(); |
1219 | } | |
1220 | } else if (get_paca()->vmalloc_sllp != | |
1221 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1222 | get_paca()->vmalloc_sllp = | |
1223 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1224 | slb_vmalloc_update(); | |
1225 | } | |
1226 | } | |
1227 | ||
1da177e4 LT |
1228 | /* Result code is: |
1229 | * 0 - handled | |
1230 | * 1 - normal page fault | |
1231 | * -1 - critical hash insertion error | |
fa28237c | 1232 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1233 | */ |
aefa5688 AK |
1234 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1235 | unsigned long access, unsigned long trap, | |
1236 | unsigned long flags) | |
1da177e4 | 1237 | { |
891121e6 | 1238 | bool is_thp; |
ba12eede | 1239 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1240 | pgd_t *pgdir; |
1da177e4 | 1241 | unsigned long vsid; |
1da177e4 | 1242 | pte_t *ptep; |
a4fe3ce7 | 1243 | unsigned hugeshift; |
aefa5688 | 1244 | int rc, user_region = 0; |
1189be65 | 1245 | int psize, ssize; |
1da177e4 | 1246 | |
3c726f8d BH |
1247 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1248 | ea, access, trap); | |
cfcb3d80 | 1249 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1250 | |
3c726f8d | 1251 | /* Get region & vsid */ |
1da177e4 LT |
1252 | switch (REGION_ID(ea)) { |
1253 | case USER_REGION_ID: | |
1254 | user_region = 1; | |
3c726f8d BH |
1255 | if (! mm) { |
1256 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1257 | rc = 1; |
1258 | goto bail; | |
3c726f8d | 1259 | } |
16c2d476 | 1260 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
1261 | ssize = user_segment_size(ea); |
1262 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 1263 | break; |
1da177e4 | 1264 | case VMALLOC_REGION_ID: |
1189be65 | 1265 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1266 | if (ea < VMALLOC_END) |
1267 | psize = mmu_vmalloc_psize; | |
1268 | else | |
1269 | psize = mmu_io_psize; | |
1189be65 | 1270 | ssize = mmu_kernel_ssize; |
1da177e4 | 1271 | break; |
1da177e4 LT |
1272 | default: |
1273 | /* Not a valid range | |
1274 | * Send the problem up to do_page_fault | |
1275 | */ | |
ba12eede LZ |
1276 | rc = 1; |
1277 | goto bail; | |
1da177e4 | 1278 | } |
3c726f8d | 1279 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1280 | |
c60ac569 AK |
1281 | /* Bad address. */ |
1282 | if (!vsid) { | |
1283 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1284 | rc = 1; |
1285 | goto bail; | |
c60ac569 | 1286 | } |
3c726f8d | 1287 | /* Get pgdir */ |
1da177e4 | 1288 | pgdir = mm->pgd; |
ba12eede LZ |
1289 | if (pgdir == NULL) { |
1290 | rc = 1; | |
1291 | goto bail; | |
1292 | } | |
1da177e4 | 1293 | |
3c726f8d | 1294 | /* Check CPU locality */ |
b426e4bd | 1295 | if (user_region && mm_is_thread_local(mm)) |
aefa5688 | 1296 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1297 | |
16c2d476 | 1298 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1299 | /* If we use 4K pages and our psize is not 4K, then we might |
1300 | * be hitting a special driver mapping, and need to align the | |
1301 | * address before we fetch the PTE. | |
1302 | * | |
1303 | * It could also be a hugepage mapping, in which case this is | |
1304 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1305 | */ |
1306 | if (psize != MMU_PAGE_4K) | |
1307 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1308 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1309 | ||
3c726f8d | 1310 | /* Get PTE and page size from page tables */ |
94171b19 | 1311 | ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1312 | if (ptep == NULL || !pte_present(*ptep)) { |
1313 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1314 | rc = 1; |
1315 | goto bail; | |
3c726f8d BH |
1316 | } |
1317 | ||
ca91e6c0 BH |
1318 | /* Add _PAGE_PRESENT to the required access perm */ |
1319 | access |= _PAGE_PRESENT; | |
1320 | ||
1321 | /* Pre-check access permissions (will be re-checked atomically | |
1322 | * in __hash_page_XX but this pre-check is a fast path | |
1323 | */ | |
ac29c640 | 1324 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1325 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1326 | rc = 1; |
1327 | goto bail; | |
ca91e6c0 BH |
1328 | } |
1329 | ||
ba12eede | 1330 | if (hugeshift) { |
891121e6 | 1331 | if (is_thp) |
6d492ecc | 1332 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1333 | trap, flags, ssize, psize); |
6d492ecc AK |
1334 | #ifdef CONFIG_HUGETLB_PAGE |
1335 | else | |
1336 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1337 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1338 | #else |
1339 | else { | |
1340 | /* | |
1341 | * if we have hugeshift, and is not transhuge with | |
1342 | * hugetlb disabled, something is really wrong. | |
1343 | */ | |
1344 | rc = 1; | |
1345 | WARN_ON(1); | |
1346 | } | |
1347 | #endif | |
a1dca346 IM |
1348 | if (current->mm == mm) |
1349 | check_paca_psize(ea, mm, psize, user_region); | |
09567e7f | 1350 | |
ba12eede LZ |
1351 | goto bail; |
1352 | } | |
a4fe3ce7 | 1353 | |
3c726f8d BH |
1354 | #ifndef CONFIG_PPC_64K_PAGES |
1355 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1356 | #else | |
1357 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1358 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1359 | #endif | |
3c726f8d | 1360 | /* Do actual hashing */ |
16c2d476 | 1361 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1362 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1363 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1364 | demote_segment_4k(mm, ea); |
1365 | psize = MMU_PAGE_4K; | |
1366 | } | |
1367 | ||
16f1c746 BH |
1368 | /* If this PTE is non-cacheable and we have restrictions on |
1369 | * using non cacheable large pages, then we switch to 4k | |
1370 | */ | |
30bda41a | 1371 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1372 | if (user_region) { |
1373 | demote_segment_4k(mm, ea); | |
1374 | psize = MMU_PAGE_4K; | |
1375 | } else if (ea < VMALLOC_END) { | |
1376 | /* | |
1377 | * some driver did a non-cacheable mapping | |
1378 | * in vmalloc space, so switch vmalloc | |
1379 | * to 4k pages | |
1380 | */ | |
1381 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1382 | "to 4kB pages because of " | |
1383 | "non-cacheable mapping\n"); | |
1384 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1385 | copro_flush_all_slbs(mm); |
bf72aeba | 1386 | } |
16f1c746 | 1387 | } |
09567e7f | 1388 | |
0863d7f2 AK |
1389 | #endif /* CONFIG_PPC_64K_PAGES */ |
1390 | ||
a1dca346 IM |
1391 | if (current->mm == mm) |
1392 | check_paca_psize(ea, mm, psize, user_region); | |
16f1c746 | 1393 | |
73b341ef | 1394 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1395 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1396 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1397 | flags, ssize); | |
3c726f8d | 1398 | else |
73b341ef | 1399 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1400 | { |
a1128f8f | 1401 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1402 | if (access & spp) |
1403 | rc = -2; | |
1404 | else | |
1405 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1406 | flags, ssize, spp); |
fa28237c | 1407 | } |
3c726f8d | 1408 | |
4b8692c0 BH |
1409 | /* Dump some info in case of hash insertion failure, they should |
1410 | * never happen so it is really useful to know if/when they do | |
1411 | */ | |
1412 | if (rc == -1) | |
1413 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1414 | psize, pte_val(*ptep)); |
3c726f8d BH |
1415 | #ifndef CONFIG_PPC_64K_PAGES |
1416 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1417 | #else | |
1418 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1419 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1420 | #endif | |
1421 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1422 | |
1423 | bail: | |
1424 | exception_exit(prev_state); | |
3c726f8d | 1425 | return rc; |
1da177e4 | 1426 | } |
a1dca346 IM |
1427 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1428 | ||
aefa5688 AK |
1429 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1430 | unsigned long dsisr) | |
a1dca346 | 1431 | { |
aefa5688 | 1432 | unsigned long flags = 0; |
a1dca346 IM |
1433 | struct mm_struct *mm = current->mm; |
1434 | ||
1435 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1436 | mm = &init_mm; | |
1437 | ||
aefa5688 AK |
1438 | if (dsisr & DSISR_NOHPTE) |
1439 | flags |= HPTE_NOHPTE_UPDATE; | |
1440 | ||
1441 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1442 | } |
67207b96 | 1443 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1444 | |
106713a1 AK |
1445 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1446 | unsigned long dsisr) | |
1447 | { | |
c7d54842 | 1448 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1449 | unsigned long flags = 0; |
1450 | struct mm_struct *mm = current->mm; | |
1451 | ||
1452 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1453 | mm = &init_mm; | |
1454 | ||
1455 | if (dsisr & DSISR_NOHPTE) | |
1456 | flags |= HPTE_NOHPTE_UPDATE; | |
1457 | ||
1458 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1459 | access |= _PAGE_WRITE; |
106713a1 | 1460 | /* |
ac29c640 AK |
1461 | * We set _PAGE_PRIVILEGED only when |
1462 | * kernel mode access kernel space. | |
1463 | * | |
1464 | * _PAGE_PRIVILEGED is NOT set | |
1465 | * 1) when kernel mode access user space | |
1466 | * 2) user space access kernel space. | |
106713a1 | 1467 | */ |
ac29c640 | 1468 | access |= _PAGE_PRIVILEGED; |
106713a1 | 1469 | if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID)) |
ac29c640 | 1470 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1471 | |
1472 | if (trap == 0x400) | |
1473 | access |= _PAGE_EXEC; | |
1474 | ||
1475 | return hash_page_mm(mm, ea, access, trap, flags); | |
1476 | } | |
1477 | ||
8bbc9b7b ME |
1478 | #ifdef CONFIG_PPC_MM_SLICES |
1479 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1480 | { | |
aac55d75 ME |
1481 | int psize = get_slice_psize(mm, ea); |
1482 | ||
8bbc9b7b | 1483 | /* We only prefault standard pages for now */ |
aac55d75 ME |
1484 | if (unlikely(psize != mm->context.user_psize)) |
1485 | return false; | |
1486 | ||
1487 | /* | |
1488 | * Don't prefault if subpage protection is enabled for the EA. | |
1489 | */ | |
1490 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1491 | return false; |
1492 | ||
1493 | return true; | |
1494 | } | |
1495 | #else | |
1496 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1497 | { | |
1498 | return true; | |
1499 | } | |
1500 | #endif | |
1501 | ||
3c726f8d BH |
1502 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1503 | unsigned long access, unsigned long trap) | |
1da177e4 | 1504 | { |
12bc9f6f | 1505 | int hugepage_shift; |
3c726f8d | 1506 | unsigned long vsid; |
0b97fee0 | 1507 | pgd_t *pgdir; |
3c726f8d | 1508 | pte_t *ptep; |
3c726f8d | 1509 | unsigned long flags; |
aefa5688 | 1510 | int rc, ssize, update_flags = 0; |
3c726f8d | 1511 | |
d0f13e3c BH |
1512 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1513 | ||
8bbc9b7b | 1514 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1515 | return; |
1516 | ||
1517 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1518 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1519 | |
16f1c746 | 1520 | /* Get Linux PTE if available */ |
3c726f8d BH |
1521 | pgdir = mm->pgd; |
1522 | if (pgdir == NULL) | |
1523 | return; | |
0ac52dd7 AK |
1524 | |
1525 | /* Get VSID */ | |
1526 | ssize = user_segment_size(ea); | |
1527 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1528 | if (!vsid) | |
1529 | return; | |
1530 | /* | |
1531 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1532 | * saves us from holding multiple locks. | |
1533 | */ | |
1534 | local_irq_save(flags); | |
1535 | ||
12bc9f6f AK |
1536 | /* |
1537 | * THP pages use update_mmu_cache_pmd. We don't do | |
1538 | * hash preload there. Hence can ignore THP here | |
1539 | */ | |
94171b19 | 1540 | ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1541 | if (!ptep) |
0ac52dd7 | 1542 | goto out_exit; |
16f1c746 | 1543 | |
12bc9f6f | 1544 | WARN_ON(hugepage_shift); |
16f1c746 | 1545 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1546 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1547 | * a 64K kernel), then we don't preload, hash_page() will take |
1548 | * care of it once we actually try to access the page. | |
1549 | * That way we don't have to duplicate all of the logic for segment | |
1550 | * page size demotion here | |
1551 | */ | |
945537df | 1552 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1553 | goto out_exit; |
16f1c746 BH |
1554 | #endif /* CONFIG_PPC_64K_PAGES */ |
1555 | ||
16c2d476 | 1556 | /* Is that local to this CPU ? */ |
b426e4bd | 1557 | if (mm_is_thread_local(mm)) |
aefa5688 | 1558 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1559 | |
1560 | /* Hash it in */ | |
73b341ef | 1561 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1562 | if (mm->context.user_psize == MMU_PAGE_64K) |
aefa5688 AK |
1563 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1564 | update_flags, ssize); | |
1da177e4 | 1565 | else |
73b341ef | 1566 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1567 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1568 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1569 | |
1570 | /* Dump some info in case of hash insertion failure, they should | |
1571 | * never happen so it is really useful to know if/when they do | |
1572 | */ | |
1573 | if (rc == -1) | |
1574 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1575 | mm->context.user_psize, |
1576 | mm->context.user_psize, | |
1577 | pte_val(*ptep)); | |
0ac52dd7 | 1578 | out_exit: |
3c726f8d BH |
1579 | local_irq_restore(flags); |
1580 | } | |
1581 | ||
f1a55ce0 RT |
1582 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1583 | static inline void tm_flush_hash_page(int local) | |
1584 | { | |
1585 | /* | |
1586 | * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a | |
1587 | * page back to a block device w/PIO could pick up transactional data | |
1588 | * (bad!) so we force an abort here. Before the sync the page will be | |
1589 | * made read-only, which will flush_hash_page. BIG ISSUE here: if the | |
1590 | * kernel uses a page from userspace without unmapping it first, it may | |
1591 | * see the speculated version. | |
1592 | */ | |
1593 | if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && | |
1594 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1595 | tm_enable(); | |
1596 | tm_abort(TM_CAUSE_TLBI); | |
1597 | } | |
1598 | } | |
1599 | #else | |
1600 | static inline void tm_flush_hash_page(int local) | |
1601 | { | |
1602 | } | |
1603 | #endif | |
1604 | ||
318995b4 RP |
1605 | /* |
1606 | * Return the global hash slot, corresponding to the given PTE, which contains | |
1607 | * the HPTE. | |
1608 | */ | |
1609 | unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, | |
1610 | int ssize, real_pte_t rpte, unsigned int subpg_index) | |
1611 | { | |
1612 | unsigned long hash, gslot, hidx; | |
1613 | ||
1614 | hash = hpt_hash(vpn, shift, ssize); | |
1615 | hidx = __rpte_to_hidx(rpte, subpg_index); | |
1616 | if (hidx & _PTEIDX_SECONDARY) | |
1617 | hash = ~hash; | |
1618 | gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1619 | gslot += hidx & _PTEIDX_GROUP_IX; | |
1620 | return gslot; | |
1621 | } | |
1622 | ||
f6ab0b92 BH |
1623 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1624 | * do not forget to update the assembly call site ! | |
1625 | */ | |
5524a27d | 1626 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1627 | unsigned long flags) |
3c726f8d | 1628 | { |
a8548686 | 1629 | unsigned long index, shift, gslot; |
aefa5688 | 1630 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1631 | |
5524a27d AK |
1632 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1633 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
a8548686 RP |
1634 | gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); |
1635 | DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); | |
db3d8534 AK |
1636 | /* |
1637 | * We use same base page size and actual psize, because we don't | |
1638 | * use these functions for hugepage | |
1639 | */ | |
a8548686 | 1640 | mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, |
7025776e | 1641 | ssize, local); |
3c726f8d | 1642 | } pte_iterate_hashed_end(); |
bc2a9408 | 1643 | |
f1a55ce0 | 1644 | tm_flush_hash_page(local); |
1da177e4 LT |
1645 | } |
1646 | ||
f1581bf1 AK |
1647 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1648 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1649 | pmd_t *pmdp, unsigned int psize, int ssize, |
1650 | unsigned long flags) | |
f1581bf1 AK |
1651 | { |
1652 | int i, max_hpte_count, valid; | |
1653 | unsigned long s_addr; | |
1654 | unsigned char *hpte_slot_array; | |
1655 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1656 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1657 | |
1658 | s_addr = addr & HPAGE_PMD_MASK; | |
1659 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1660 | /* | |
1661 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1662 | * we will find the below NULL. This happens when we do | |
1663 | * split_huge_page_pmd | |
1664 | */ | |
1665 | if (!hpte_slot_array) | |
1666 | return; | |
1667 | ||
7025776e BH |
1668 | if (mmu_hash_ops.hugepage_invalidate) { |
1669 | mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1670 | psize, ssize, local); | |
d557b098 AK |
1671 | goto tm_abort; |
1672 | } | |
f1581bf1 AK |
1673 | /* |
1674 | * No bluk hpte removal support, invalidate each entry | |
1675 | */ | |
1676 | shift = mmu_psize_defs[psize].shift; | |
1677 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1678 | for (i = 0; i < max_hpte_count; i++) { | |
1679 | /* | |
1680 | * 8 bits per each hpte entries | |
1681 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1682 | */ | |
1683 | valid = hpte_valid(hpte_slot_array, i); | |
1684 | if (!valid) | |
1685 | continue; | |
1686 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1687 | ||
1688 | /* get the vpn */ | |
1689 | addr = s_addr + (i * (1ul << shift)); | |
1690 | vpn = hpt_vpn(addr, vsid, ssize); | |
1691 | hash = hpt_hash(vpn, shift, ssize); | |
1692 | if (hidx & _PTEIDX_SECONDARY) | |
1693 | hash = ~hash; | |
1694 | ||
1695 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1696 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1697 | mmu_hash_ops.hpte_invalidate(slot, vpn, psize, |
1698 | MMU_PAGE_16M, ssize, local); | |
d557b098 AK |
1699 | } |
1700 | tm_abort: | |
f1a55ce0 | 1701 | tm_flush_hash_page(local); |
f1581bf1 AK |
1702 | } |
1703 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1704 | ||
61b1a942 | 1705 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1706 | { |
7025776e BH |
1707 | if (mmu_hash_ops.flush_hash_range) |
1708 | mmu_hash_ops.flush_hash_range(number, local); | |
3c726f8d | 1709 | else { |
1da177e4 | 1710 | int i; |
61b1a942 | 1711 | struct ppc64_tlb_batch *batch = |
69111bac | 1712 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1713 | |
1714 | for (i = 0; i < number; i++) | |
5524a27d | 1715 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1716 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1717 | } |
1718 | } | |
1719 | ||
1da177e4 LT |
1720 | /* |
1721 | * low_hash_fault is called when we the low level hash code failed | |
1722 | * to instert a PTE due to an hypervisor error | |
1723 | */ | |
fa28237c | 1724 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1725 | { |
ba12eede LZ |
1726 | enum ctx_state prev_state = exception_enter(); |
1727 | ||
1da177e4 | 1728 | if (user_mode(regs)) { |
fa28237c PM |
1729 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1730 | if (rc == -2) | |
1731 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1732 | else | |
1733 | #endif | |
1734 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1735 | } else | |
1736 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1737 | |
1738 | exception_exit(prev_state); | |
1da177e4 | 1739 | } |
370a908d | 1740 | |
b170bd3d LZ |
1741 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1742 | unsigned long pa, unsigned long rflags, | |
1743 | unsigned long vflags, int psize, int ssize) | |
1744 | { | |
1745 | unsigned long hpte_group; | |
1746 | long slot; | |
1747 | ||
1748 | repeat: | |
1749 | hpte_group = ((hash & htab_hash_mask) * | |
1750 | HPTES_PER_GROUP) & ~0x7UL; | |
1751 | ||
1752 | /* Insert into the hash table, primary slot */ | |
7025776e BH |
1753 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, |
1754 | psize, psize, ssize); | |
b170bd3d LZ |
1755 | |
1756 | /* Primary is full, try the secondary */ | |
1757 | if (unlikely(slot == -1)) { | |
1758 | hpte_group = ((~hash & htab_hash_mask) * | |
1759 | HPTES_PER_GROUP) & ~0x7UL; | |
7025776e BH |
1760 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, |
1761 | vflags | HPTE_V_SECONDARY, | |
1762 | psize, psize, ssize); | |
b170bd3d LZ |
1763 | if (slot == -1) { |
1764 | if (mftb() & 0x1) | |
1765 | hpte_group = ((hash & htab_hash_mask) * | |
1766 | HPTES_PER_GROUP)&~0x7UL; | |
1767 | ||
7025776e | 1768 | mmu_hash_ops.hpte_remove(hpte_group); |
b170bd3d LZ |
1769 | goto repeat; |
1770 | } | |
1771 | } | |
1772 | ||
1773 | return slot; | |
1774 | } | |
1775 | ||
370a908d BH |
1776 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1777 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1778 | { | |
016af59f | 1779 | unsigned long hash; |
1189be65 | 1780 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1781 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1782 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1783 | long ret; |
370a908d | 1784 | |
5524a27d | 1785 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1786 | |
c60ac569 AK |
1787 | /* Don't create HPTE entries for bad address */ |
1788 | if (!vsid) | |
1789 | return; | |
016af59f LZ |
1790 | |
1791 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1792 | HPTE_V_BOLTED, | |
1793 | mmu_linear_psize, mmu_kernel_ssize); | |
1794 | ||
370a908d BH |
1795 | BUG_ON (ret < 0); |
1796 | spin_lock(&linear_map_hash_lock); | |
1797 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1798 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1799 | spin_unlock(&linear_map_hash_lock); | |
1800 | } | |
1801 | ||
1802 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1803 | { | |
1189be65 PM |
1804 | unsigned long hash, hidx, slot; |
1805 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1806 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1807 | |
5524a27d | 1808 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1809 | spin_lock(&linear_map_hash_lock); |
1810 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1811 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1812 | linear_map_hash_slots[lmi] = 0; | |
1813 | spin_unlock(&linear_map_hash_lock); | |
1814 | if (hidx & _PTEIDX_SECONDARY) | |
1815 | hash = ~hash; | |
1816 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1817 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1818 | mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, |
1819 | mmu_linear_psize, | |
1820 | mmu_kernel_ssize, 0); | |
370a908d BH |
1821 | } |
1822 | ||
031bc574 | 1823 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1824 | { |
1825 | unsigned long flags, vaddr, lmi; | |
1826 | int i; | |
1827 | ||
1828 | local_irq_save(flags); | |
1829 | for (i = 0; i < numpages; i++, page++) { | |
1830 | vaddr = (unsigned long)page_address(page); | |
1831 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1832 | if (lmi >= linear_map_hash_count) | |
1833 | continue; | |
1834 | if (enable) | |
1835 | kernel_map_linear_page(vaddr, lmi); | |
1836 | else | |
1837 | kernel_unmap_linear_page(vaddr, lmi); | |
1838 | } | |
1839 | local_irq_restore(flags); | |
1840 | } | |
1841 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1842 | |
756d08d1 | 1843 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1844 | phys_addr_t first_memblock_size) |
1845 | { | |
1846 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1847 | * physical on those processors | |
1848 | */ | |
1849 | BUG_ON(first_memblock_base != 0); | |
1850 | ||
1513c33d NP |
1851 | /* |
1852 | * On virtualized systems the first entry is our RMA region aka VRMA, | |
1853 | * non-virtualized 64-bit hash MMU systems don't have a limitation | |
1854 | * on real mode access. | |
1855 | * | |
c610d65c NP |
1856 | * For guests on platforms before POWER9, we clamp the it limit to 1G |
1857 | * to avoid some funky things such as RTAS bugs etc... | |
cd3db0c4 | 1858 | */ |
1513c33d | 1859 | if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { |
c610d65c NP |
1860 | ppc64_rma_size = first_memblock_size; |
1861 | if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) | |
1862 | ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); | |
cd3db0c4 | 1863 | |
1513c33d NP |
1864 | /* Finally limit subsequent allocations */ |
1865 | memblock_set_current_limit(ppc64_rma_size); | |
1866 | } else { | |
1867 | ppc64_rma_size = ULONG_MAX; | |
1868 | } | |
cd3db0c4 | 1869 | } |
dbcf929c DG |
1870 | |
1871 | #ifdef CONFIG_DEBUG_FS | |
1872 | ||
1873 | static int hpt_order_get(void *data, u64 *val) | |
1874 | { | |
1875 | *val = ppc64_pft_size; | |
1876 | return 0; | |
1877 | } | |
1878 | ||
1879 | static int hpt_order_set(void *data, u64 val) | |
1880 | { | |
1881 | if (!mmu_hash_ops.resize_hpt) | |
1882 | return -ENODEV; | |
1883 | ||
1884 | return mmu_hash_ops.resize_hpt(val); | |
1885 | } | |
1886 | ||
1887 | DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); | |
1888 | ||
1889 | static int __init hash64_debugfs(void) | |
1890 | { | |
1891 | if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, | |
1892 | NULL, &fops_hpt_order)) { | |
1893 | pr_err("lpar: unable to create hpt_order debugsfs file\n"); | |
1894 | } | |
1895 | ||
1896 | return 0; | |
1897 | } | |
1898 | machine_device_initcall(pseries, hash64_debugfs); | |
dbcf929c | 1899 | #endif /* CONFIG_DEBUG_FS */ |