Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
66b15db6 | 30 | #include <linux/export.h> |
1da177e4 LT |
31 | #include <linux/ctype.h> |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
95f72d1e | 35 | #include <linux/memblock.h> |
ba12eede | 36 | #include <linux/context_tracking.h> |
1da177e4 | 37 | |
1da177e4 LT |
38 | #include <asm/processor.h> |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/mmu.h> | |
41 | #include <asm/mmu_context.h> | |
42 | #include <asm/page.h> | |
43 | #include <asm/types.h> | |
1da177e4 LT |
44 | #include <asm/uaccess.h> |
45 | #include <asm/machdep.h> | |
d9b2b2a2 | 46 | #include <asm/prom.h> |
1da177e4 LT |
47 | #include <asm/tlbflush.h> |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
1da177e4 | 53 | #include <asm/sections.h> |
be3ebfe8 | 54 | #include <asm/copro.h> |
aa39be09 | 55 | #include <asm/udbg.h> |
b68a70c4 | 56 | #include <asm/code-patching.h> |
3ccc00a7 | 57 | #include <asm/fadump.h> |
f5339277 | 58 | #include <asm/firmware.h> |
bc2a9408 | 59 | #include <asm/tm.h> |
cfcb3d80 | 60 | #include <asm/trace.h> |
1da177e4 LT |
61 | |
62 | #ifdef DEBUG | |
63 | #define DBG(fmt...) udbg_printf(fmt) | |
64 | #else | |
65 | #define DBG(fmt...) | |
66 | #endif | |
67 | ||
3c726f8d BH |
68 | #ifdef DEBUG_LOW |
69 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
70 | #else | |
71 | #define DBG_LOW(fmt...) | |
72 | #endif | |
73 | ||
74 | #define KB (1024) | |
75 | #define MB (1024*KB) | |
658013e9 | 76 | #define GB (1024L*MB) |
3c726f8d | 77 | |
1da177e4 LT |
78 | /* |
79 | * Note: pte --> Linux PTE | |
80 | * HPTE --> PowerPC Hashed Page Table Entry | |
81 | * | |
82 | * Execution context: | |
83 | * htab_initialize is called with the MMU off (of course), but | |
84 | * the kernel has been copied down to zero so it can directly | |
85 | * reference global data. At this point it is very difficult | |
86 | * to print debug info. | |
87 | * | |
88 | */ | |
89 | ||
90 | #ifdef CONFIG_U3_DART | |
91 | extern unsigned long dart_tablebase; | |
92 | #endif /* CONFIG_U3_DART */ | |
93 | ||
799d6046 PM |
94 | static unsigned long _SDR1; |
95 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 96 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 97 | |
8e561e7e | 98 | struct hash_pte *htab_address; |
337a7128 | 99 | unsigned long htab_size_bytes; |
96e28449 | 100 | unsigned long htab_hash_mask; |
4ab79aa8 | 101 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 102 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 103 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 104 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 105 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
106 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
107 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
108 | #endif | |
bf72aeba | 109 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 110 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 111 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 112 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 113 | u16 mmu_slb_size = 64; |
4ab79aa8 | 114 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
115 | #ifdef CONFIG_PPC_64K_PAGES |
116 | int mmu_ci_restrictions; | |
117 | #endif | |
370a908d BH |
118 | #ifdef CONFIG_DEBUG_PAGEALLOC |
119 | static u8 *linear_map_hash_slots; | |
120 | static unsigned long linear_map_hash_count; | |
ed166692 | 121 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 122 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 123 | |
3c726f8d BH |
124 | /* There are definitions of page sizes arrays to be used when none |
125 | * is provided by the firmware. | |
126 | */ | |
1da177e4 | 127 | |
3c726f8d BH |
128 | /* Pre-POWER4 CPUs (4k pages only) |
129 | */ | |
09de9ff8 | 130 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
131 | [MMU_PAGE_4K] = { |
132 | .shift = 12, | |
133 | .sllp = 0, | |
b1022fbd | 134 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
135 | .avpnm = 0, |
136 | .tlbiel = 0, | |
137 | }, | |
138 | }; | |
139 | ||
140 | /* POWER4, GPUL, POWER5 | |
141 | * | |
142 | * Support for 16Mb large pages | |
143 | */ | |
09de9ff8 | 144 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
145 | [MMU_PAGE_4K] = { |
146 | .shift = 12, | |
147 | .sllp = 0, | |
b1022fbd | 148 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
149 | .avpnm = 0, |
150 | .tlbiel = 1, | |
151 | }, | |
152 | [MMU_PAGE_16M] = { | |
153 | .shift = 24, | |
154 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
155 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
156 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
157 | .avpnm = 0x1UL, |
158 | .tlbiel = 0, | |
159 | }, | |
160 | }; | |
161 | ||
c6a3c495 | 162 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 163 | { |
c6a3c495 | 164 | unsigned long rflags = 0; |
bc033b63 BH |
165 | |
166 | /* _PAGE_EXEC -> NOEXEC */ | |
167 | if ((pteflags & _PAGE_EXEC) == 0) | |
168 | rflags |= HPTE_R_N; | |
c6a3c495 AK |
169 | /* |
170 | * PP bits: | |
1ec3f937 PM |
171 | * Linux uses slb key 0 for kernel and 1 for user. |
172 | * kernel areas are mapped with PP=00 | |
173 | * and there is no kernel RO (_PAGE_KERNEL_RO). | |
174 | * User area is mapped with PP=0x2 for read/write | |
175 | * or PP=0x3 for read-only (including writeable but clean pages). | |
bc033b63 | 176 | */ |
ac29c640 | 177 | if (!(pteflags & _PAGE_PRIVILEGED)) { |
c7d54842 AK |
178 | if (pteflags & _PAGE_RWX) |
179 | rflags |= 0x2; | |
180 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
181 | rflags |= 0x1; |
182 | } | |
c8c06f5a AK |
183 | /* |
184 | * Always add "C" bit for perf. Memory coherence is always enabled | |
185 | */ | |
40e8550a AK |
186 | rflags |= HPTE_R_C | HPTE_R_M; |
187 | /* | |
188 | * Add in WIG bits | |
189 | */ | |
190 | if (pteflags & _PAGE_WRITETHRU) | |
191 | rflags |= HPTE_R_W; | |
192 | if (pteflags & _PAGE_NO_CACHE) | |
193 | rflags |= HPTE_R_I; | |
194 | if (pteflags & _PAGE_GUARDED) | |
195 | rflags |= HPTE_R_G; | |
196 | ||
197 | return rflags; | |
bc033b63 | 198 | } |
3c726f8d BH |
199 | |
200 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 201 | unsigned long pstart, unsigned long prot, |
1189be65 | 202 | int psize, int ssize) |
1da177e4 | 203 | { |
3c726f8d BH |
204 | unsigned long vaddr, paddr; |
205 | unsigned int step, shift; | |
3c726f8d | 206 | int ret = 0; |
1da177e4 | 207 | |
3c726f8d BH |
208 | shift = mmu_psize_defs[psize].shift; |
209 | step = 1 << shift; | |
1da177e4 | 210 | |
bc033b63 BH |
211 | prot = htab_convert_pte_flags(prot); |
212 | ||
213 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
214 | vstart, vend, pstart, prot, psize, ssize); | |
215 | ||
3c726f8d BH |
216 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
217 | vaddr += step, paddr += step) { | |
370a908d | 218 | unsigned long hash, hpteg; |
1189be65 | 219 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 220 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
221 | unsigned long tprot = prot; |
222 | ||
c60ac569 AK |
223 | /* |
224 | * If we hit a bad address return error. | |
225 | */ | |
226 | if (!vsid) | |
227 | return -1; | |
9e88ba4e | 228 | /* Make kernel text executable */ |
549e8152 | 229 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 230 | tprot &= ~HPTE_R_N; |
1da177e4 | 231 | |
b18db0b8 AG |
232 | /* Make kvm guest trampolines executable */ |
233 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
234 | tprot &= ~HPTE_R_N; | |
235 | ||
429d2e83 MS |
236 | /* |
237 | * If relocatable, check if it overlaps interrupt vectors that | |
238 | * are copied down to real 0. For relocatable kernel | |
239 | * (e.g. kdump case) we copy interrupt vectors down to real | |
240 | * address 0. Mark that region as executable. This is | |
241 | * because on p8 system with relocation on exception feature | |
242 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
243 | * in order to execute the interrupt handlers in virtual | |
244 | * mode the vector region need to be marked as executable. | |
245 | */ | |
246 | if ((PHYSICAL_START > MEMORY_START) && | |
247 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
248 | tprot &= ~HPTE_R_N; | |
249 | ||
5524a27d | 250 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
251 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
252 | ||
c30a4df3 | 253 | BUG_ON(!ppc_md.hpte_insert); |
5524a27d | 254 | ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot, |
b1022fbd | 255 | HPTE_V_BOLTED, psize, psize, ssize); |
c30a4df3 | 256 | |
3c726f8d BH |
257 | if (ret < 0) |
258 | break; | |
e7df0d88 | 259 | |
370a908d | 260 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
261 | if (debug_pagealloc_enabled() && |
262 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
263 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
264 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
265 | } |
266 | return ret < 0 ? ret : 0; | |
267 | } | |
1da177e4 | 268 | |
ed5694a8 | 269 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
270 | int psize, int ssize) |
271 | { | |
272 | unsigned long vaddr; | |
273 | unsigned int step, shift; | |
27828f98 DG |
274 | int rc; |
275 | int ret = 0; | |
f8c8803b BP |
276 | |
277 | shift = mmu_psize_defs[psize].shift; | |
278 | step = 1 << shift; | |
279 | ||
abd0a0e7 DG |
280 | if (!ppc_md.hpte_removebolted) |
281 | return -ENODEV; | |
f8c8803b | 282 | |
27828f98 DG |
283 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
284 | rc = ppc_md.hpte_removebolted(vaddr, psize, ssize); | |
285 | if (rc == -ENOENT) { | |
286 | ret = -ENOENT; | |
287 | continue; | |
288 | } | |
289 | if (rc < 0) | |
290 | return rc; | |
291 | } | |
52db9b44 | 292 | |
27828f98 | 293 | return ret; |
f8c8803b BP |
294 | } |
295 | ||
1189be65 PM |
296 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
297 | const char *uname, int depth, | |
298 | void *data) | |
299 | { | |
9d0c4dfe RH |
300 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
301 | const __be32 *prop; | |
302 | int size = 0; | |
1189be65 PM |
303 | |
304 | /* We are scanning "cpu" nodes only */ | |
305 | if (type == NULL || strcmp(type, "cpu") != 0) | |
306 | return 0; | |
307 | ||
12f04f2b | 308 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
309 | if (prop == NULL) |
310 | return 0; | |
311 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 312 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 313 | DBG("1T segment support detected\n"); |
44ae3ab3 | 314 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 315 | return 1; |
1189be65 | 316 | } |
1189be65 | 317 | } |
44ae3ab3 | 318 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
319 | return 0; |
320 | } | |
321 | ||
322 | static void __init htab_init_seg_sizes(void) | |
323 | { | |
324 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
325 | } | |
326 | ||
b1022fbd AK |
327 | static int __init get_idx_from_shift(unsigned int shift) |
328 | { | |
329 | int idx = -1; | |
330 | ||
331 | switch (shift) { | |
332 | case 0xc: | |
333 | idx = MMU_PAGE_4K; | |
334 | break; | |
335 | case 0x10: | |
336 | idx = MMU_PAGE_64K; | |
337 | break; | |
338 | case 0x14: | |
339 | idx = MMU_PAGE_1M; | |
340 | break; | |
341 | case 0x18: | |
342 | idx = MMU_PAGE_16M; | |
343 | break; | |
344 | case 0x22: | |
345 | idx = MMU_PAGE_16G; | |
346 | break; | |
347 | } | |
348 | return idx; | |
349 | } | |
350 | ||
3c726f8d BH |
351 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
352 | const char *uname, int depth, | |
353 | void *data) | |
354 | { | |
9d0c4dfe RH |
355 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
356 | const __be32 *prop; | |
357 | int size = 0; | |
3c726f8d BH |
358 | |
359 | /* We are scanning "cpu" nodes only */ | |
360 | if (type == NULL || strcmp(type, "cpu") != 0) | |
361 | return 0; | |
362 | ||
12f04f2b | 363 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
364 | if (!prop) |
365 | return 0; | |
366 | ||
367 | pr_info("Page sizes from device-tree:\n"); | |
368 | size /= 4; | |
369 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
370 | while(size > 0) { | |
371 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
372 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
373 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
374 | struct mmu_psize_def *def; | |
375 | int idx, base_idx; | |
376 | ||
377 | size -= 3; prop += 3; | |
378 | base_idx = get_idx_from_shift(base_shift); | |
379 | if (base_idx < 0) { | |
380 | /* skip the pte encoding also */ | |
381 | prop += lpnum * 2; size -= lpnum * 2; | |
382 | continue; | |
383 | } | |
384 | def = &mmu_psize_defs[base_idx]; | |
385 | if (base_idx == MMU_PAGE_16M) | |
386 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
387 | ||
388 | def->shift = base_shift; | |
389 | if (base_shift <= 23) | |
390 | def->avpnm = 0; | |
391 | else | |
392 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
393 | def->sllp = slbenc; | |
394 | /* | |
395 | * We don't know for sure what's up with tlbiel, so | |
396 | * for now we only set it for 4K and 64K pages | |
397 | */ | |
398 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
399 | def->tlbiel = 1; | |
400 | else | |
401 | def->tlbiel = 0; | |
402 | ||
403 | while (size > 0 && lpnum) { | |
404 | unsigned int shift = be32_to_cpu(prop[0]); | |
405 | int penc = be32_to_cpu(prop[1]); | |
406 | ||
407 | prop += 2; size -= 2; | |
408 | lpnum--; | |
409 | ||
410 | idx = get_idx_from_shift(shift); | |
411 | if (idx < 0) | |
b1022fbd | 412 | continue; |
9e34992a ME |
413 | |
414 | if (penc == -1) | |
415 | pr_err("Invalid penc for base_shift=%d " | |
416 | "shift=%d\n", base_shift, shift); | |
417 | ||
418 | def->penc[idx] = penc; | |
419 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
420 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
421 | base_shift, shift, def->sllp, | |
422 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 423 | } |
3c726f8d | 424 | } |
9e34992a ME |
425 | |
426 | return 1; | |
3c726f8d BH |
427 | } |
428 | ||
e16a9c09 | 429 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
430 | /* Scan for 16G memory blocks that have been set aside for huge pages |
431 | * and reserve those blocks for 16G huge pages. | |
432 | */ | |
433 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
434 | const char *uname, int depth, | |
435 | void *data) { | |
9d0c4dfe RH |
436 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
437 | const __be64 *addr_prop; | |
438 | const __be32 *page_count_prop; | |
658013e9 JT |
439 | unsigned int expected_pages; |
440 | long unsigned int phys_addr; | |
441 | long unsigned int block_size; | |
442 | ||
443 | /* We are scanning "memory" nodes only */ | |
444 | if (type == NULL || strcmp(type, "memory") != 0) | |
445 | return 0; | |
446 | ||
447 | /* This property is the log base 2 of the number of virtual pages that | |
448 | * will represent this memory block. */ | |
449 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
450 | if (page_count_prop == NULL) | |
451 | return 0; | |
12f04f2b | 452 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
453 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
454 | if (addr_prop == NULL) | |
455 | return 0; | |
12f04f2b AB |
456 | phys_addr = be64_to_cpu(addr_prop[0]); |
457 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
458 | if (block_size != (16 * GB)) |
459 | return 0; | |
460 | printk(KERN_INFO "Huge page(16GB) memory: " | |
461 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
462 | phys_addr, block_size, expected_pages); | |
95f72d1e YL |
463 | if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) { |
464 | memblock_reserve(phys_addr, block_size * expected_pages); | |
4792adba JT |
465 | add_gpage(phys_addr, block_size, expected_pages); |
466 | } | |
658013e9 JT |
467 | return 0; |
468 | } | |
e16a9c09 | 469 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 470 | |
b1022fbd AK |
471 | static void mmu_psize_set_default_penc(void) |
472 | { | |
473 | int bpsize, apsize; | |
474 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
475 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
476 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
477 | } | |
478 | ||
9048e648 AG |
479 | #ifdef CONFIG_PPC_64K_PAGES |
480 | ||
481 | static bool might_have_hea(void) | |
482 | { | |
483 | /* | |
484 | * The HEA ethernet adapter requires awareness of the | |
485 | * GX bus. Without that awareness we can easily assume | |
486 | * we will never see an HEA ethernet device. | |
487 | */ | |
488 | #ifdef CONFIG_IBMEBUS | |
489 | return !cpu_has_feature(CPU_FTR_ARCH_207S); | |
490 | #else | |
491 | return false; | |
492 | #endif | |
493 | } | |
494 | ||
495 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
496 | ||
3c726f8d BH |
497 | static void __init htab_init_page_sizes(void) |
498 | { | |
499 | int rc; | |
500 | ||
b1022fbd AK |
501 | /* se the invalid penc to -1 */ |
502 | mmu_psize_set_default_penc(); | |
503 | ||
3c726f8d BH |
504 | /* Default to 4K pages only */ |
505 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
506 | sizeof(mmu_psize_defaults_old)); | |
507 | ||
508 | /* | |
509 | * Try to find the available page sizes in the device-tree | |
510 | */ | |
511 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
512 | if (rc != 0) /* Found */ | |
513 | goto found; | |
514 | ||
515 | /* | |
516 | * Not in the device-tree, let's fallback on known size | |
517 | * list for 16M capable GP & GR | |
518 | */ | |
44ae3ab3 | 519 | if (mmu_has_feature(MMU_FTR_16M_PAGE)) |
3c726f8d BH |
520 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
521 | sizeof(mmu_psize_defaults_gp)); | |
e7df0d88 JK |
522 | found: |
523 | if (!debug_pagealloc_enabled()) { | |
524 | /* | |
525 | * Pick a size for the linear mapping. Currently, we only | |
526 | * support 16M, 1M and 4K which is the default | |
527 | */ | |
528 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
529 | mmu_linear_psize = MMU_PAGE_16M; | |
530 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
531 | mmu_linear_psize = MMU_PAGE_1M; | |
532 | } | |
3c726f8d | 533 | |
bf72aeba | 534 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
535 | /* |
536 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
537 | * 64K for user mappings and vmalloc if supported by the processor. |
538 | * We only use 64k for ioremap if the processor | |
539 | * (and firmware) support cache-inhibited large pages. | |
540 | * If not, we use 4k and set mmu_ci_restrictions so that | |
541 | * hash_page knows to switch processes that use cache-inhibited | |
542 | * mappings to 4k pages. | |
3c726f8d | 543 | */ |
bf72aeba | 544 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 545 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 546 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
547 | if (mmu_linear_psize == MMU_PAGE_4K) |
548 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 549 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 550 | /* |
9048e648 AG |
551 | * When running on pSeries using 64k pages for ioremap |
552 | * would stop us accessing the HEA ethernet. So if we | |
553 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 554 | */ |
9048e648 | 555 | if (!might_have_hea() || !machine_is(pseries)) |
cfe666b1 PM |
556 | mmu_io_psize = MMU_PAGE_64K; |
557 | } else | |
bf72aeba PM |
558 | mmu_ci_restrictions = 1; |
559 | } | |
370a908d | 560 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 561 | |
cec08e7a BH |
562 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
563 | /* We try to use 16M pages for vmemmap if that is supported | |
564 | * and we have at least 1G of RAM at boot | |
565 | */ | |
566 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 567 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
568 | mmu_vmemmap_psize = MMU_PAGE_16M; |
569 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
570 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
571 | else | |
572 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
573 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
574 | ||
bf72aeba | 575 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
576 | "virtual = %d, io = %d" |
577 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
578 | ", vmemmap = %d" | |
579 | #endif | |
580 | "\n", | |
3c726f8d | 581 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 582 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
583 | mmu_psize_defs[mmu_io_psize].shift |
584 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
585 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
586 | #endif | |
587 | ); | |
3c726f8d BH |
588 | |
589 | #ifdef CONFIG_HUGETLB_PAGE | |
658013e9 JT |
590 | /* Reserve 16G huge page memory sections for huge pages */ |
591 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
3c726f8d BH |
592 | #endif /* CONFIG_HUGETLB_PAGE */ |
593 | } | |
594 | ||
595 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
596 | const char *uname, int depth, | |
597 | void *data) | |
598 | { | |
9d0c4dfe RH |
599 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
600 | const __be32 *prop; | |
3c726f8d BH |
601 | |
602 | /* We are scanning "cpu" nodes only */ | |
603 | if (type == NULL || strcmp(type, "cpu") != 0) | |
604 | return 0; | |
605 | ||
12f04f2b | 606 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
607 | if (prop != NULL) { |
608 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 609 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 610 | return 1; |
1da177e4 | 611 | } |
3c726f8d | 612 | return 0; |
1da177e4 LT |
613 | } |
614 | ||
5c3c7ede | 615 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 616 | { |
5c3c7ede DG |
617 | unsigned memshift = __ilog2(mem_size); |
618 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
619 | unsigned pteg_shift; | |
620 | ||
621 | /* round mem_size up to next power of 2 */ | |
622 | if ((1UL << memshift) < mem_size) | |
623 | memshift += 1; | |
3eac8c69 | 624 | |
5c3c7ede DG |
625 | /* aim for 2 pages / pteg */ |
626 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 627 | |
5c3c7ede DG |
628 | /* |
629 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
630 | * size permitted by the architecture. | |
631 | */ | |
632 | return max(pteg_shift + 7, 18U); | |
633 | } | |
634 | ||
635 | static unsigned long __init htab_get_table_size(void) | |
636 | { | |
3c726f8d | 637 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 638 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 639 | * calculate it now based on the total RAM size |
3eac8c69 | 640 | */ |
3c726f8d BH |
641 | if (ppc64_pft_size == 0) |
642 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
643 | if (ppc64_pft_size) |
644 | return 1UL << ppc64_pft_size; | |
645 | ||
5c3c7ede | 646 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
647 | } |
648 | ||
54b79248 | 649 | #ifdef CONFIG_MEMORY_HOTPLUG |
a1194097 | 650 | int create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 651 | { |
1dace6c6 DG |
652 | int rc = htab_bolt_mapping(start, end, __pa(start), |
653 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
654 | mmu_kernel_ssize); | |
655 | ||
656 | if (rc < 0) { | |
657 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
658 | mmu_kernel_ssize); | |
659 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
660 | } | |
661 | return rc; | |
54b79248 | 662 | } |
f8c8803b | 663 | |
52db9b44 | 664 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 665 | { |
abd0a0e7 DG |
666 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
667 | mmu_kernel_ssize); | |
668 | WARN_ON(rc < 0); | |
669 | return rc; | |
f8c8803b | 670 | } |
54b79248 MK |
671 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
672 | ||
757c74d2 | 673 | static void __init htab_initialize(void) |
1da177e4 | 674 | { |
337a7128 | 675 | unsigned long table; |
1da177e4 | 676 | unsigned long pteg_count; |
9e88ba4e | 677 | unsigned long prot; |
41d824bf | 678 | unsigned long base = 0, size = 0, limit; |
28be7072 | 679 | struct memblock_region *reg; |
3c726f8d | 680 | |
1da177e4 LT |
681 | DBG(" -> htab_initialize()\n"); |
682 | ||
1189be65 PM |
683 | /* Initialize segment sizes */ |
684 | htab_init_seg_sizes(); | |
685 | ||
3c726f8d BH |
686 | /* Initialize page sizes */ |
687 | htab_init_page_sizes(); | |
688 | ||
44ae3ab3 | 689 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
690 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
691 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
692 | printk(KERN_INFO "Using 1TB segments\n"); | |
693 | } | |
694 | ||
1da177e4 LT |
695 | /* |
696 | * Calculate the required size of the htab. We want the number of | |
697 | * PTEGs to equal one half the number of real pages. | |
698 | */ | |
3c726f8d | 699 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
700 | pteg_count = htab_size_bytes >> 7; |
701 | ||
1da177e4 LT |
702 | htab_hash_mask = pteg_count - 1; |
703 | ||
57cfb814 | 704 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
705 | /* Using a hypervisor which owns the htab */ |
706 | htab_address = NULL; | |
707 | _SDR1 = 0; | |
3ccc00a7 MS |
708 | #ifdef CONFIG_FA_DUMP |
709 | /* | |
710 | * If firmware assisted dump is active firmware preserves | |
711 | * the contents of htab along with entire partition memory. | |
712 | * Clear the htab if firmware assisted dump is active so | |
713 | * that we dont end up using old mappings. | |
714 | */ | |
715 | if (is_fadump_active() && ppc_md.hpte_clear_all) | |
716 | ppc_md.hpte_clear_all(); | |
717 | #endif | |
1da177e4 LT |
718 | } else { |
719 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf | 720 | * the absolute address space. On cell we want it to be |
31bf1119 | 721 | * in the first 2 Gig so we can use it for IOMMU hacks. |
1da177e4 | 722 | */ |
41d824bf | 723 | if (machine_is(cell)) |
31bf1119 | 724 | limit = 0x80000000; |
41d824bf | 725 | else |
27f574c2 | 726 | limit = MEMBLOCK_ALLOC_ANYWHERE; |
41d824bf | 727 | |
95f72d1e | 728 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit); |
1da177e4 LT |
729 | |
730 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
731 | htab_size_bytes); | |
732 | ||
70267a7f | 733 | htab_address = __va(table); |
1da177e4 LT |
734 | |
735 | /* htab absolute addr + encoded htabsize */ | |
736 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
737 | ||
738 | /* Initialize the HPT with no entries */ | |
739 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 PM |
740 | |
741 | /* Set SDR1 */ | |
742 | mtspr(SPRN_SDR1, _SDR1); | |
1da177e4 LT |
743 | } |
744 | ||
f5ea64dc | 745 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 746 | |
370a908d | 747 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
748 | if (debug_pagealloc_enabled()) { |
749 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
750 | linear_map_hash_slots = __va(memblock_alloc_base( | |
751 | linear_map_hash_count, 1, ppc64_rma_size)); | |
752 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
753 | } | |
370a908d BH |
754 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
755 | ||
1da177e4 LT |
756 | /* On U3 based machines, we need to reserve the DART area and |
757 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
758 | * cacheable later on | |
759 | */ | |
1da177e4 LT |
760 | |
761 | /* create bolted the linear mapping in the hash table */ | |
28be7072 BH |
762 | for_each_memblock(memory, reg) { |
763 | base = (unsigned long)__va(reg->base); | |
764 | size = reg->size; | |
1da177e4 | 765 | |
5c339919 | 766 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 767 | base, size, prot); |
1da177e4 LT |
768 | |
769 | #ifdef CONFIG_U3_DART | |
770 | /* Do not map the DART space. Fortunately, it will be aligned | |
95f72d1e | 771 | * in such a way that it will not cross two memblock regions and |
3c726f8d BH |
772 | * will fit within a single 16Mb page. |
773 | * The DART space is assumed to be a full 16Mb region even if | |
774 | * we only use 2Mb of that space. We will use more of it later | |
775 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
776 | */ |
777 | DBG("DART base: %lx\n", dart_tablebase); | |
778 | ||
779 | if (dart_tablebase != 0 && dart_tablebase >= base | |
780 | && dart_tablebase < (base + size)) { | |
caf80e57 | 781 | unsigned long dart_table_end = dart_tablebase + 16 * MB; |
1da177e4 | 782 | if (base != dart_tablebase) |
3c726f8d | 783 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
9e88ba4e | 784 | __pa(base), prot, |
1189be65 PM |
785 | mmu_linear_psize, |
786 | mmu_kernel_ssize)); | |
caf80e57 | 787 | if ((base + size) > dart_table_end) |
3c726f8d | 788 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
caf80e57 ME |
789 | base + size, |
790 | __pa(dart_table_end), | |
9e88ba4e | 791 | prot, |
1189be65 PM |
792 | mmu_linear_psize, |
793 | mmu_kernel_ssize)); | |
1da177e4 LT |
794 | continue; |
795 | } | |
796 | #endif /* CONFIG_U3_DART */ | |
caf80e57 | 797 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 798 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
799 | } |
800 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
801 | |
802 | /* | |
803 | * If we have a memory_limit and we've allocated TCEs then we need to | |
804 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
805 | * case that the TCEs start below memory_limit. | |
806 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
807 | * for either 4K or 16MB pages. | |
808 | */ | |
809 | if (tce_alloc_start) { | |
b5666f70 ME |
810 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
811 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
812 | |
813 | if (base + size >= tce_alloc_start) | |
814 | tce_alloc_start = base + size + 1; | |
815 | ||
caf80e57 | 816 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 817 | __pa(tce_alloc_start), prot, |
1189be65 | 818 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
819 | } |
820 | ||
7d0daae4 | 821 | |
1da177e4 LT |
822 | DBG(" <- htab_initialize()\n"); |
823 | } | |
824 | #undef KB | |
825 | #undef MB | |
1da177e4 | 826 | |
757c74d2 | 827 | void __init early_init_mmu(void) |
799d6046 | 828 | { |
757c74d2 | 829 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
830 | * of memory. Has to be done before SLB initialization as this is |
831 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
832 | */ |
833 | htab_initialize(); | |
834 | ||
376af594 | 835 | /* Initialize SLB management */ |
13b3d13b | 836 | slb_initialize(); |
757c74d2 BH |
837 | } |
838 | ||
839 | #ifdef CONFIG_SMP | |
061d19f2 | 840 | void early_init_mmu_secondary(void) |
757c74d2 BH |
841 | { |
842 | /* Initialize hash table for that CPU */ | |
57cfb814 | 843 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
799d6046 | 844 | mtspr(SPRN_SDR1, _SDR1); |
757c74d2 | 845 | |
376af594 | 846 | /* Initialize SLB */ |
13b3d13b | 847 | slb_initialize(); |
799d6046 | 848 | } |
757c74d2 | 849 | #endif /* CONFIG_SMP */ |
799d6046 | 850 | |
1da177e4 LT |
851 | /* |
852 | * Called by asm hashtable.S for doing lazy icache flush | |
853 | */ | |
854 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
855 | { | |
856 | struct page *page; | |
857 | ||
76c8e25b BH |
858 | if (!pfn_valid(pte_pfn(pte))) |
859 | return pp; | |
860 | ||
1da177e4 LT |
861 | page = pte_page(pte); |
862 | ||
863 | /* page is dirty */ | |
864 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
865 | if (trap == 0x400) { | |
0895ecda | 866 | flush_dcache_icache_page(page); |
1da177e4 LT |
867 | set_bit(PG_arch_1, &page->flags); |
868 | } else | |
3c726f8d | 869 | pp |= HPTE_R_N; |
1da177e4 LT |
870 | } |
871 | return pp; | |
872 | } | |
873 | ||
3a8247cc | 874 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 875 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 876 | { |
7aa0727f AK |
877 | u64 lpsizes; |
878 | unsigned char *hpsizes; | |
879 | unsigned long index, mask_index; | |
3a8247cc PM |
880 | |
881 | if (addr < SLICE_LOW_TOP) { | |
2fc251a8 | 882 | lpsizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 883 | index = GET_LOW_SLICE_INDEX(addr); |
7aa0727f | 884 | return (lpsizes >> (index * 4)) & 0xF; |
3a8247cc | 885 | } |
2fc251a8 | 886 | hpsizes = get_paca()->mm_ctx_high_slices_psize; |
7aa0727f AK |
887 | index = GET_HIGH_SLICE_INDEX(addr); |
888 | mask_index = index & 0x1; | |
889 | return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF; | |
3a8247cc PM |
890 | } |
891 | ||
892 | #else | |
893 | unsigned int get_paca_psize(unsigned long addr) | |
894 | { | |
c33e54fa | 895 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
896 | } |
897 | #endif | |
898 | ||
721151d0 PM |
899 | /* |
900 | * Demote a segment to using 4k pages. | |
901 | * For now this makes the whole process use 4k pages. | |
902 | */ | |
721151d0 | 903 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 904 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 905 | { |
3a8247cc | 906 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 907 | return; |
3a8247cc | 908 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 909 | copro_flush_all_slbs(mm); |
a1dca346 | 910 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
c395465d MN |
911 | |
912 | copy_mm_to_paca(&mm->context); | |
fa28237c PM |
913 | slb_flush_and_rebolt(); |
914 | } | |
721151d0 | 915 | } |
16f1c746 | 916 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 917 | |
fa28237c PM |
918 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
919 | /* | |
920 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
921 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
922 | * | |
923 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 924 | * _PAGE_RWX: no access. |
fa28237c | 925 | */ |
d28513bc | 926 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 927 | { |
d28513bc | 928 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
929 | u32 spp = 0; |
930 | u32 **sbpm, *sbpp; | |
931 | ||
932 | if (ea >= spt->maxaddr) | |
933 | return 0; | |
b0d436c7 | 934 | if (ea < 0x100000000UL) { |
fa28237c PM |
935 | /* addresses below 4GB use spt->low_prot */ |
936 | sbpm = spt->low_prot; | |
937 | } else { | |
938 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
939 | if (!sbpm) | |
940 | return 0; | |
941 | } | |
942 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
943 | if (!sbpp) | |
944 | return 0; | |
945 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
946 | ||
947 | /* extract 2-bit bitfield for this 4k subpage */ | |
948 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
949 | ||
73a1441a AK |
950 | /* |
951 | * 0 -> full premission | |
952 | * 1 -> Read only | |
953 | * 2 -> no access. | |
954 | * We return the flag that need to be cleared. | |
955 | */ | |
956 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
957 | return spp; |
958 | } | |
959 | ||
960 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 961 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
962 | { |
963 | return 0; | |
964 | } | |
965 | #endif | |
966 | ||
4b8692c0 BH |
967 | void hash_failure_debug(unsigned long ea, unsigned long access, |
968 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 969 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
970 | { |
971 | if (!printk_ratelimit()) | |
972 | return; | |
973 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
974 | ea, access, current->comm); | |
d8139ebf AK |
975 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
976 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
977 | } |
978 | ||
09567e7f ME |
979 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
980 | int psize, bool user_region) | |
981 | { | |
982 | if (user_region) { | |
983 | if (psize != get_paca_psize(ea)) { | |
c395465d | 984 | copy_mm_to_paca(&mm->context); |
09567e7f ME |
985 | slb_flush_and_rebolt(); |
986 | } | |
987 | } else if (get_paca()->vmalloc_sllp != | |
988 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
989 | get_paca()->vmalloc_sllp = | |
990 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
991 | slb_vmalloc_update(); | |
992 | } | |
993 | } | |
994 | ||
1da177e4 LT |
995 | /* Result code is: |
996 | * 0 - handled | |
997 | * 1 - normal page fault | |
998 | * -1 - critical hash insertion error | |
fa28237c | 999 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1000 | */ |
aefa5688 AK |
1001 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1002 | unsigned long access, unsigned long trap, | |
1003 | unsigned long flags) | |
1da177e4 | 1004 | { |
891121e6 | 1005 | bool is_thp; |
ba12eede | 1006 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1007 | pgd_t *pgdir; |
1da177e4 | 1008 | unsigned long vsid; |
1da177e4 | 1009 | pte_t *ptep; |
a4fe3ce7 | 1010 | unsigned hugeshift; |
56aa4129 | 1011 | const struct cpumask *tmp; |
aefa5688 | 1012 | int rc, user_region = 0; |
1189be65 | 1013 | int psize, ssize; |
1da177e4 | 1014 | |
3c726f8d BH |
1015 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1016 | ea, access, trap); | |
cfcb3d80 | 1017 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1018 | |
3c726f8d | 1019 | /* Get region & vsid */ |
1da177e4 LT |
1020 | switch (REGION_ID(ea)) { |
1021 | case USER_REGION_ID: | |
1022 | user_region = 1; | |
3c726f8d BH |
1023 | if (! mm) { |
1024 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1025 | rc = 1; |
1026 | goto bail; | |
3c726f8d | 1027 | } |
16c2d476 | 1028 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
1029 | ssize = user_segment_size(ea); |
1030 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 1031 | break; |
1da177e4 | 1032 | case VMALLOC_REGION_ID: |
1189be65 | 1033 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1034 | if (ea < VMALLOC_END) |
1035 | psize = mmu_vmalloc_psize; | |
1036 | else | |
1037 | psize = mmu_io_psize; | |
1189be65 | 1038 | ssize = mmu_kernel_ssize; |
1da177e4 | 1039 | break; |
1da177e4 LT |
1040 | default: |
1041 | /* Not a valid range | |
1042 | * Send the problem up to do_page_fault | |
1043 | */ | |
ba12eede LZ |
1044 | rc = 1; |
1045 | goto bail; | |
1da177e4 | 1046 | } |
3c726f8d | 1047 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1048 | |
c60ac569 AK |
1049 | /* Bad address. */ |
1050 | if (!vsid) { | |
1051 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1052 | rc = 1; |
1053 | goto bail; | |
c60ac569 | 1054 | } |
3c726f8d | 1055 | /* Get pgdir */ |
1da177e4 | 1056 | pgdir = mm->pgd; |
ba12eede LZ |
1057 | if (pgdir == NULL) { |
1058 | rc = 1; | |
1059 | goto bail; | |
1060 | } | |
1da177e4 | 1061 | |
3c726f8d | 1062 | /* Check CPU locality */ |
56aa4129 RR |
1063 | tmp = cpumask_of(smp_processor_id()); |
1064 | if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) | |
aefa5688 | 1065 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1066 | |
16c2d476 | 1067 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1068 | /* If we use 4K pages and our psize is not 4K, then we might |
1069 | * be hitting a special driver mapping, and need to align the | |
1070 | * address before we fetch the PTE. | |
1071 | * | |
1072 | * It could also be a hugepage mapping, in which case this is | |
1073 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1074 | */ |
1075 | if (psize != MMU_PAGE_4K) | |
1076 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1077 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1078 | ||
3c726f8d | 1079 | /* Get PTE and page size from page tables */ |
891121e6 | 1080 | ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1081 | if (ptep == NULL || !pte_present(*ptep)) { |
1082 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1083 | rc = 1; |
1084 | goto bail; | |
3c726f8d BH |
1085 | } |
1086 | ||
ca91e6c0 BH |
1087 | /* Add _PAGE_PRESENT to the required access perm */ |
1088 | access |= _PAGE_PRESENT; | |
1089 | ||
1090 | /* Pre-check access permissions (will be re-checked atomically | |
1091 | * in __hash_page_XX but this pre-check is a fast path | |
1092 | */ | |
ac29c640 | 1093 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1094 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1095 | rc = 1; |
1096 | goto bail; | |
ca91e6c0 BH |
1097 | } |
1098 | ||
ba12eede | 1099 | if (hugeshift) { |
891121e6 | 1100 | if (is_thp) |
6d492ecc | 1101 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1102 | trap, flags, ssize, psize); |
6d492ecc AK |
1103 | #ifdef CONFIG_HUGETLB_PAGE |
1104 | else | |
1105 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1106 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1107 | #else |
1108 | else { | |
1109 | /* | |
1110 | * if we have hugeshift, and is not transhuge with | |
1111 | * hugetlb disabled, something is really wrong. | |
1112 | */ | |
1113 | rc = 1; | |
1114 | WARN_ON(1); | |
1115 | } | |
1116 | #endif | |
a1dca346 IM |
1117 | if (current->mm == mm) |
1118 | check_paca_psize(ea, mm, psize, user_region); | |
09567e7f | 1119 | |
ba12eede LZ |
1120 | goto bail; |
1121 | } | |
a4fe3ce7 | 1122 | |
3c726f8d BH |
1123 | #ifndef CONFIG_PPC_64K_PAGES |
1124 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1125 | #else | |
1126 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1127 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1128 | #endif | |
3c726f8d | 1129 | /* Do actual hashing */ |
16c2d476 | 1130 | #ifdef CONFIG_PPC_64K_PAGES |
721151d0 | 1131 | /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ |
3a8247cc | 1132 | if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) { |
721151d0 PM |
1133 | demote_segment_4k(mm, ea); |
1134 | psize = MMU_PAGE_4K; | |
1135 | } | |
1136 | ||
16f1c746 BH |
1137 | /* If this PTE is non-cacheable and we have restrictions on |
1138 | * using non cacheable large pages, then we switch to 4k | |
1139 | */ | |
1140 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && | |
1141 | (pte_val(*ptep) & _PAGE_NO_CACHE)) { | |
1142 | if (user_region) { | |
1143 | demote_segment_4k(mm, ea); | |
1144 | psize = MMU_PAGE_4K; | |
1145 | } else if (ea < VMALLOC_END) { | |
1146 | /* | |
1147 | * some driver did a non-cacheable mapping | |
1148 | * in vmalloc space, so switch vmalloc | |
1149 | * to 4k pages | |
1150 | */ | |
1151 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1152 | "to 4kB pages because of " | |
1153 | "non-cacheable mapping\n"); | |
1154 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1155 | copro_flush_all_slbs(mm); |
bf72aeba | 1156 | } |
16f1c746 | 1157 | } |
09567e7f | 1158 | |
0863d7f2 AK |
1159 | #endif /* CONFIG_PPC_64K_PAGES */ |
1160 | ||
a1dca346 IM |
1161 | if (current->mm == mm) |
1162 | check_paca_psize(ea, mm, psize, user_region); | |
16f1c746 | 1163 | |
73b341ef | 1164 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1165 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1166 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1167 | flags, ssize); | |
3c726f8d | 1168 | else |
73b341ef | 1169 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1170 | { |
a1128f8f | 1171 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1172 | if (access & spp) |
1173 | rc = -2; | |
1174 | else | |
1175 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1176 | flags, ssize, spp); |
fa28237c | 1177 | } |
3c726f8d | 1178 | |
4b8692c0 BH |
1179 | /* Dump some info in case of hash insertion failure, they should |
1180 | * never happen so it is really useful to know if/when they do | |
1181 | */ | |
1182 | if (rc == -1) | |
1183 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1184 | psize, pte_val(*ptep)); |
3c726f8d BH |
1185 | #ifndef CONFIG_PPC_64K_PAGES |
1186 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1187 | #else | |
1188 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1189 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1190 | #endif | |
1191 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1192 | |
1193 | bail: | |
1194 | exception_exit(prev_state); | |
3c726f8d | 1195 | return rc; |
1da177e4 | 1196 | } |
a1dca346 IM |
1197 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1198 | ||
aefa5688 AK |
1199 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1200 | unsigned long dsisr) | |
a1dca346 | 1201 | { |
aefa5688 | 1202 | unsigned long flags = 0; |
a1dca346 IM |
1203 | struct mm_struct *mm = current->mm; |
1204 | ||
1205 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1206 | mm = &init_mm; | |
1207 | ||
aefa5688 AK |
1208 | if (dsisr & DSISR_NOHPTE) |
1209 | flags |= HPTE_NOHPTE_UPDATE; | |
1210 | ||
1211 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1212 | } |
67207b96 | 1213 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1214 | |
106713a1 AK |
1215 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1216 | unsigned long dsisr) | |
1217 | { | |
c7d54842 | 1218 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1219 | unsigned long flags = 0; |
1220 | struct mm_struct *mm = current->mm; | |
1221 | ||
1222 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1223 | mm = &init_mm; | |
1224 | ||
1225 | if (dsisr & DSISR_NOHPTE) | |
1226 | flags |= HPTE_NOHPTE_UPDATE; | |
1227 | ||
1228 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1229 | access |= _PAGE_WRITE; |
106713a1 | 1230 | /* |
ac29c640 AK |
1231 | * We set _PAGE_PRIVILEGED only when |
1232 | * kernel mode access kernel space. | |
1233 | * | |
1234 | * _PAGE_PRIVILEGED is NOT set | |
1235 | * 1) when kernel mode access user space | |
1236 | * 2) user space access kernel space. | |
106713a1 | 1237 | */ |
ac29c640 | 1238 | access |= _PAGE_PRIVILEGED; |
106713a1 | 1239 | if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID)) |
ac29c640 | 1240 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1241 | |
1242 | if (trap == 0x400) | |
1243 | access |= _PAGE_EXEC; | |
1244 | ||
1245 | return hash_page_mm(mm, ea, access, trap, flags); | |
1246 | } | |
1247 | ||
3c726f8d BH |
1248 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1249 | unsigned long access, unsigned long trap) | |
1da177e4 | 1250 | { |
12bc9f6f | 1251 | int hugepage_shift; |
3c726f8d | 1252 | unsigned long vsid; |
0b97fee0 | 1253 | pgd_t *pgdir; |
3c726f8d | 1254 | pte_t *ptep; |
3c726f8d | 1255 | unsigned long flags; |
aefa5688 | 1256 | int rc, ssize, update_flags = 0; |
3c726f8d | 1257 | |
d0f13e3c BH |
1258 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1259 | ||
1260 | #ifdef CONFIG_PPC_MM_SLICES | |
1261 | /* We only prefault standard pages for now */ | |
2b02d139 | 1262 | if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize)) |
3c726f8d | 1263 | return; |
d0f13e3c | 1264 | #endif |
3c726f8d BH |
1265 | |
1266 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1267 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1268 | |
16f1c746 | 1269 | /* Get Linux PTE if available */ |
3c726f8d BH |
1270 | pgdir = mm->pgd; |
1271 | if (pgdir == NULL) | |
1272 | return; | |
0ac52dd7 AK |
1273 | |
1274 | /* Get VSID */ | |
1275 | ssize = user_segment_size(ea); | |
1276 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1277 | if (!vsid) | |
1278 | return; | |
1279 | /* | |
1280 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1281 | * saves us from holding multiple locks. | |
1282 | */ | |
1283 | local_irq_save(flags); | |
1284 | ||
12bc9f6f AK |
1285 | /* |
1286 | * THP pages use update_mmu_cache_pmd. We don't do | |
1287 | * hash preload there. Hence can ignore THP here | |
1288 | */ | |
891121e6 | 1289 | ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1290 | if (!ptep) |
0ac52dd7 | 1291 | goto out_exit; |
16f1c746 | 1292 | |
12bc9f6f | 1293 | WARN_ON(hugepage_shift); |
16f1c746 BH |
1294 | #ifdef CONFIG_PPC_64K_PAGES |
1295 | /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on | |
1296 | * a 64K kernel), then we don't preload, hash_page() will take | |
1297 | * care of it once we actually try to access the page. | |
1298 | * That way we don't have to duplicate all of the logic for segment | |
1299 | * page size demotion here | |
1300 | */ | |
1301 | if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE)) | |
0ac52dd7 | 1302 | goto out_exit; |
16f1c746 BH |
1303 | #endif /* CONFIG_PPC_64K_PAGES */ |
1304 | ||
16c2d476 | 1305 | /* Is that local to this CPU ? */ |
56aa4129 | 1306 | if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) |
aefa5688 | 1307 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1308 | |
1309 | /* Hash it in */ | |
73b341ef | 1310 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1311 | if (mm->context.user_psize == MMU_PAGE_64K) |
aefa5688 AK |
1312 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1313 | update_flags, ssize); | |
1da177e4 | 1314 | else |
73b341ef | 1315 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1316 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1317 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1318 | |
1319 | /* Dump some info in case of hash insertion failure, they should | |
1320 | * never happen so it is really useful to know if/when they do | |
1321 | */ | |
1322 | if (rc == -1) | |
1323 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1324 | mm->context.user_psize, |
1325 | mm->context.user_psize, | |
1326 | pte_val(*ptep)); | |
0ac52dd7 | 1327 | out_exit: |
3c726f8d BH |
1328 | local_irq_restore(flags); |
1329 | } | |
1330 | ||
f6ab0b92 BH |
1331 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1332 | * do not forget to update the assembly call site ! | |
1333 | */ | |
5524a27d | 1334 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1335 | unsigned long flags) |
3c726f8d BH |
1336 | { |
1337 | unsigned long hash, index, shift, hidx, slot; | |
aefa5688 | 1338 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1339 | |
5524a27d AK |
1340 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1341 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
1342 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
1343 | hidx = __rpte_to_hidx(pte, index); |
1344 | if (hidx & _PTEIDX_SECONDARY) | |
1345 | hash = ~hash; | |
1346 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1347 | slot += hidx & _PTEIDX_GROUP_IX; | |
5c339919 | 1348 | DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx); |
db3d8534 AK |
1349 | /* |
1350 | * We use same base page size and actual psize, because we don't | |
1351 | * use these functions for hugepage | |
1352 | */ | |
1353 | ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local); | |
3c726f8d | 1354 | } pte_iterate_hashed_end(); |
bc2a9408 MN |
1355 | |
1356 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1357 | /* Transactions are not aborted by tlbiel, only tlbie. | |
1358 | * Without, syncing a page back to a block device w/ PIO could pick up | |
1359 | * transactional data (bad!) so we force an abort here. Before the | |
1360 | * sync the page will be made read-only, which will flush_hash_page. | |
1361 | * BIG ISSUE here: if the kernel uses a page from userspace without | |
1362 | * unmapping it first, it may see the speculated version. | |
1363 | */ | |
1364 | if (local && cpu_has_feature(CPU_FTR_TM) && | |
c2fd22df | 1365 | current->thread.regs && |
bc2a9408 MN |
1366 | MSR_TM_ACTIVE(current->thread.regs->msr)) { |
1367 | tm_enable(); | |
1368 | tm_abort(TM_CAUSE_TLBI); | |
1369 | } | |
1370 | #endif | |
1da177e4 LT |
1371 | } |
1372 | ||
f1581bf1 AK |
1373 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1374 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1375 | pmd_t *pmdp, unsigned int psize, int ssize, |
1376 | unsigned long flags) | |
f1581bf1 AK |
1377 | { |
1378 | int i, max_hpte_count, valid; | |
1379 | unsigned long s_addr; | |
1380 | unsigned char *hpte_slot_array; | |
1381 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1382 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1383 | |
1384 | s_addr = addr & HPAGE_PMD_MASK; | |
1385 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1386 | /* | |
1387 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1388 | * we will find the below NULL. This happens when we do | |
1389 | * split_huge_page_pmd | |
1390 | */ | |
1391 | if (!hpte_slot_array) | |
1392 | return; | |
1393 | ||
d557b098 AK |
1394 | if (ppc_md.hugepage_invalidate) { |
1395 | ppc_md.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1396 | psize, ssize, local); | |
1397 | goto tm_abort; | |
1398 | } | |
f1581bf1 AK |
1399 | /* |
1400 | * No bluk hpte removal support, invalidate each entry | |
1401 | */ | |
1402 | shift = mmu_psize_defs[psize].shift; | |
1403 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1404 | for (i = 0; i < max_hpte_count; i++) { | |
1405 | /* | |
1406 | * 8 bits per each hpte entries | |
1407 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1408 | */ | |
1409 | valid = hpte_valid(hpte_slot_array, i); | |
1410 | if (!valid) | |
1411 | continue; | |
1412 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1413 | ||
1414 | /* get the vpn */ | |
1415 | addr = s_addr + (i * (1ul << shift)); | |
1416 | vpn = hpt_vpn(addr, vsid, ssize); | |
1417 | hash = hpt_hash(vpn, shift, ssize); | |
1418 | if (hidx & _PTEIDX_SECONDARY) | |
1419 | hash = ~hash; | |
1420 | ||
1421 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1422 | slot += hidx & _PTEIDX_GROUP_IX; | |
1423 | ppc_md.hpte_invalidate(slot, vpn, psize, | |
d557b098 AK |
1424 | MMU_PAGE_16M, ssize, local); |
1425 | } | |
1426 | tm_abort: | |
1427 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1428 | /* Transactions are not aborted by tlbiel, only tlbie. | |
1429 | * Without, syncing a page back to a block device w/ PIO could pick up | |
1430 | * transactional data (bad!) so we force an abort here. Before the | |
1431 | * sync the page will be made read-only, which will flush_hash_page. | |
1432 | * BIG ISSUE here: if the kernel uses a page from userspace without | |
1433 | * unmapping it first, it may see the speculated version. | |
1434 | */ | |
1435 | if (local && cpu_has_feature(CPU_FTR_TM) && | |
1436 | current->thread.regs && | |
1437 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1438 | tm_enable(); | |
1439 | tm_abort(TM_CAUSE_TLBI); | |
f1581bf1 | 1440 | } |
d557b098 | 1441 | #endif |
2e826695 | 1442 | return; |
f1581bf1 AK |
1443 | } |
1444 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1445 | ||
61b1a942 | 1446 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1447 | { |
3c726f8d | 1448 | if (ppc_md.flush_hash_range) |
61b1a942 | 1449 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 1450 | else { |
1da177e4 | 1451 | int i; |
61b1a942 | 1452 | struct ppc64_tlb_batch *batch = |
69111bac | 1453 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1454 | |
1455 | for (i = 0; i < number; i++) | |
5524a27d | 1456 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1457 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1458 | } |
1459 | } | |
1460 | ||
1da177e4 LT |
1461 | /* |
1462 | * low_hash_fault is called when we the low level hash code failed | |
1463 | * to instert a PTE due to an hypervisor error | |
1464 | */ | |
fa28237c | 1465 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1466 | { |
ba12eede LZ |
1467 | enum ctx_state prev_state = exception_enter(); |
1468 | ||
1da177e4 | 1469 | if (user_mode(regs)) { |
fa28237c PM |
1470 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1471 | if (rc == -2) | |
1472 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1473 | else | |
1474 | #endif | |
1475 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1476 | } else | |
1477 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1478 | |
1479 | exception_exit(prev_state); | |
1da177e4 | 1480 | } |
370a908d | 1481 | |
b170bd3d LZ |
1482 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1483 | unsigned long pa, unsigned long rflags, | |
1484 | unsigned long vflags, int psize, int ssize) | |
1485 | { | |
1486 | unsigned long hpte_group; | |
1487 | long slot; | |
1488 | ||
1489 | repeat: | |
1490 | hpte_group = ((hash & htab_hash_mask) * | |
1491 | HPTES_PER_GROUP) & ~0x7UL; | |
1492 | ||
1493 | /* Insert into the hash table, primary slot */ | |
1494 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags, | |
b1022fbd | 1495 | psize, psize, ssize); |
b170bd3d LZ |
1496 | |
1497 | /* Primary is full, try the secondary */ | |
1498 | if (unlikely(slot == -1)) { | |
1499 | hpte_group = ((~hash & htab_hash_mask) * | |
1500 | HPTES_PER_GROUP) & ~0x7UL; | |
1501 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, | |
1502 | vflags | HPTE_V_SECONDARY, | |
b1022fbd | 1503 | psize, psize, ssize); |
b170bd3d LZ |
1504 | if (slot == -1) { |
1505 | if (mftb() & 0x1) | |
1506 | hpte_group = ((hash & htab_hash_mask) * | |
1507 | HPTES_PER_GROUP)&~0x7UL; | |
1508 | ||
1509 | ppc_md.hpte_remove(hpte_group); | |
1510 | goto repeat; | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | return slot; | |
1515 | } | |
1516 | ||
370a908d BH |
1517 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1518 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1519 | { | |
016af59f | 1520 | unsigned long hash; |
1189be65 | 1521 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1522 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1523 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1524 | long ret; |
370a908d | 1525 | |
5524a27d | 1526 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1527 | |
c60ac569 AK |
1528 | /* Don't create HPTE entries for bad address */ |
1529 | if (!vsid) | |
1530 | return; | |
016af59f LZ |
1531 | |
1532 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1533 | HPTE_V_BOLTED, | |
1534 | mmu_linear_psize, mmu_kernel_ssize); | |
1535 | ||
370a908d BH |
1536 | BUG_ON (ret < 0); |
1537 | spin_lock(&linear_map_hash_lock); | |
1538 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1539 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1540 | spin_unlock(&linear_map_hash_lock); | |
1541 | } | |
1542 | ||
1543 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1544 | { | |
1189be65 PM |
1545 | unsigned long hash, hidx, slot; |
1546 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1547 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1548 | |
5524a27d | 1549 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1550 | spin_lock(&linear_map_hash_lock); |
1551 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1552 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1553 | linear_map_hash_slots[lmi] = 0; | |
1554 | spin_unlock(&linear_map_hash_lock); | |
1555 | if (hidx & _PTEIDX_SECONDARY) | |
1556 | hash = ~hash; | |
1557 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1558 | slot += hidx & _PTEIDX_GROUP_IX; | |
db3d8534 AK |
1559 | ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize, |
1560 | mmu_kernel_ssize, 0); | |
370a908d BH |
1561 | } |
1562 | ||
031bc574 | 1563 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1564 | { |
1565 | unsigned long flags, vaddr, lmi; | |
1566 | int i; | |
1567 | ||
1568 | local_irq_save(flags); | |
1569 | for (i = 0; i < numpages; i++, page++) { | |
1570 | vaddr = (unsigned long)page_address(page); | |
1571 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1572 | if (lmi >= linear_map_hash_count) | |
1573 | continue; | |
1574 | if (enable) | |
1575 | kernel_map_linear_page(vaddr, lmi); | |
1576 | else | |
1577 | kernel_unmap_linear_page(vaddr, lmi); | |
1578 | } | |
1579 | local_irq_restore(flags); | |
1580 | } | |
1581 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 BH |
1582 | |
1583 | void setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
1584 | phys_addr_t first_memblock_size) | |
1585 | { | |
1586 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1587 | * physical on those processors | |
1588 | */ | |
1589 | BUG_ON(first_memblock_base != 0); | |
1590 | ||
1591 | /* On LPAR systems, the first entry is our RMA region, | |
1592 | * non-LPAR 64-bit hash MMU systems don't have a limitation | |
1593 | * on real mode access, but using the first entry works well | |
1594 | * enough. We also clamp it to 1G to avoid some funky things | |
1595 | * such as RTAS bugs etc... | |
1596 | */ | |
1597 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
1598 | ||
1599 | /* Finally limit subsequent allocations */ | |
1600 | memblock_set_current_limit(ppc64_rma_size); | |
1601 | } |