Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
66b15db6 | 30 | #include <linux/export.h> |
1da177e4 LT |
31 | #include <linux/ctype.h> |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
95f72d1e | 35 | #include <linux/memblock.h> |
ba12eede | 36 | #include <linux/context_tracking.h> |
1da177e4 | 37 | |
1da177e4 LT |
38 | #include <asm/processor.h> |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/mmu.h> | |
41 | #include <asm/mmu_context.h> | |
42 | #include <asm/page.h> | |
43 | #include <asm/types.h> | |
1da177e4 LT |
44 | #include <asm/uaccess.h> |
45 | #include <asm/machdep.h> | |
d9b2b2a2 | 46 | #include <asm/prom.h> |
1da177e4 LT |
47 | #include <asm/tlbflush.h> |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
1da177e4 | 53 | #include <asm/sections.h> |
d0f13e3c | 54 | #include <asm/spu.h> |
aa39be09 | 55 | #include <asm/udbg.h> |
b68a70c4 | 56 | #include <asm/code-patching.h> |
3ccc00a7 | 57 | #include <asm/fadump.h> |
f5339277 | 58 | #include <asm/firmware.h> |
bc2a9408 | 59 | #include <asm/tm.h> |
1da177e4 LT |
60 | |
61 | #ifdef DEBUG | |
62 | #define DBG(fmt...) udbg_printf(fmt) | |
63 | #else | |
64 | #define DBG(fmt...) | |
65 | #endif | |
66 | ||
3c726f8d BH |
67 | #ifdef DEBUG_LOW |
68 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
69 | #else | |
70 | #define DBG_LOW(fmt...) | |
71 | #endif | |
72 | ||
73 | #define KB (1024) | |
74 | #define MB (1024*KB) | |
658013e9 | 75 | #define GB (1024L*MB) |
3c726f8d | 76 | |
1da177e4 LT |
77 | /* |
78 | * Note: pte --> Linux PTE | |
79 | * HPTE --> PowerPC Hashed Page Table Entry | |
80 | * | |
81 | * Execution context: | |
82 | * htab_initialize is called with the MMU off (of course), but | |
83 | * the kernel has been copied down to zero so it can directly | |
84 | * reference global data. At this point it is very difficult | |
85 | * to print debug info. | |
86 | * | |
87 | */ | |
88 | ||
89 | #ifdef CONFIG_U3_DART | |
90 | extern unsigned long dart_tablebase; | |
91 | #endif /* CONFIG_U3_DART */ | |
92 | ||
799d6046 PM |
93 | static unsigned long _SDR1; |
94 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 95 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 96 | |
8e561e7e | 97 | struct hash_pte *htab_address; |
337a7128 | 98 | unsigned long htab_size_bytes; |
96e28449 | 99 | unsigned long htab_hash_mask; |
4ab79aa8 | 100 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d BH |
101 | int mmu_linear_psize = MMU_PAGE_4K; |
102 | int mmu_virtual_psize = MMU_PAGE_4K; | |
bf72aeba | 103 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
104 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
105 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
106 | #endif | |
bf72aeba | 107 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 PM |
108 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
109 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; | |
584f8b71 | 110 | u16 mmu_slb_size = 64; |
4ab79aa8 | 111 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
112 | #ifdef CONFIG_PPC_64K_PAGES |
113 | int mmu_ci_restrictions; | |
114 | #endif | |
370a908d BH |
115 | #ifdef CONFIG_DEBUG_PAGEALLOC |
116 | static u8 *linear_map_hash_slots; | |
117 | static unsigned long linear_map_hash_count; | |
ed166692 | 118 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 119 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 120 | |
3c726f8d BH |
121 | /* There are definitions of page sizes arrays to be used when none |
122 | * is provided by the firmware. | |
123 | */ | |
1da177e4 | 124 | |
3c726f8d BH |
125 | /* Pre-POWER4 CPUs (4k pages only) |
126 | */ | |
09de9ff8 | 127 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
128 | [MMU_PAGE_4K] = { |
129 | .shift = 12, | |
130 | .sllp = 0, | |
b1022fbd | 131 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
132 | .avpnm = 0, |
133 | .tlbiel = 0, | |
134 | }, | |
135 | }; | |
136 | ||
137 | /* POWER4, GPUL, POWER5 | |
138 | * | |
139 | * Support for 16Mb large pages | |
140 | */ | |
09de9ff8 | 141 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
142 | [MMU_PAGE_4K] = { |
143 | .shift = 12, | |
144 | .sllp = 0, | |
b1022fbd | 145 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
146 | .avpnm = 0, |
147 | .tlbiel = 1, | |
148 | }, | |
149 | [MMU_PAGE_16M] = { | |
150 | .shift = 24, | |
151 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
152 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
153 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
154 | .avpnm = 0x1UL, |
155 | .tlbiel = 0, | |
156 | }, | |
157 | }; | |
158 | ||
bc033b63 BH |
159 | static unsigned long htab_convert_pte_flags(unsigned long pteflags) |
160 | { | |
161 | unsigned long rflags = pteflags & 0x1fa; | |
162 | ||
163 | /* _PAGE_EXEC -> NOEXEC */ | |
164 | if ((pteflags & _PAGE_EXEC) == 0) | |
165 | rflags |= HPTE_R_N; | |
166 | ||
167 | /* PP bits. PAGE_USER is already PP bit 0x2, so we only | |
168 | * need to add in 0x1 if it's a read-only user page | |
169 | */ | |
170 | if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) && | |
171 | (pteflags & _PAGE_DIRTY))) | |
172 | rflags |= 1; | |
c8c06f5a AK |
173 | /* |
174 | * Always add "C" bit for perf. Memory coherence is always enabled | |
175 | */ | |
176 | return rflags | HPTE_R_C | HPTE_R_M; | |
bc033b63 | 177 | } |
3c726f8d BH |
178 | |
179 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 180 | unsigned long pstart, unsigned long prot, |
1189be65 | 181 | int psize, int ssize) |
1da177e4 | 182 | { |
3c726f8d BH |
183 | unsigned long vaddr, paddr; |
184 | unsigned int step, shift; | |
3c726f8d | 185 | int ret = 0; |
1da177e4 | 186 | |
3c726f8d BH |
187 | shift = mmu_psize_defs[psize].shift; |
188 | step = 1 << shift; | |
1da177e4 | 189 | |
bc033b63 BH |
190 | prot = htab_convert_pte_flags(prot); |
191 | ||
192 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
193 | vstart, vend, pstart, prot, psize, ssize); | |
194 | ||
3c726f8d BH |
195 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
196 | vaddr += step, paddr += step) { | |
370a908d | 197 | unsigned long hash, hpteg; |
1189be65 | 198 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 199 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
200 | unsigned long tprot = prot; |
201 | ||
c60ac569 AK |
202 | /* |
203 | * If we hit a bad address return error. | |
204 | */ | |
205 | if (!vsid) | |
206 | return -1; | |
9e88ba4e | 207 | /* Make kernel text executable */ |
549e8152 | 208 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 209 | tprot &= ~HPTE_R_N; |
1da177e4 | 210 | |
b18db0b8 AG |
211 | /* Make kvm guest trampolines executable */ |
212 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
213 | tprot &= ~HPTE_R_N; | |
214 | ||
429d2e83 MS |
215 | /* |
216 | * If relocatable, check if it overlaps interrupt vectors that | |
217 | * are copied down to real 0. For relocatable kernel | |
218 | * (e.g. kdump case) we copy interrupt vectors down to real | |
219 | * address 0. Mark that region as executable. This is | |
220 | * because on p8 system with relocation on exception feature | |
221 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
222 | * in order to execute the interrupt handlers in virtual | |
223 | * mode the vector region need to be marked as executable. | |
224 | */ | |
225 | if ((PHYSICAL_START > MEMORY_START) && | |
226 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
227 | tprot &= ~HPTE_R_N; | |
228 | ||
5524a27d | 229 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
230 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
231 | ||
c30a4df3 | 232 | BUG_ON(!ppc_md.hpte_insert); |
5524a27d | 233 | ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot, |
b1022fbd | 234 | HPTE_V_BOLTED, psize, psize, ssize); |
c30a4df3 | 235 | |
3c726f8d BH |
236 | if (ret < 0) |
237 | break; | |
370a908d BH |
238 | #ifdef CONFIG_DEBUG_PAGEALLOC |
239 | if ((paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
240 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; | |
241 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
242 | } |
243 | return ret < 0 ? ret : 0; | |
244 | } | |
1da177e4 | 245 | |
ae86f008 | 246 | #ifdef CONFIG_MEMORY_HOTPLUG |
ed5694a8 | 247 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
248 | int psize, int ssize) |
249 | { | |
250 | unsigned long vaddr; | |
251 | unsigned int step, shift; | |
252 | ||
253 | shift = mmu_psize_defs[psize].shift; | |
254 | step = 1 << shift; | |
255 | ||
256 | if (!ppc_md.hpte_removebolted) { | |
52db9b44 BP |
257 | printk(KERN_WARNING "Platform doesn't implement " |
258 | "hpte_removebolted\n"); | |
259 | return -EINVAL; | |
f8c8803b BP |
260 | } |
261 | ||
262 | for (vaddr = vstart; vaddr < vend; vaddr += step) | |
263 | ppc_md.hpte_removebolted(vaddr, psize, ssize); | |
52db9b44 BP |
264 | |
265 | return 0; | |
f8c8803b | 266 | } |
ae86f008 | 267 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
f8c8803b | 268 | |
1189be65 PM |
269 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
270 | const char *uname, int depth, | |
271 | void *data) | |
272 | { | |
9d0c4dfe RH |
273 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
274 | const __be32 *prop; | |
275 | int size = 0; | |
1189be65 PM |
276 | |
277 | /* We are scanning "cpu" nodes only */ | |
278 | if (type == NULL || strcmp(type, "cpu") != 0) | |
279 | return 0; | |
280 | ||
12f04f2b | 281 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
282 | if (prop == NULL) |
283 | return 0; | |
284 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 285 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 286 | DBG("1T segment support detected\n"); |
44ae3ab3 | 287 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 288 | return 1; |
1189be65 | 289 | } |
1189be65 | 290 | } |
44ae3ab3 | 291 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
292 | return 0; |
293 | } | |
294 | ||
295 | static void __init htab_init_seg_sizes(void) | |
296 | { | |
297 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
298 | } | |
299 | ||
b1022fbd AK |
300 | static int __init get_idx_from_shift(unsigned int shift) |
301 | { | |
302 | int idx = -1; | |
303 | ||
304 | switch (shift) { | |
305 | case 0xc: | |
306 | idx = MMU_PAGE_4K; | |
307 | break; | |
308 | case 0x10: | |
309 | idx = MMU_PAGE_64K; | |
310 | break; | |
311 | case 0x14: | |
312 | idx = MMU_PAGE_1M; | |
313 | break; | |
314 | case 0x18: | |
315 | idx = MMU_PAGE_16M; | |
316 | break; | |
317 | case 0x22: | |
318 | idx = MMU_PAGE_16G; | |
319 | break; | |
320 | } | |
321 | return idx; | |
322 | } | |
323 | ||
3c726f8d BH |
324 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
325 | const char *uname, int depth, | |
326 | void *data) | |
327 | { | |
9d0c4dfe RH |
328 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
329 | const __be32 *prop; | |
330 | int size = 0; | |
3c726f8d BH |
331 | |
332 | /* We are scanning "cpu" nodes only */ | |
333 | if (type == NULL || strcmp(type, "cpu") != 0) | |
334 | return 0; | |
335 | ||
12f04f2b | 336 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
3c726f8d | 337 | if (prop != NULL) { |
3dc4feca | 338 | pr_info("Page sizes from device-tree:\n"); |
3c726f8d | 339 | size /= 4; |
44ae3ab3 | 340 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); |
3c726f8d | 341 | while(size > 0) { |
12f04f2b AB |
342 | unsigned int base_shift = be32_to_cpu(prop[0]); |
343 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
344 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
3c726f8d | 345 | struct mmu_psize_def *def; |
b1022fbd | 346 | int idx, base_idx; |
3c726f8d BH |
347 | |
348 | size -= 3; prop += 3; | |
b1022fbd AK |
349 | base_idx = get_idx_from_shift(base_shift); |
350 | if (base_idx < 0) { | |
351 | /* | |
352 | * skip the pte encoding also | |
353 | */ | |
354 | prop += lpnum * 2; size -= lpnum * 2; | |
355 | continue; | |
3c726f8d | 356 | } |
b1022fbd AK |
357 | def = &mmu_psize_defs[base_idx]; |
358 | if (base_idx == MMU_PAGE_16M) | |
44ae3ab3 | 359 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; |
b1022fbd AK |
360 | |
361 | def->shift = base_shift; | |
362 | if (base_shift <= 23) | |
3c726f8d BH |
363 | def->avpnm = 0; |
364 | else | |
b1022fbd | 365 | def->avpnm = (1 << (base_shift - 23)) - 1; |
3c726f8d | 366 | def->sllp = slbenc; |
b1022fbd AK |
367 | /* |
368 | * We don't know for sure what's up with tlbiel, so | |
3c726f8d BH |
369 | * for now we only set it for 4K and 64K pages |
370 | */ | |
b1022fbd | 371 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) |
3c726f8d BH |
372 | def->tlbiel = 1; |
373 | else | |
374 | def->tlbiel = 0; | |
375 | ||
b1022fbd | 376 | while (size > 0 && lpnum) { |
12f04f2b AB |
377 | unsigned int shift = be32_to_cpu(prop[0]); |
378 | int penc = be32_to_cpu(prop[1]); | |
b1022fbd AK |
379 | |
380 | prop += 2; size -= 2; | |
381 | lpnum--; | |
382 | ||
383 | idx = get_idx_from_shift(shift); | |
384 | if (idx < 0) | |
385 | continue; | |
386 | ||
387 | if (penc == -1) | |
388 | pr_err("Invalid penc for base_shift=%d " | |
389 | "shift=%d\n", base_shift, shift); | |
390 | ||
391 | def->penc[idx] = penc; | |
3dc4feca AK |
392 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," |
393 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
394 | base_shift, shift, def->sllp, | |
395 | def->avpnm, def->tlbiel, def->penc[idx]); | |
b1022fbd | 396 | } |
1da177e4 | 397 | } |
3c726f8d BH |
398 | return 1; |
399 | } | |
400 | return 0; | |
401 | } | |
402 | ||
e16a9c09 | 403 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
404 | /* Scan for 16G memory blocks that have been set aside for huge pages |
405 | * and reserve those blocks for 16G huge pages. | |
406 | */ | |
407 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
408 | const char *uname, int depth, | |
409 | void *data) { | |
9d0c4dfe RH |
410 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
411 | const __be64 *addr_prop; | |
412 | const __be32 *page_count_prop; | |
658013e9 JT |
413 | unsigned int expected_pages; |
414 | long unsigned int phys_addr; | |
415 | long unsigned int block_size; | |
416 | ||
417 | /* We are scanning "memory" nodes only */ | |
418 | if (type == NULL || strcmp(type, "memory") != 0) | |
419 | return 0; | |
420 | ||
421 | /* This property is the log base 2 of the number of virtual pages that | |
422 | * will represent this memory block. */ | |
423 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
424 | if (page_count_prop == NULL) | |
425 | return 0; | |
12f04f2b | 426 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
427 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
428 | if (addr_prop == NULL) | |
429 | return 0; | |
12f04f2b AB |
430 | phys_addr = be64_to_cpu(addr_prop[0]); |
431 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
432 | if (block_size != (16 * GB)) |
433 | return 0; | |
434 | printk(KERN_INFO "Huge page(16GB) memory: " | |
435 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
436 | phys_addr, block_size, expected_pages); | |
95f72d1e YL |
437 | if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) { |
438 | memblock_reserve(phys_addr, block_size * expected_pages); | |
4792adba JT |
439 | add_gpage(phys_addr, block_size, expected_pages); |
440 | } | |
658013e9 JT |
441 | return 0; |
442 | } | |
e16a9c09 | 443 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 444 | |
b1022fbd AK |
445 | static void mmu_psize_set_default_penc(void) |
446 | { | |
447 | int bpsize, apsize; | |
448 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
449 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
450 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
451 | } | |
452 | ||
9048e648 AG |
453 | #ifdef CONFIG_PPC_64K_PAGES |
454 | ||
455 | static bool might_have_hea(void) | |
456 | { | |
457 | /* | |
458 | * The HEA ethernet adapter requires awareness of the | |
459 | * GX bus. Without that awareness we can easily assume | |
460 | * we will never see an HEA ethernet device. | |
461 | */ | |
462 | #ifdef CONFIG_IBMEBUS | |
463 | return !cpu_has_feature(CPU_FTR_ARCH_207S); | |
464 | #else | |
465 | return false; | |
466 | #endif | |
467 | } | |
468 | ||
469 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
470 | ||
3c726f8d BH |
471 | static void __init htab_init_page_sizes(void) |
472 | { | |
473 | int rc; | |
474 | ||
b1022fbd AK |
475 | /* se the invalid penc to -1 */ |
476 | mmu_psize_set_default_penc(); | |
477 | ||
3c726f8d BH |
478 | /* Default to 4K pages only */ |
479 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
480 | sizeof(mmu_psize_defaults_old)); | |
481 | ||
482 | /* | |
483 | * Try to find the available page sizes in the device-tree | |
484 | */ | |
485 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
486 | if (rc != 0) /* Found */ | |
487 | goto found; | |
488 | ||
489 | /* | |
490 | * Not in the device-tree, let's fallback on known size | |
491 | * list for 16M capable GP & GR | |
492 | */ | |
44ae3ab3 | 493 | if (mmu_has_feature(MMU_FTR_16M_PAGE)) |
3c726f8d BH |
494 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
495 | sizeof(mmu_psize_defaults_gp)); | |
496 | found: | |
370a908d | 497 | #ifndef CONFIG_DEBUG_PAGEALLOC |
3c726f8d BH |
498 | /* |
499 | * Pick a size for the linear mapping. Currently, we only support | |
500 | * 16M, 1M and 4K which is the default | |
501 | */ | |
502 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
503 | mmu_linear_psize = MMU_PAGE_16M; | |
504 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
505 | mmu_linear_psize = MMU_PAGE_1M; | |
370a908d | 506 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
3c726f8d | 507 | |
bf72aeba | 508 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
509 | /* |
510 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
511 | * 64K for user mappings and vmalloc if supported by the processor. |
512 | * We only use 64k for ioremap if the processor | |
513 | * (and firmware) support cache-inhibited large pages. | |
514 | * If not, we use 4k and set mmu_ci_restrictions so that | |
515 | * hash_page knows to switch processes that use cache-inhibited | |
516 | * mappings to 4k pages. | |
3c726f8d | 517 | */ |
bf72aeba | 518 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 519 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 520 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
521 | if (mmu_linear_psize == MMU_PAGE_4K) |
522 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 523 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 524 | /* |
9048e648 AG |
525 | * When running on pSeries using 64k pages for ioremap |
526 | * would stop us accessing the HEA ethernet. So if we | |
527 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 528 | */ |
9048e648 | 529 | if (!might_have_hea() || !machine_is(pseries)) |
cfe666b1 PM |
530 | mmu_io_psize = MMU_PAGE_64K; |
531 | } else | |
bf72aeba PM |
532 | mmu_ci_restrictions = 1; |
533 | } | |
370a908d | 534 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 535 | |
cec08e7a BH |
536 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
537 | /* We try to use 16M pages for vmemmap if that is supported | |
538 | * and we have at least 1G of RAM at boot | |
539 | */ | |
540 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 541 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
542 | mmu_vmemmap_psize = MMU_PAGE_16M; |
543 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
544 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
545 | else | |
546 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
547 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
548 | ||
bf72aeba | 549 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
550 | "virtual = %d, io = %d" |
551 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
552 | ", vmemmap = %d" | |
553 | #endif | |
554 | "\n", | |
3c726f8d | 555 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 556 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
557 | mmu_psize_defs[mmu_io_psize].shift |
558 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
559 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
560 | #endif | |
561 | ); | |
3c726f8d BH |
562 | |
563 | #ifdef CONFIG_HUGETLB_PAGE | |
658013e9 JT |
564 | /* Reserve 16G huge page memory sections for huge pages */ |
565 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
3c726f8d BH |
566 | #endif /* CONFIG_HUGETLB_PAGE */ |
567 | } | |
568 | ||
569 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
570 | const char *uname, int depth, | |
571 | void *data) | |
572 | { | |
9d0c4dfe RH |
573 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
574 | const __be32 *prop; | |
3c726f8d BH |
575 | |
576 | /* We are scanning "cpu" nodes only */ | |
577 | if (type == NULL || strcmp(type, "cpu") != 0) | |
578 | return 0; | |
579 | ||
12f04f2b | 580 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
581 | if (prop != NULL) { |
582 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 583 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 584 | return 1; |
1da177e4 | 585 | } |
3c726f8d | 586 | return 0; |
1da177e4 LT |
587 | } |
588 | ||
3c726f8d | 589 | static unsigned long __init htab_get_table_size(void) |
3eac8c69 | 590 | { |
13870b65 | 591 | unsigned long mem_size, rnd_mem_size, pteg_count, psize; |
3eac8c69 | 592 | |
3c726f8d | 593 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 594 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 595 | * calculate it now based on the total RAM size |
3eac8c69 | 596 | */ |
3c726f8d BH |
597 | if (ppc64_pft_size == 0) |
598 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
599 | if (ppc64_pft_size) |
600 | return 1UL << ppc64_pft_size; | |
601 | ||
602 | /* round mem_size up to next power of 2 */ | |
95f72d1e | 603 | mem_size = memblock_phys_mem_size(); |
799d6046 PM |
604 | rnd_mem_size = 1UL << __ilog2(mem_size); |
605 | if (rnd_mem_size < mem_size) | |
3eac8c69 PM |
606 | rnd_mem_size <<= 1; |
607 | ||
608 | /* # pages / 2 */ | |
13870b65 AB |
609 | psize = mmu_psize_defs[mmu_virtual_psize].shift; |
610 | pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11); | |
3eac8c69 PM |
611 | |
612 | return pteg_count << 7; | |
613 | } | |
614 | ||
54b79248 | 615 | #ifdef CONFIG_MEMORY_HOTPLUG |
a1194097 | 616 | int create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 617 | { |
a1194097 | 618 | return htab_bolt_mapping(start, end, __pa(start), |
f5ea64dc | 619 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, |
a1194097 | 620 | mmu_kernel_ssize); |
54b79248 | 621 | } |
f8c8803b | 622 | |
52db9b44 | 623 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 624 | { |
52db9b44 BP |
625 | return htab_remove_mapping(start, end, mmu_linear_psize, |
626 | mmu_kernel_ssize); | |
f8c8803b | 627 | } |
54b79248 MK |
628 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
629 | ||
b86206e4 AB |
630 | extern u32 htab_call_hpte_insert1[]; |
631 | extern u32 htab_call_hpte_insert2[]; | |
632 | extern u32 htab_call_hpte_remove[]; | |
633 | extern u32 htab_call_hpte_updatepp[]; | |
634 | extern u32 ht64_call_hpte_insert1[]; | |
635 | extern u32 ht64_call_hpte_insert2[]; | |
636 | extern u32 ht64_call_hpte_remove[]; | |
637 | extern u32 ht64_call_hpte_updatepp[]; | |
7d0daae4 ME |
638 | |
639 | static void __init htab_finish_init(void) | |
640 | { | |
16c2d476 | 641 | #ifdef CONFIG_PPC_HAS_HASH_64K |
b68a70c4 | 642 | patch_branch(ht64_call_hpte_insert1, |
26f92060 | 643 | ppc_function_entry(ppc_md.hpte_insert), |
b68a70c4 AB |
644 | BRANCH_SET_LINK); |
645 | patch_branch(ht64_call_hpte_insert2, | |
26f92060 | 646 | ppc_function_entry(ppc_md.hpte_insert), |
b68a70c4 AB |
647 | BRANCH_SET_LINK); |
648 | patch_branch(ht64_call_hpte_remove, | |
26f92060 | 649 | ppc_function_entry(ppc_md.hpte_remove), |
b68a70c4 AB |
650 | BRANCH_SET_LINK); |
651 | patch_branch(ht64_call_hpte_updatepp, | |
26f92060 | 652 | ppc_function_entry(ppc_md.hpte_updatepp), |
b68a70c4 | 653 | BRANCH_SET_LINK); |
5b825831 | 654 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
7d0daae4 | 655 | |
b68a70c4 | 656 | patch_branch(htab_call_hpte_insert1, |
26f92060 | 657 | ppc_function_entry(ppc_md.hpte_insert), |
b68a70c4 AB |
658 | BRANCH_SET_LINK); |
659 | patch_branch(htab_call_hpte_insert2, | |
26f92060 | 660 | ppc_function_entry(ppc_md.hpte_insert), |
b68a70c4 AB |
661 | BRANCH_SET_LINK); |
662 | patch_branch(htab_call_hpte_remove, | |
26f92060 | 663 | ppc_function_entry(ppc_md.hpte_remove), |
b68a70c4 AB |
664 | BRANCH_SET_LINK); |
665 | patch_branch(htab_call_hpte_updatepp, | |
26f92060 | 666 | ppc_function_entry(ppc_md.hpte_updatepp), |
b68a70c4 | 667 | BRANCH_SET_LINK); |
7d0daae4 ME |
668 | } |
669 | ||
757c74d2 | 670 | static void __init htab_initialize(void) |
1da177e4 | 671 | { |
337a7128 | 672 | unsigned long table; |
1da177e4 | 673 | unsigned long pteg_count; |
9e88ba4e | 674 | unsigned long prot; |
41d824bf | 675 | unsigned long base = 0, size = 0, limit; |
28be7072 | 676 | struct memblock_region *reg; |
3c726f8d | 677 | |
1da177e4 LT |
678 | DBG(" -> htab_initialize()\n"); |
679 | ||
1189be65 PM |
680 | /* Initialize segment sizes */ |
681 | htab_init_seg_sizes(); | |
682 | ||
3c726f8d BH |
683 | /* Initialize page sizes */ |
684 | htab_init_page_sizes(); | |
685 | ||
44ae3ab3 | 686 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
687 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
688 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
689 | printk(KERN_INFO "Using 1TB segments\n"); | |
690 | } | |
691 | ||
1da177e4 LT |
692 | /* |
693 | * Calculate the required size of the htab. We want the number of | |
694 | * PTEGs to equal one half the number of real pages. | |
695 | */ | |
3c726f8d | 696 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
697 | pteg_count = htab_size_bytes >> 7; |
698 | ||
1da177e4 LT |
699 | htab_hash_mask = pteg_count - 1; |
700 | ||
57cfb814 | 701 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
702 | /* Using a hypervisor which owns the htab */ |
703 | htab_address = NULL; | |
704 | _SDR1 = 0; | |
3ccc00a7 MS |
705 | #ifdef CONFIG_FA_DUMP |
706 | /* | |
707 | * If firmware assisted dump is active firmware preserves | |
708 | * the contents of htab along with entire partition memory. | |
709 | * Clear the htab if firmware assisted dump is active so | |
710 | * that we dont end up using old mappings. | |
711 | */ | |
712 | if (is_fadump_active() && ppc_md.hpte_clear_all) | |
713 | ppc_md.hpte_clear_all(); | |
714 | #endif | |
1da177e4 LT |
715 | } else { |
716 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf | 717 | * the absolute address space. On cell we want it to be |
31bf1119 | 718 | * in the first 2 Gig so we can use it for IOMMU hacks. |
1da177e4 | 719 | */ |
41d824bf | 720 | if (machine_is(cell)) |
31bf1119 | 721 | limit = 0x80000000; |
41d824bf | 722 | else |
27f574c2 | 723 | limit = MEMBLOCK_ALLOC_ANYWHERE; |
41d824bf | 724 | |
95f72d1e | 725 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit); |
1da177e4 LT |
726 | |
727 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
728 | htab_size_bytes); | |
729 | ||
70267a7f | 730 | htab_address = __va(table); |
1da177e4 LT |
731 | |
732 | /* htab absolute addr + encoded htabsize */ | |
733 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
734 | ||
735 | /* Initialize the HPT with no entries */ | |
736 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 PM |
737 | |
738 | /* Set SDR1 */ | |
739 | mtspr(SPRN_SDR1, _SDR1); | |
1da177e4 LT |
740 | } |
741 | ||
f5ea64dc | 742 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 743 | |
370a908d | 744 | #ifdef CONFIG_DEBUG_PAGEALLOC |
95f72d1e YL |
745 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; |
746 | linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count, | |
cd3db0c4 | 747 | 1, ppc64_rma_size)); |
370a908d BH |
748 | memset(linear_map_hash_slots, 0, linear_map_hash_count); |
749 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
750 | ||
1da177e4 LT |
751 | /* On U3 based machines, we need to reserve the DART area and |
752 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
753 | * cacheable later on | |
754 | */ | |
1da177e4 LT |
755 | |
756 | /* create bolted the linear mapping in the hash table */ | |
28be7072 BH |
757 | for_each_memblock(memory, reg) { |
758 | base = (unsigned long)__va(reg->base); | |
759 | size = reg->size; | |
1da177e4 | 760 | |
5c339919 | 761 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 762 | base, size, prot); |
1da177e4 LT |
763 | |
764 | #ifdef CONFIG_U3_DART | |
765 | /* Do not map the DART space. Fortunately, it will be aligned | |
95f72d1e | 766 | * in such a way that it will not cross two memblock regions and |
3c726f8d BH |
767 | * will fit within a single 16Mb page. |
768 | * The DART space is assumed to be a full 16Mb region even if | |
769 | * we only use 2Mb of that space. We will use more of it later | |
770 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
771 | */ |
772 | DBG("DART base: %lx\n", dart_tablebase); | |
773 | ||
774 | if (dart_tablebase != 0 && dart_tablebase >= base | |
775 | && dart_tablebase < (base + size)) { | |
caf80e57 | 776 | unsigned long dart_table_end = dart_tablebase + 16 * MB; |
1da177e4 | 777 | if (base != dart_tablebase) |
3c726f8d | 778 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
9e88ba4e | 779 | __pa(base), prot, |
1189be65 PM |
780 | mmu_linear_psize, |
781 | mmu_kernel_ssize)); | |
caf80e57 | 782 | if ((base + size) > dart_table_end) |
3c726f8d | 783 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
caf80e57 ME |
784 | base + size, |
785 | __pa(dart_table_end), | |
9e88ba4e | 786 | prot, |
1189be65 PM |
787 | mmu_linear_psize, |
788 | mmu_kernel_ssize)); | |
1da177e4 LT |
789 | continue; |
790 | } | |
791 | #endif /* CONFIG_U3_DART */ | |
caf80e57 | 792 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 793 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
794 | } |
795 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
796 | |
797 | /* | |
798 | * If we have a memory_limit and we've allocated TCEs then we need to | |
799 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
800 | * case that the TCEs start below memory_limit. | |
801 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
802 | * for either 4K or 16MB pages. | |
803 | */ | |
804 | if (tce_alloc_start) { | |
b5666f70 ME |
805 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
806 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
807 | |
808 | if (base + size >= tce_alloc_start) | |
809 | tce_alloc_start = base + size + 1; | |
810 | ||
caf80e57 | 811 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 812 | __pa(tce_alloc_start), prot, |
1189be65 | 813 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
814 | } |
815 | ||
7d0daae4 ME |
816 | htab_finish_init(); |
817 | ||
1da177e4 LT |
818 | DBG(" <- htab_initialize()\n"); |
819 | } | |
820 | #undef KB | |
821 | #undef MB | |
1da177e4 | 822 | |
757c74d2 | 823 | void __init early_init_mmu(void) |
799d6046 | 824 | { |
757c74d2 | 825 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
826 | * of memory. Has to be done before SLB initialization as this is |
827 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
828 | */ |
829 | htab_initialize(); | |
830 | ||
376af594 | 831 | /* Initialize SLB management */ |
13b3d13b | 832 | slb_initialize(); |
757c74d2 BH |
833 | } |
834 | ||
835 | #ifdef CONFIG_SMP | |
061d19f2 | 836 | void early_init_mmu_secondary(void) |
757c74d2 BH |
837 | { |
838 | /* Initialize hash table for that CPU */ | |
57cfb814 | 839 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
799d6046 | 840 | mtspr(SPRN_SDR1, _SDR1); |
757c74d2 | 841 | |
376af594 | 842 | /* Initialize SLB */ |
13b3d13b | 843 | slb_initialize(); |
799d6046 | 844 | } |
757c74d2 | 845 | #endif /* CONFIG_SMP */ |
799d6046 | 846 | |
1da177e4 LT |
847 | /* |
848 | * Called by asm hashtable.S for doing lazy icache flush | |
849 | */ | |
850 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
851 | { | |
852 | struct page *page; | |
853 | ||
76c8e25b BH |
854 | if (!pfn_valid(pte_pfn(pte))) |
855 | return pp; | |
856 | ||
1da177e4 LT |
857 | page = pte_page(pte); |
858 | ||
859 | /* page is dirty */ | |
860 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
861 | if (trap == 0x400) { | |
0895ecda | 862 | flush_dcache_icache_page(page); |
1da177e4 LT |
863 | set_bit(PG_arch_1, &page->flags); |
864 | } else | |
3c726f8d | 865 | pp |= HPTE_R_N; |
1da177e4 LT |
866 | } |
867 | return pp; | |
868 | } | |
869 | ||
3a8247cc | 870 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 871 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 872 | { |
7aa0727f AK |
873 | u64 lpsizes; |
874 | unsigned char *hpsizes; | |
875 | unsigned long index, mask_index; | |
3a8247cc PM |
876 | |
877 | if (addr < SLICE_LOW_TOP) { | |
7aa0727f | 878 | lpsizes = get_paca()->context.low_slices_psize; |
3a8247cc | 879 | index = GET_LOW_SLICE_INDEX(addr); |
7aa0727f | 880 | return (lpsizes >> (index * 4)) & 0xF; |
3a8247cc | 881 | } |
7aa0727f AK |
882 | hpsizes = get_paca()->context.high_slices_psize; |
883 | index = GET_HIGH_SLICE_INDEX(addr); | |
884 | mask_index = index & 0x1; | |
885 | return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF; | |
3a8247cc PM |
886 | } |
887 | ||
888 | #else | |
889 | unsigned int get_paca_psize(unsigned long addr) | |
890 | { | |
891 | return get_paca()->context.user_psize; | |
892 | } | |
893 | #endif | |
894 | ||
721151d0 PM |
895 | /* |
896 | * Demote a segment to using 4k pages. | |
897 | * For now this makes the whole process use 4k pages. | |
898 | */ | |
721151d0 | 899 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 900 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 901 | { |
3a8247cc | 902 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 903 | return; |
3a8247cc | 904 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
1e57ba8d | 905 | #ifdef CONFIG_SPU_BASE |
721151d0 PM |
906 | spu_flush_all_slbs(mm); |
907 | #endif | |
3a8247cc | 908 | if (get_paca_psize(addr) != MMU_PAGE_4K) { |
fa28237c PM |
909 | get_paca()->context = mm->context; |
910 | slb_flush_and_rebolt(); | |
911 | } | |
721151d0 | 912 | } |
16f1c746 | 913 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 914 | |
fa28237c PM |
915 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
916 | /* | |
917 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
918 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
919 | * | |
920 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
921 | * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access. | |
922 | */ | |
d28513bc | 923 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 924 | { |
d28513bc | 925 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
926 | u32 spp = 0; |
927 | u32 **sbpm, *sbpp; | |
928 | ||
929 | if (ea >= spt->maxaddr) | |
930 | return 0; | |
b0d436c7 | 931 | if (ea < 0x100000000UL) { |
fa28237c PM |
932 | /* addresses below 4GB use spt->low_prot */ |
933 | sbpm = spt->low_prot; | |
934 | } else { | |
935 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
936 | if (!sbpm) | |
937 | return 0; | |
938 | } | |
939 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
940 | if (!sbpp) | |
941 | return 0; | |
942 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
943 | ||
944 | /* extract 2-bit bitfield for this 4k subpage */ | |
945 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
946 | ||
947 | /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */ | |
948 | spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0); | |
949 | return spp; | |
950 | } | |
951 | ||
952 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 953 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
954 | { |
955 | return 0; | |
956 | } | |
957 | #endif | |
958 | ||
4b8692c0 BH |
959 | void hash_failure_debug(unsigned long ea, unsigned long access, |
960 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 961 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
962 | { |
963 | if (!printk_ratelimit()) | |
964 | return; | |
965 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
966 | ea, access, current->comm); | |
d8139ebf AK |
967 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
968 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
969 | } |
970 | ||
09567e7f ME |
971 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
972 | int psize, bool user_region) | |
973 | { | |
974 | if (user_region) { | |
975 | if (psize != get_paca_psize(ea)) { | |
976 | get_paca()->context = mm->context; | |
977 | slb_flush_and_rebolt(); | |
978 | } | |
979 | } else if (get_paca()->vmalloc_sllp != | |
980 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
981 | get_paca()->vmalloc_sllp = | |
982 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
983 | slb_vmalloc_update(); | |
984 | } | |
985 | } | |
986 | ||
1da177e4 LT |
987 | /* Result code is: |
988 | * 0 - handled | |
989 | * 1 - normal page fault | |
990 | * -1 - critical hash insertion error | |
fa28237c | 991 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 LT |
992 | */ |
993 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap) | |
994 | { | |
ba12eede | 995 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 996 | pgd_t *pgdir; |
1da177e4 LT |
997 | unsigned long vsid; |
998 | struct mm_struct *mm; | |
999 | pte_t *ptep; | |
a4fe3ce7 | 1000 | unsigned hugeshift; |
56aa4129 | 1001 | const struct cpumask *tmp; |
3c726f8d | 1002 | int rc, user_region = 0, local = 0; |
1189be65 | 1003 | int psize, ssize; |
1da177e4 | 1004 | |
3c726f8d BH |
1005 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1006 | ea, access, trap); | |
1f8d419e | 1007 | |
3c726f8d | 1008 | /* Get region & vsid */ |
1da177e4 LT |
1009 | switch (REGION_ID(ea)) { |
1010 | case USER_REGION_ID: | |
1011 | user_region = 1; | |
1012 | mm = current->mm; | |
3c726f8d BH |
1013 | if (! mm) { |
1014 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1015 | rc = 1; |
1016 | goto bail; | |
3c726f8d | 1017 | } |
16c2d476 | 1018 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
1019 | ssize = user_segment_size(ea); |
1020 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 1021 | break; |
1da177e4 | 1022 | case VMALLOC_REGION_ID: |
1da177e4 | 1023 | mm = &init_mm; |
1189be65 | 1024 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1025 | if (ea < VMALLOC_END) |
1026 | psize = mmu_vmalloc_psize; | |
1027 | else | |
1028 | psize = mmu_io_psize; | |
1189be65 | 1029 | ssize = mmu_kernel_ssize; |
1da177e4 | 1030 | break; |
1da177e4 LT |
1031 | default: |
1032 | /* Not a valid range | |
1033 | * Send the problem up to do_page_fault | |
1034 | */ | |
ba12eede LZ |
1035 | rc = 1; |
1036 | goto bail; | |
1da177e4 | 1037 | } |
3c726f8d | 1038 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1039 | |
c60ac569 AK |
1040 | /* Bad address. */ |
1041 | if (!vsid) { | |
1042 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1043 | rc = 1; |
1044 | goto bail; | |
c60ac569 | 1045 | } |
3c726f8d | 1046 | /* Get pgdir */ |
1da177e4 | 1047 | pgdir = mm->pgd; |
ba12eede LZ |
1048 | if (pgdir == NULL) { |
1049 | rc = 1; | |
1050 | goto bail; | |
1051 | } | |
1da177e4 | 1052 | |
3c726f8d | 1053 | /* Check CPU locality */ |
56aa4129 RR |
1054 | tmp = cpumask_of(smp_processor_id()); |
1055 | if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) | |
1da177e4 LT |
1056 | local = 1; |
1057 | ||
16c2d476 | 1058 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1059 | /* If we use 4K pages and our psize is not 4K, then we might |
1060 | * be hitting a special driver mapping, and need to align the | |
1061 | * address before we fetch the PTE. | |
1062 | * | |
1063 | * It could also be a hugepage mapping, in which case this is | |
1064 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1065 | */ |
1066 | if (psize != MMU_PAGE_4K) | |
1067 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1068 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1069 | ||
3c726f8d | 1070 | /* Get PTE and page size from page tables */ |
a4fe3ce7 | 1071 | ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift); |
3c726f8d BH |
1072 | if (ptep == NULL || !pte_present(*ptep)) { |
1073 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1074 | rc = 1; |
1075 | goto bail; | |
3c726f8d BH |
1076 | } |
1077 | ||
ca91e6c0 BH |
1078 | /* Add _PAGE_PRESENT to the required access perm */ |
1079 | access |= _PAGE_PRESENT; | |
1080 | ||
1081 | /* Pre-check access permissions (will be re-checked atomically | |
1082 | * in __hash_page_XX but this pre-check is a fast path | |
1083 | */ | |
1084 | if (access & ~pte_val(*ptep)) { | |
1085 | DBG_LOW(" no access !\n"); | |
ba12eede LZ |
1086 | rc = 1; |
1087 | goto bail; | |
ca91e6c0 BH |
1088 | } |
1089 | ||
ba12eede | 1090 | if (hugeshift) { |
6d492ecc AK |
1091 | if (pmd_trans_huge(*(pmd_t *)ptep)) |
1092 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, | |
1093 | trap, local, ssize, psize); | |
1094 | #ifdef CONFIG_HUGETLB_PAGE | |
1095 | else | |
1096 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
1097 | local, ssize, hugeshift, psize); | |
1098 | #else | |
1099 | else { | |
1100 | /* | |
1101 | * if we have hugeshift, and is not transhuge with | |
1102 | * hugetlb disabled, something is really wrong. | |
1103 | */ | |
1104 | rc = 1; | |
1105 | WARN_ON(1); | |
1106 | } | |
1107 | #endif | |
09567e7f ME |
1108 | check_paca_psize(ea, mm, psize, user_region); |
1109 | ||
ba12eede LZ |
1110 | goto bail; |
1111 | } | |
a4fe3ce7 | 1112 | |
3c726f8d BH |
1113 | #ifndef CONFIG_PPC_64K_PAGES |
1114 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1115 | #else | |
1116 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1117 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1118 | #endif | |
3c726f8d | 1119 | /* Do actual hashing */ |
16c2d476 | 1120 | #ifdef CONFIG_PPC_64K_PAGES |
721151d0 | 1121 | /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ |
3a8247cc | 1122 | if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) { |
721151d0 PM |
1123 | demote_segment_4k(mm, ea); |
1124 | psize = MMU_PAGE_4K; | |
1125 | } | |
1126 | ||
16f1c746 BH |
1127 | /* If this PTE is non-cacheable and we have restrictions on |
1128 | * using non cacheable large pages, then we switch to 4k | |
1129 | */ | |
1130 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && | |
1131 | (pte_val(*ptep) & _PAGE_NO_CACHE)) { | |
1132 | if (user_region) { | |
1133 | demote_segment_4k(mm, ea); | |
1134 | psize = MMU_PAGE_4K; | |
1135 | } else if (ea < VMALLOC_END) { | |
1136 | /* | |
1137 | * some driver did a non-cacheable mapping | |
1138 | * in vmalloc space, so switch vmalloc | |
1139 | * to 4k pages | |
1140 | */ | |
1141 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1142 | "to 4kB pages because of " | |
1143 | "non-cacheable mapping\n"); | |
1144 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
1e57ba8d | 1145 | #ifdef CONFIG_SPU_BASE |
94b2a439 BH |
1146 | spu_flush_all_slbs(mm); |
1147 | #endif | |
bf72aeba | 1148 | } |
16f1c746 | 1149 | } |
09567e7f ME |
1150 | |
1151 | check_paca_psize(ea, mm, psize, user_region); | |
16c2d476 | 1152 | #endif /* CONFIG_PPC_64K_PAGES */ |
16f1c746 | 1153 | |
16c2d476 | 1154 | #ifdef CONFIG_PPC_HAS_HASH_64K |
bf72aeba | 1155 | if (psize == MMU_PAGE_64K) |
1189be65 | 1156 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
3c726f8d | 1157 | else |
16c2d476 | 1158 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
fa28237c | 1159 | { |
a1128f8f | 1160 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1161 | if (access & spp) |
1162 | rc = -2; | |
1163 | else | |
1164 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
1165 | local, ssize, spp); | |
1166 | } | |
3c726f8d | 1167 | |
4b8692c0 BH |
1168 | /* Dump some info in case of hash insertion failure, they should |
1169 | * never happen so it is really useful to know if/when they do | |
1170 | */ | |
1171 | if (rc == -1) | |
1172 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1173 | psize, pte_val(*ptep)); |
3c726f8d BH |
1174 | #ifndef CONFIG_PPC_64K_PAGES |
1175 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1176 | #else | |
1177 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1178 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1179 | #endif | |
1180 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1181 | |
1182 | bail: | |
1183 | exception_exit(prev_state); | |
3c726f8d | 1184 | return rc; |
1da177e4 | 1185 | } |
67207b96 | 1186 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1187 | |
3c726f8d BH |
1188 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1189 | unsigned long access, unsigned long trap) | |
1da177e4 | 1190 | { |
12bc9f6f | 1191 | int hugepage_shift; |
3c726f8d | 1192 | unsigned long vsid; |
0b97fee0 | 1193 | pgd_t *pgdir; |
3c726f8d | 1194 | pte_t *ptep; |
3c726f8d | 1195 | unsigned long flags; |
4b8692c0 | 1196 | int rc, ssize, local = 0; |
3c726f8d | 1197 | |
d0f13e3c BH |
1198 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1199 | ||
1200 | #ifdef CONFIG_PPC_MM_SLICES | |
1201 | /* We only prefault standard pages for now */ | |
2b02d139 | 1202 | if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize)) |
3c726f8d | 1203 | return; |
d0f13e3c | 1204 | #endif |
3c726f8d BH |
1205 | |
1206 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1207 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1208 | |
16f1c746 | 1209 | /* Get Linux PTE if available */ |
3c726f8d BH |
1210 | pgdir = mm->pgd; |
1211 | if (pgdir == NULL) | |
1212 | return; | |
0ac52dd7 AK |
1213 | |
1214 | /* Get VSID */ | |
1215 | ssize = user_segment_size(ea); | |
1216 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1217 | if (!vsid) | |
1218 | return; | |
1219 | /* | |
1220 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1221 | * saves us from holding multiple locks. | |
1222 | */ | |
1223 | local_irq_save(flags); | |
1224 | ||
12bc9f6f AK |
1225 | /* |
1226 | * THP pages use update_mmu_cache_pmd. We don't do | |
1227 | * hash preload there. Hence can ignore THP here | |
1228 | */ | |
1229 | ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugepage_shift); | |
3c726f8d | 1230 | if (!ptep) |
0ac52dd7 | 1231 | goto out_exit; |
16f1c746 | 1232 | |
12bc9f6f | 1233 | WARN_ON(hugepage_shift); |
16f1c746 BH |
1234 | #ifdef CONFIG_PPC_64K_PAGES |
1235 | /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on | |
1236 | * a 64K kernel), then we don't preload, hash_page() will take | |
1237 | * care of it once we actually try to access the page. | |
1238 | * That way we don't have to duplicate all of the logic for segment | |
1239 | * page size demotion here | |
1240 | */ | |
1241 | if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE)) | |
0ac52dd7 | 1242 | goto out_exit; |
16f1c746 BH |
1243 | #endif /* CONFIG_PPC_64K_PAGES */ |
1244 | ||
16c2d476 | 1245 | /* Is that local to this CPU ? */ |
56aa4129 | 1246 | if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) |
3c726f8d | 1247 | local = 1; |
16c2d476 BH |
1248 | |
1249 | /* Hash it in */ | |
1250 | #ifdef CONFIG_PPC_HAS_HASH_64K | |
bf72aeba | 1251 | if (mm->context.user_psize == MMU_PAGE_64K) |
4b8692c0 | 1252 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
1da177e4 | 1253 | else |
5b825831 | 1254 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
4b8692c0 | 1255 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize, |
1c2c25c7 | 1256 | subpage_protection(mm, ea)); |
4b8692c0 BH |
1257 | |
1258 | /* Dump some info in case of hash insertion failure, they should | |
1259 | * never happen so it is really useful to know if/when they do | |
1260 | */ | |
1261 | if (rc == -1) | |
1262 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1263 | mm->context.user_psize, |
1264 | mm->context.user_psize, | |
1265 | pte_val(*ptep)); | |
0ac52dd7 | 1266 | out_exit: |
3c726f8d BH |
1267 | local_irq_restore(flags); |
1268 | } | |
1269 | ||
f6ab0b92 BH |
1270 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1271 | * do not forget to update the assembly call site ! | |
1272 | */ | |
5524a27d | 1273 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
1189be65 | 1274 | int local) |
3c726f8d BH |
1275 | { |
1276 | unsigned long hash, index, shift, hidx, slot; | |
1277 | ||
5524a27d AK |
1278 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1279 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
1280 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
1281 | hidx = __rpte_to_hidx(pte, index); |
1282 | if (hidx & _PTEIDX_SECONDARY) | |
1283 | hash = ~hash; | |
1284 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1285 | slot += hidx & _PTEIDX_GROUP_IX; | |
5c339919 | 1286 | DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx); |
db3d8534 AK |
1287 | /* |
1288 | * We use same base page size and actual psize, because we don't | |
1289 | * use these functions for hugepage | |
1290 | */ | |
1291 | ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local); | |
3c726f8d | 1292 | } pte_iterate_hashed_end(); |
bc2a9408 MN |
1293 | |
1294 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1295 | /* Transactions are not aborted by tlbiel, only tlbie. | |
1296 | * Without, syncing a page back to a block device w/ PIO could pick up | |
1297 | * transactional data (bad!) so we force an abort here. Before the | |
1298 | * sync the page will be made read-only, which will flush_hash_page. | |
1299 | * BIG ISSUE here: if the kernel uses a page from userspace without | |
1300 | * unmapping it first, it may see the speculated version. | |
1301 | */ | |
1302 | if (local && cpu_has_feature(CPU_FTR_TM) && | |
c2fd22df | 1303 | current->thread.regs && |
bc2a9408 MN |
1304 | MSR_TM_ACTIVE(current->thread.regs->msr)) { |
1305 | tm_enable(); | |
1306 | tm_abort(TM_CAUSE_TLBI); | |
1307 | } | |
1308 | #endif | |
1da177e4 LT |
1309 | } |
1310 | ||
61b1a942 | 1311 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1312 | { |
3c726f8d | 1313 | if (ppc_md.flush_hash_range) |
61b1a942 | 1314 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 1315 | else { |
1da177e4 | 1316 | int i; |
61b1a942 BH |
1317 | struct ppc64_tlb_batch *batch = |
1318 | &__get_cpu_var(ppc64_tlb_batch); | |
1da177e4 LT |
1319 | |
1320 | for (i = 0; i < number; i++) | |
5524a27d | 1321 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1322 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1323 | } |
1324 | } | |
1325 | ||
1da177e4 LT |
1326 | /* |
1327 | * low_hash_fault is called when we the low level hash code failed | |
1328 | * to instert a PTE due to an hypervisor error | |
1329 | */ | |
fa28237c | 1330 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1331 | { |
ba12eede LZ |
1332 | enum ctx_state prev_state = exception_enter(); |
1333 | ||
1da177e4 | 1334 | if (user_mode(regs)) { |
fa28237c PM |
1335 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1336 | if (rc == -2) | |
1337 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1338 | else | |
1339 | #endif | |
1340 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1341 | } else | |
1342 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1343 | |
1344 | exception_exit(prev_state); | |
1da177e4 | 1345 | } |
370a908d | 1346 | |
b170bd3d LZ |
1347 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1348 | unsigned long pa, unsigned long rflags, | |
1349 | unsigned long vflags, int psize, int ssize) | |
1350 | { | |
1351 | unsigned long hpte_group; | |
1352 | long slot; | |
1353 | ||
1354 | repeat: | |
1355 | hpte_group = ((hash & htab_hash_mask) * | |
1356 | HPTES_PER_GROUP) & ~0x7UL; | |
1357 | ||
1358 | /* Insert into the hash table, primary slot */ | |
1359 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags, | |
b1022fbd | 1360 | psize, psize, ssize); |
b170bd3d LZ |
1361 | |
1362 | /* Primary is full, try the secondary */ | |
1363 | if (unlikely(slot == -1)) { | |
1364 | hpte_group = ((~hash & htab_hash_mask) * | |
1365 | HPTES_PER_GROUP) & ~0x7UL; | |
1366 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, | |
1367 | vflags | HPTE_V_SECONDARY, | |
b1022fbd | 1368 | psize, psize, ssize); |
b170bd3d LZ |
1369 | if (slot == -1) { |
1370 | if (mftb() & 0x1) | |
1371 | hpte_group = ((hash & htab_hash_mask) * | |
1372 | HPTES_PER_GROUP)&~0x7UL; | |
1373 | ||
1374 | ppc_md.hpte_remove(hpte_group); | |
1375 | goto repeat; | |
1376 | } | |
1377 | } | |
1378 | ||
1379 | return slot; | |
1380 | } | |
1381 | ||
370a908d BH |
1382 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1383 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1384 | { | |
016af59f | 1385 | unsigned long hash; |
1189be65 | 1386 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1387 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
bc033b63 | 1388 | unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL); |
016af59f | 1389 | long ret; |
370a908d | 1390 | |
5524a27d | 1391 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1392 | |
c60ac569 AK |
1393 | /* Don't create HPTE entries for bad address */ |
1394 | if (!vsid) | |
1395 | return; | |
016af59f LZ |
1396 | |
1397 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1398 | HPTE_V_BOLTED, | |
1399 | mmu_linear_psize, mmu_kernel_ssize); | |
1400 | ||
370a908d BH |
1401 | BUG_ON (ret < 0); |
1402 | spin_lock(&linear_map_hash_lock); | |
1403 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1404 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1405 | spin_unlock(&linear_map_hash_lock); | |
1406 | } | |
1407 | ||
1408 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1409 | { | |
1189be65 PM |
1410 | unsigned long hash, hidx, slot; |
1411 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1412 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1413 | |
5524a27d | 1414 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1415 | spin_lock(&linear_map_hash_lock); |
1416 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1417 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1418 | linear_map_hash_slots[lmi] = 0; | |
1419 | spin_unlock(&linear_map_hash_lock); | |
1420 | if (hidx & _PTEIDX_SECONDARY) | |
1421 | hash = ~hash; | |
1422 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1423 | slot += hidx & _PTEIDX_GROUP_IX; | |
db3d8534 AK |
1424 | ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize, |
1425 | mmu_kernel_ssize, 0); | |
370a908d BH |
1426 | } |
1427 | ||
1428 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
1429 | { | |
1430 | unsigned long flags, vaddr, lmi; | |
1431 | int i; | |
1432 | ||
1433 | local_irq_save(flags); | |
1434 | for (i = 0; i < numpages; i++, page++) { | |
1435 | vaddr = (unsigned long)page_address(page); | |
1436 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1437 | if (lmi >= linear_map_hash_count) | |
1438 | continue; | |
1439 | if (enable) | |
1440 | kernel_map_linear_page(vaddr, lmi); | |
1441 | else | |
1442 | kernel_unmap_linear_page(vaddr, lmi); | |
1443 | } | |
1444 | local_irq_restore(flags); | |
1445 | } | |
1446 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 BH |
1447 | |
1448 | void setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
1449 | phys_addr_t first_memblock_size) | |
1450 | { | |
1451 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1452 | * physical on those processors | |
1453 | */ | |
1454 | BUG_ON(first_memblock_base != 0); | |
1455 | ||
1456 | /* On LPAR systems, the first entry is our RMA region, | |
1457 | * non-LPAR 64-bit hash MMU systems don't have a limitation | |
1458 | * on real mode access, but using the first entry works well | |
1459 | * enough. We also clamp it to 1G to avoid some funky things | |
1460 | * such as RTAS bugs etc... | |
1461 | */ | |
1462 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
1463 | ||
1464 | /* Finally limit subsequent allocations */ | |
1465 | memblock_set_current_limit(ppc64_rma_size); | |
1466 | } |