Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
30 | #include <linux/ctype.h> | |
31 | #include <linux/cache.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/signal.h> | |
95f72d1e | 34 | #include <linux/memblock.h> |
1da177e4 | 35 | |
1da177e4 LT |
36 | #include <asm/processor.h> |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/mmu.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/page.h> | |
41 | #include <asm/types.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/uaccess.h> | |
44 | #include <asm/machdep.h> | |
d9b2b2a2 | 45 | #include <asm/prom.h> |
1da177e4 LT |
46 | #include <asm/abs_addr.h> |
47 | #include <asm/tlbflush.h> | |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
1da177e4 | 53 | #include <asm/sections.h> |
d0f13e3c | 54 | #include <asm/spu.h> |
aa39be09 | 55 | #include <asm/udbg.h> |
1da177e4 LT |
56 | |
57 | #ifdef DEBUG | |
58 | #define DBG(fmt...) udbg_printf(fmt) | |
59 | #else | |
60 | #define DBG(fmt...) | |
61 | #endif | |
62 | ||
3c726f8d BH |
63 | #ifdef DEBUG_LOW |
64 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
65 | #else | |
66 | #define DBG_LOW(fmt...) | |
67 | #endif | |
68 | ||
69 | #define KB (1024) | |
70 | #define MB (1024*KB) | |
658013e9 | 71 | #define GB (1024L*MB) |
3c726f8d | 72 | |
1da177e4 LT |
73 | /* |
74 | * Note: pte --> Linux PTE | |
75 | * HPTE --> PowerPC Hashed Page Table Entry | |
76 | * | |
77 | * Execution context: | |
78 | * htab_initialize is called with the MMU off (of course), but | |
79 | * the kernel has been copied down to zero so it can directly | |
80 | * reference global data. At this point it is very difficult | |
81 | * to print debug info. | |
82 | * | |
83 | */ | |
84 | ||
85 | #ifdef CONFIG_U3_DART | |
86 | extern unsigned long dart_tablebase; | |
87 | #endif /* CONFIG_U3_DART */ | |
88 | ||
799d6046 PM |
89 | static unsigned long _SDR1; |
90 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
91 | ||
8e561e7e | 92 | struct hash_pte *htab_address; |
337a7128 | 93 | unsigned long htab_size_bytes; |
96e28449 | 94 | unsigned long htab_hash_mask; |
4ab79aa8 | 95 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d BH |
96 | int mmu_linear_psize = MMU_PAGE_4K; |
97 | int mmu_virtual_psize = MMU_PAGE_4K; | |
bf72aeba | 98 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
99 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
100 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
101 | #endif | |
bf72aeba | 102 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 PM |
103 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
104 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; | |
584f8b71 | 105 | u16 mmu_slb_size = 64; |
4ab79aa8 | 106 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
3c726f8d | 107 | #ifdef CONFIG_HUGETLB_PAGE |
3c726f8d BH |
108 | unsigned int HPAGE_SHIFT; |
109 | #endif | |
bf72aeba PM |
110 | #ifdef CONFIG_PPC_64K_PAGES |
111 | int mmu_ci_restrictions; | |
112 | #endif | |
370a908d BH |
113 | #ifdef CONFIG_DEBUG_PAGEALLOC |
114 | static u8 *linear_map_hash_slots; | |
115 | static unsigned long linear_map_hash_count; | |
ed166692 | 116 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 117 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 118 | |
3c726f8d BH |
119 | /* There are definitions of page sizes arrays to be used when none |
120 | * is provided by the firmware. | |
121 | */ | |
1da177e4 | 122 | |
3c726f8d BH |
123 | /* Pre-POWER4 CPUs (4k pages only) |
124 | */ | |
09de9ff8 | 125 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
126 | [MMU_PAGE_4K] = { |
127 | .shift = 12, | |
128 | .sllp = 0, | |
129 | .penc = 0, | |
130 | .avpnm = 0, | |
131 | .tlbiel = 0, | |
132 | }, | |
133 | }; | |
134 | ||
135 | /* POWER4, GPUL, POWER5 | |
136 | * | |
137 | * Support for 16Mb large pages | |
138 | */ | |
09de9ff8 | 139 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
140 | [MMU_PAGE_4K] = { |
141 | .shift = 12, | |
142 | .sllp = 0, | |
143 | .penc = 0, | |
144 | .avpnm = 0, | |
145 | .tlbiel = 1, | |
146 | }, | |
147 | [MMU_PAGE_16M] = { | |
148 | .shift = 24, | |
149 | .sllp = SLB_VSID_L, | |
150 | .penc = 0, | |
151 | .avpnm = 0x1UL, | |
152 | .tlbiel = 0, | |
153 | }, | |
154 | }; | |
155 | ||
bc033b63 BH |
156 | static unsigned long htab_convert_pte_flags(unsigned long pteflags) |
157 | { | |
158 | unsigned long rflags = pteflags & 0x1fa; | |
159 | ||
160 | /* _PAGE_EXEC -> NOEXEC */ | |
161 | if ((pteflags & _PAGE_EXEC) == 0) | |
162 | rflags |= HPTE_R_N; | |
163 | ||
164 | /* PP bits. PAGE_USER is already PP bit 0x2, so we only | |
165 | * need to add in 0x1 if it's a read-only user page | |
166 | */ | |
167 | if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) && | |
168 | (pteflags & _PAGE_DIRTY))) | |
169 | rflags |= 1; | |
170 | ||
171 | /* Always add C */ | |
172 | return rflags | HPTE_R_C; | |
173 | } | |
3c726f8d BH |
174 | |
175 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 176 | unsigned long pstart, unsigned long prot, |
1189be65 | 177 | int psize, int ssize) |
1da177e4 | 178 | { |
3c726f8d BH |
179 | unsigned long vaddr, paddr; |
180 | unsigned int step, shift; | |
3c726f8d | 181 | int ret = 0; |
1da177e4 | 182 | |
3c726f8d BH |
183 | shift = mmu_psize_defs[psize].shift; |
184 | step = 1 << shift; | |
1da177e4 | 185 | |
bc033b63 BH |
186 | prot = htab_convert_pte_flags(prot); |
187 | ||
188 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
189 | vstart, vend, pstart, prot, psize, ssize); | |
190 | ||
3c726f8d BH |
191 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
192 | vaddr += step, paddr += step) { | |
370a908d | 193 | unsigned long hash, hpteg; |
1189be65 PM |
194 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
195 | unsigned long va = hpt_va(vaddr, vsid, ssize); | |
9e88ba4e PM |
196 | unsigned long tprot = prot; |
197 | ||
198 | /* Make kernel text executable */ | |
549e8152 | 199 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 200 | tprot &= ~HPTE_R_N; |
1da177e4 | 201 | |
1189be65 | 202 | hash = hpt_hash(va, shift, ssize); |
1da177e4 LT |
203 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
204 | ||
c30a4df3 | 205 | BUG_ON(!ppc_md.hpte_insert); |
9e88ba4e | 206 | ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot, |
bc033b63 | 207 | HPTE_V_BOLTED, psize, ssize); |
c30a4df3 | 208 | |
3c726f8d BH |
209 | if (ret < 0) |
210 | break; | |
370a908d BH |
211 | #ifdef CONFIG_DEBUG_PAGEALLOC |
212 | if ((paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
213 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; | |
214 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
215 | } |
216 | return ret < 0 ? ret : 0; | |
217 | } | |
1da177e4 | 218 | |
ae86f008 | 219 | #ifdef CONFIG_MEMORY_HOTPLUG |
52db9b44 | 220 | static int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
221 | int psize, int ssize) |
222 | { | |
223 | unsigned long vaddr; | |
224 | unsigned int step, shift; | |
225 | ||
226 | shift = mmu_psize_defs[psize].shift; | |
227 | step = 1 << shift; | |
228 | ||
229 | if (!ppc_md.hpte_removebolted) { | |
52db9b44 BP |
230 | printk(KERN_WARNING "Platform doesn't implement " |
231 | "hpte_removebolted\n"); | |
232 | return -EINVAL; | |
f8c8803b BP |
233 | } |
234 | ||
235 | for (vaddr = vstart; vaddr < vend; vaddr += step) | |
236 | ppc_md.hpte_removebolted(vaddr, psize, ssize); | |
52db9b44 BP |
237 | |
238 | return 0; | |
f8c8803b | 239 | } |
ae86f008 | 240 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
f8c8803b | 241 | |
1189be65 PM |
242 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
243 | const char *uname, int depth, | |
244 | void *data) | |
245 | { | |
246 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
247 | u32 *prop; | |
248 | unsigned long size = 0; | |
249 | ||
250 | /* We are scanning "cpu" nodes only */ | |
251 | if (type == NULL || strcmp(type, "cpu") != 0) | |
252 | return 0; | |
253 | ||
254 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", | |
255 | &size); | |
256 | if (prop == NULL) | |
257 | return 0; | |
258 | for (; size >= 4; size -= 4, ++prop) { | |
259 | if (prop[0] == 40) { | |
260 | DBG("1T segment support detected\n"); | |
261 | cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT; | |
f5534004 | 262 | return 1; |
1189be65 | 263 | } |
1189be65 | 264 | } |
f66bce5e | 265 | cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B; |
1189be65 PM |
266 | return 0; |
267 | } | |
268 | ||
269 | static void __init htab_init_seg_sizes(void) | |
270 | { | |
271 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
272 | } | |
273 | ||
3c726f8d BH |
274 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
275 | const char *uname, int depth, | |
276 | void *data) | |
277 | { | |
278 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
279 | u32 *prop; | |
280 | unsigned long size = 0; | |
281 | ||
282 | /* We are scanning "cpu" nodes only */ | |
283 | if (type == NULL || strcmp(type, "cpu") != 0) | |
284 | return 0; | |
285 | ||
286 | prop = (u32 *)of_get_flat_dt_prop(node, | |
287 | "ibm,segment-page-sizes", &size); | |
288 | if (prop != NULL) { | |
289 | DBG("Page sizes from device-tree:\n"); | |
290 | size /= 4; | |
291 | cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE); | |
292 | while(size > 0) { | |
293 | unsigned int shift = prop[0]; | |
294 | unsigned int slbenc = prop[1]; | |
295 | unsigned int lpnum = prop[2]; | |
296 | unsigned int lpenc = 0; | |
297 | struct mmu_psize_def *def; | |
298 | int idx = -1; | |
299 | ||
300 | size -= 3; prop += 3; | |
301 | while(size > 0 && lpnum) { | |
302 | if (prop[0] == shift) | |
303 | lpenc = prop[1]; | |
304 | prop += 2; size -= 2; | |
305 | lpnum--; | |
306 | } | |
307 | switch(shift) { | |
308 | case 0xc: | |
309 | idx = MMU_PAGE_4K; | |
310 | break; | |
311 | case 0x10: | |
312 | idx = MMU_PAGE_64K; | |
313 | break; | |
314 | case 0x14: | |
315 | idx = MMU_PAGE_1M; | |
316 | break; | |
317 | case 0x18: | |
318 | idx = MMU_PAGE_16M; | |
319 | cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE; | |
320 | break; | |
321 | case 0x22: | |
322 | idx = MMU_PAGE_16G; | |
323 | break; | |
324 | } | |
325 | if (idx < 0) | |
326 | continue; | |
327 | def = &mmu_psize_defs[idx]; | |
328 | def->shift = shift; | |
329 | if (shift <= 23) | |
330 | def->avpnm = 0; | |
331 | else | |
332 | def->avpnm = (1 << (shift - 23)) - 1; | |
333 | def->sllp = slbenc; | |
334 | def->penc = lpenc; | |
335 | /* We don't know for sure what's up with tlbiel, so | |
336 | * for now we only set it for 4K and 64K pages | |
337 | */ | |
338 | if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K) | |
339 | def->tlbiel = 1; | |
340 | else | |
341 | def->tlbiel = 0; | |
342 | ||
5c339919 | 343 | DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, " |
3c726f8d BH |
344 | "tlbiel=%d, penc=%d\n", |
345 | idx, shift, def->sllp, def->avpnm, def->tlbiel, | |
346 | def->penc); | |
1da177e4 | 347 | } |
3c726f8d BH |
348 | return 1; |
349 | } | |
350 | return 0; | |
351 | } | |
352 | ||
e16a9c09 | 353 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
354 | /* Scan for 16G memory blocks that have been set aside for huge pages |
355 | * and reserve those blocks for 16G huge pages. | |
356 | */ | |
357 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
358 | const char *uname, int depth, | |
359 | void *data) { | |
360 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
361 | unsigned long *addr_prop; | |
362 | u32 *page_count_prop; | |
363 | unsigned int expected_pages; | |
364 | long unsigned int phys_addr; | |
365 | long unsigned int block_size; | |
366 | ||
367 | /* We are scanning "memory" nodes only */ | |
368 | if (type == NULL || strcmp(type, "memory") != 0) | |
369 | return 0; | |
370 | ||
371 | /* This property is the log base 2 of the number of virtual pages that | |
372 | * will represent this memory block. */ | |
373 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
374 | if (page_count_prop == NULL) | |
375 | return 0; | |
376 | expected_pages = (1 << page_count_prop[0]); | |
377 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); | |
378 | if (addr_prop == NULL) | |
379 | return 0; | |
380 | phys_addr = addr_prop[0]; | |
381 | block_size = addr_prop[1]; | |
382 | if (block_size != (16 * GB)) | |
383 | return 0; | |
384 | printk(KERN_INFO "Huge page(16GB) memory: " | |
385 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
386 | phys_addr, block_size, expected_pages); | |
95f72d1e YL |
387 | if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) { |
388 | memblock_reserve(phys_addr, block_size * expected_pages); | |
4792adba JT |
389 | add_gpage(phys_addr, block_size, expected_pages); |
390 | } | |
658013e9 JT |
391 | return 0; |
392 | } | |
e16a9c09 | 393 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 394 | |
3c726f8d BH |
395 | static void __init htab_init_page_sizes(void) |
396 | { | |
397 | int rc; | |
398 | ||
399 | /* Default to 4K pages only */ | |
400 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
401 | sizeof(mmu_psize_defaults_old)); | |
402 | ||
403 | /* | |
404 | * Try to find the available page sizes in the device-tree | |
405 | */ | |
406 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
407 | if (rc != 0) /* Found */ | |
408 | goto found; | |
409 | ||
410 | /* | |
411 | * Not in the device-tree, let's fallback on known size | |
412 | * list for 16M capable GP & GR | |
413 | */ | |
0470466d | 414 | if (cpu_has_feature(CPU_FTR_16M_PAGE)) |
3c726f8d BH |
415 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
416 | sizeof(mmu_psize_defaults_gp)); | |
417 | found: | |
370a908d | 418 | #ifndef CONFIG_DEBUG_PAGEALLOC |
3c726f8d BH |
419 | /* |
420 | * Pick a size for the linear mapping. Currently, we only support | |
421 | * 16M, 1M and 4K which is the default | |
422 | */ | |
423 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
424 | mmu_linear_psize = MMU_PAGE_16M; | |
425 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
426 | mmu_linear_psize = MMU_PAGE_1M; | |
370a908d | 427 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
3c726f8d | 428 | |
bf72aeba | 429 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
430 | /* |
431 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
432 | * 64K for user mappings and vmalloc if supported by the processor. |
433 | * We only use 64k for ioremap if the processor | |
434 | * (and firmware) support cache-inhibited large pages. | |
435 | * If not, we use 4k and set mmu_ci_restrictions so that | |
436 | * hash_page knows to switch processes that use cache-inhibited | |
437 | * mappings to 4k pages. | |
3c726f8d | 438 | */ |
bf72aeba | 439 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 440 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 441 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
442 | if (mmu_linear_psize == MMU_PAGE_4K) |
443 | mmu_linear_psize = MMU_PAGE_64K; | |
cfe666b1 PM |
444 | if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) { |
445 | /* | |
446 | * Don't use 64k pages for ioremap on pSeries, since | |
447 | * that would stop us accessing the HEA ethernet. | |
448 | */ | |
449 | if (!machine_is(pseries)) | |
450 | mmu_io_psize = MMU_PAGE_64K; | |
451 | } else | |
bf72aeba PM |
452 | mmu_ci_restrictions = 1; |
453 | } | |
370a908d | 454 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 455 | |
cec08e7a BH |
456 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
457 | /* We try to use 16M pages for vmemmap if that is supported | |
458 | * and we have at least 1G of RAM at boot | |
459 | */ | |
460 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 461 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
462 | mmu_vmemmap_psize = MMU_PAGE_16M; |
463 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
464 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
465 | else | |
466 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
467 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
468 | ||
bf72aeba | 469 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
470 | "virtual = %d, io = %d" |
471 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
472 | ", vmemmap = %d" | |
473 | #endif | |
474 | "\n", | |
3c726f8d | 475 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 476 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
477 | mmu_psize_defs[mmu_io_psize].shift |
478 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
479 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
480 | #endif | |
481 | ); | |
3c726f8d BH |
482 | |
483 | #ifdef CONFIG_HUGETLB_PAGE | |
658013e9 JT |
484 | /* Reserve 16G huge page memory sections for huge pages */ |
485 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
3c726f8d BH |
486 | #endif /* CONFIG_HUGETLB_PAGE */ |
487 | } | |
488 | ||
489 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
490 | const char *uname, int depth, | |
491 | void *data) | |
492 | { | |
493 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
494 | u32 *prop; | |
495 | ||
496 | /* We are scanning "cpu" nodes only */ | |
497 | if (type == NULL || strcmp(type, "cpu") != 0) | |
498 | return 0; | |
499 | ||
500 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL); | |
501 | if (prop != NULL) { | |
502 | /* pft_size[0] is the NUMA CEC cookie */ | |
503 | ppc64_pft_size = prop[1]; | |
504 | return 1; | |
1da177e4 | 505 | } |
3c726f8d | 506 | return 0; |
1da177e4 LT |
507 | } |
508 | ||
3c726f8d | 509 | static unsigned long __init htab_get_table_size(void) |
3eac8c69 | 510 | { |
13870b65 | 511 | unsigned long mem_size, rnd_mem_size, pteg_count, psize; |
3eac8c69 | 512 | |
3c726f8d | 513 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 514 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 515 | * calculate it now based on the total RAM size |
3eac8c69 | 516 | */ |
3c726f8d BH |
517 | if (ppc64_pft_size == 0) |
518 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
519 | if (ppc64_pft_size) |
520 | return 1UL << ppc64_pft_size; | |
521 | ||
522 | /* round mem_size up to next power of 2 */ | |
95f72d1e | 523 | mem_size = memblock_phys_mem_size(); |
799d6046 PM |
524 | rnd_mem_size = 1UL << __ilog2(mem_size); |
525 | if (rnd_mem_size < mem_size) | |
3eac8c69 PM |
526 | rnd_mem_size <<= 1; |
527 | ||
528 | /* # pages / 2 */ | |
13870b65 AB |
529 | psize = mmu_psize_defs[mmu_virtual_psize].shift; |
530 | pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11); | |
3eac8c69 PM |
531 | |
532 | return pteg_count << 7; | |
533 | } | |
534 | ||
54b79248 MK |
535 | #ifdef CONFIG_MEMORY_HOTPLUG |
536 | void create_section_mapping(unsigned long start, unsigned long end) | |
537 | { | |
bc033b63 | 538 | BUG_ON(htab_bolt_mapping(start, end, __pa(start), |
f5ea64dc | 539 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, |
bc033b63 | 540 | mmu_kernel_ssize)); |
54b79248 | 541 | } |
f8c8803b | 542 | |
52db9b44 | 543 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 544 | { |
52db9b44 BP |
545 | return htab_remove_mapping(start, end, mmu_linear_psize, |
546 | mmu_kernel_ssize); | |
f8c8803b | 547 | } |
54b79248 MK |
548 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
549 | ||
7d0daae4 ME |
550 | static inline void make_bl(unsigned int *insn_addr, void *func) |
551 | { | |
552 | unsigned long funcp = *((unsigned long *)func); | |
553 | int offset = funcp - (unsigned long)insn_addr; | |
554 | ||
555 | *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc)); | |
556 | flush_icache_range((unsigned long)insn_addr, 4+ | |
557 | (unsigned long)insn_addr); | |
558 | } | |
559 | ||
560 | static void __init htab_finish_init(void) | |
561 | { | |
562 | extern unsigned int *htab_call_hpte_insert1; | |
563 | extern unsigned int *htab_call_hpte_insert2; | |
564 | extern unsigned int *htab_call_hpte_remove; | |
565 | extern unsigned int *htab_call_hpte_updatepp; | |
566 | ||
16c2d476 | 567 | #ifdef CONFIG_PPC_HAS_HASH_64K |
7d0daae4 ME |
568 | extern unsigned int *ht64_call_hpte_insert1; |
569 | extern unsigned int *ht64_call_hpte_insert2; | |
570 | extern unsigned int *ht64_call_hpte_remove; | |
571 | extern unsigned int *ht64_call_hpte_updatepp; | |
572 | ||
573 | make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert); | |
574 | make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert); | |
575 | make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove); | |
576 | make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
5b825831 | 577 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
7d0daae4 ME |
578 | |
579 | make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert); | |
580 | make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert); | |
581 | make_bl(htab_call_hpte_remove, ppc_md.hpte_remove); | |
582 | make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
583 | } | |
584 | ||
757c74d2 | 585 | static void __init htab_initialize(void) |
1da177e4 | 586 | { |
337a7128 | 587 | unsigned long table; |
1da177e4 | 588 | unsigned long pteg_count; |
9e88ba4e | 589 | unsigned long prot; |
41d824bf | 590 | unsigned long base = 0, size = 0, limit; |
28be7072 | 591 | struct memblock_region *reg; |
3c726f8d | 592 | |
1da177e4 LT |
593 | DBG(" -> htab_initialize()\n"); |
594 | ||
1189be65 PM |
595 | /* Initialize segment sizes */ |
596 | htab_init_seg_sizes(); | |
597 | ||
3c726f8d BH |
598 | /* Initialize page sizes */ |
599 | htab_init_page_sizes(); | |
600 | ||
1189be65 PM |
601 | if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) { |
602 | mmu_kernel_ssize = MMU_SEGSIZE_1T; | |
603 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
604 | printk(KERN_INFO "Using 1TB segments\n"); | |
605 | } | |
606 | ||
1da177e4 LT |
607 | /* |
608 | * Calculate the required size of the htab. We want the number of | |
609 | * PTEGs to equal one half the number of real pages. | |
610 | */ | |
3c726f8d | 611 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
612 | pteg_count = htab_size_bytes >> 7; |
613 | ||
1da177e4 LT |
614 | htab_hash_mask = pteg_count - 1; |
615 | ||
57cfb814 | 616 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
617 | /* Using a hypervisor which owns the htab */ |
618 | htab_address = NULL; | |
619 | _SDR1 = 0; | |
620 | } else { | |
621 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf | 622 | * the absolute address space. On cell we want it to be |
31bf1119 | 623 | * in the first 2 Gig so we can use it for IOMMU hacks. |
1da177e4 | 624 | */ |
41d824bf | 625 | if (machine_is(cell)) |
31bf1119 | 626 | limit = 0x80000000; |
41d824bf | 627 | else |
27f574c2 | 628 | limit = MEMBLOCK_ALLOC_ANYWHERE; |
41d824bf | 629 | |
95f72d1e | 630 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit); |
1da177e4 LT |
631 | |
632 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
633 | htab_size_bytes); | |
634 | ||
1da177e4 LT |
635 | htab_address = abs_to_virt(table); |
636 | ||
637 | /* htab absolute addr + encoded htabsize */ | |
638 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
639 | ||
640 | /* Initialize the HPT with no entries */ | |
641 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 PM |
642 | |
643 | /* Set SDR1 */ | |
644 | mtspr(SPRN_SDR1, _SDR1); | |
1da177e4 LT |
645 | } |
646 | ||
f5ea64dc | 647 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 648 | |
370a908d | 649 | #ifdef CONFIG_DEBUG_PAGEALLOC |
95f72d1e YL |
650 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; |
651 | linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count, | |
cd3db0c4 | 652 | 1, ppc64_rma_size)); |
370a908d BH |
653 | memset(linear_map_hash_slots, 0, linear_map_hash_count); |
654 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
655 | ||
1da177e4 LT |
656 | /* On U3 based machines, we need to reserve the DART area and |
657 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
658 | * cacheable later on | |
659 | */ | |
1da177e4 LT |
660 | |
661 | /* create bolted the linear mapping in the hash table */ | |
28be7072 BH |
662 | for_each_memblock(memory, reg) { |
663 | base = (unsigned long)__va(reg->base); | |
664 | size = reg->size; | |
1da177e4 | 665 | |
5c339919 | 666 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 667 | base, size, prot); |
1da177e4 LT |
668 | |
669 | #ifdef CONFIG_U3_DART | |
670 | /* Do not map the DART space. Fortunately, it will be aligned | |
95f72d1e | 671 | * in such a way that it will not cross two memblock regions and |
3c726f8d BH |
672 | * will fit within a single 16Mb page. |
673 | * The DART space is assumed to be a full 16Mb region even if | |
674 | * we only use 2Mb of that space. We will use more of it later | |
675 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
676 | */ |
677 | DBG("DART base: %lx\n", dart_tablebase); | |
678 | ||
679 | if (dart_tablebase != 0 && dart_tablebase >= base | |
680 | && dart_tablebase < (base + size)) { | |
caf80e57 | 681 | unsigned long dart_table_end = dart_tablebase + 16 * MB; |
1da177e4 | 682 | if (base != dart_tablebase) |
3c726f8d | 683 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
9e88ba4e | 684 | __pa(base), prot, |
1189be65 PM |
685 | mmu_linear_psize, |
686 | mmu_kernel_ssize)); | |
caf80e57 | 687 | if ((base + size) > dart_table_end) |
3c726f8d | 688 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
caf80e57 ME |
689 | base + size, |
690 | __pa(dart_table_end), | |
9e88ba4e | 691 | prot, |
1189be65 PM |
692 | mmu_linear_psize, |
693 | mmu_kernel_ssize)); | |
1da177e4 LT |
694 | continue; |
695 | } | |
696 | #endif /* CONFIG_U3_DART */ | |
caf80e57 | 697 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 698 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
699 | } |
700 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
701 | |
702 | /* | |
703 | * If we have a memory_limit and we've allocated TCEs then we need to | |
704 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
705 | * case that the TCEs start below memory_limit. | |
706 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
707 | * for either 4K or 16MB pages. | |
708 | */ | |
709 | if (tce_alloc_start) { | |
b5666f70 ME |
710 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
711 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
712 | |
713 | if (base + size >= tce_alloc_start) | |
714 | tce_alloc_start = base + size + 1; | |
715 | ||
caf80e57 | 716 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 717 | __pa(tce_alloc_start), prot, |
1189be65 | 718 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
719 | } |
720 | ||
7d0daae4 ME |
721 | htab_finish_init(); |
722 | ||
1da177e4 LT |
723 | DBG(" <- htab_initialize()\n"); |
724 | } | |
725 | #undef KB | |
726 | #undef MB | |
1da177e4 | 727 | |
757c74d2 | 728 | void __init early_init_mmu(void) |
799d6046 | 729 | { |
757c74d2 BH |
730 | /* Setup initial STAB address in the PACA */ |
731 | get_paca()->stab_real = __pa((u64)&initial_stab); | |
732 | get_paca()->stab_addr = (u64)&initial_stab; | |
733 | ||
734 | /* Initialize the MMU Hash table and create the linear mapping | |
735 | * of memory. Has to be done before stab/slb initialization as | |
736 | * this is currently where the page size encoding is obtained | |
737 | */ | |
738 | htab_initialize(); | |
739 | ||
740 | /* Initialize stab / SLB management except on iSeries | |
741 | */ | |
742 | if (cpu_has_feature(CPU_FTR_SLB)) | |
743 | slb_initialize(); | |
744 | else if (!firmware_has_feature(FW_FEATURE_ISERIES)) | |
745 | stab_initialize(get_paca()->stab_real); | |
746 | } | |
747 | ||
748 | #ifdef CONFIG_SMP | |
24f1ce80 | 749 | void __cpuinit early_init_mmu_secondary(void) |
757c74d2 BH |
750 | { |
751 | /* Initialize hash table for that CPU */ | |
57cfb814 | 752 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
799d6046 | 753 | mtspr(SPRN_SDR1, _SDR1); |
757c74d2 BH |
754 | |
755 | /* Initialize STAB/SLB. We use a virtual address as it works | |
756 | * in real mode on pSeries and we want a virutal address on | |
757 | * iSeries anyway | |
758 | */ | |
759 | if (cpu_has_feature(CPU_FTR_SLB)) | |
760 | slb_initialize(); | |
761 | else | |
762 | stab_initialize(get_paca()->stab_addr); | |
799d6046 | 763 | } |
757c74d2 | 764 | #endif /* CONFIG_SMP */ |
799d6046 | 765 | |
1da177e4 LT |
766 | /* |
767 | * Called by asm hashtable.S for doing lazy icache flush | |
768 | */ | |
769 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
770 | { | |
771 | struct page *page; | |
772 | ||
76c8e25b BH |
773 | if (!pfn_valid(pte_pfn(pte))) |
774 | return pp; | |
775 | ||
1da177e4 LT |
776 | page = pte_page(pte); |
777 | ||
778 | /* page is dirty */ | |
779 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
780 | if (trap == 0x400) { | |
0895ecda | 781 | flush_dcache_icache_page(page); |
1da177e4 LT |
782 | set_bit(PG_arch_1, &page->flags); |
783 | } else | |
3c726f8d | 784 | pp |= HPTE_R_N; |
1da177e4 LT |
785 | } |
786 | return pp; | |
787 | } | |
788 | ||
3a8247cc PM |
789 | #ifdef CONFIG_PPC_MM_SLICES |
790 | unsigned int get_paca_psize(unsigned long addr) | |
791 | { | |
792 | unsigned long index, slices; | |
793 | ||
794 | if (addr < SLICE_LOW_TOP) { | |
795 | slices = get_paca()->context.low_slices_psize; | |
796 | index = GET_LOW_SLICE_INDEX(addr); | |
797 | } else { | |
798 | slices = get_paca()->context.high_slices_psize; | |
799 | index = GET_HIGH_SLICE_INDEX(addr); | |
800 | } | |
801 | return (slices >> (index * 4)) & 0xF; | |
802 | } | |
803 | ||
804 | #else | |
805 | unsigned int get_paca_psize(unsigned long addr) | |
806 | { | |
807 | return get_paca()->context.user_psize; | |
808 | } | |
809 | #endif | |
810 | ||
721151d0 PM |
811 | /* |
812 | * Demote a segment to using 4k pages. | |
813 | * For now this makes the whole process use 4k pages. | |
814 | */ | |
721151d0 | 815 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 816 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 817 | { |
3a8247cc | 818 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 819 | return; |
3a8247cc | 820 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
1e57ba8d | 821 | #ifdef CONFIG_SPU_BASE |
721151d0 PM |
822 | spu_flush_all_slbs(mm); |
823 | #endif | |
3a8247cc | 824 | if (get_paca_psize(addr) != MMU_PAGE_4K) { |
fa28237c PM |
825 | get_paca()->context = mm->context; |
826 | slb_flush_and_rebolt(); | |
827 | } | |
721151d0 | 828 | } |
16f1c746 | 829 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 830 | |
fa28237c PM |
831 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
832 | /* | |
833 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
834 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
835 | * | |
836 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
837 | * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access. | |
838 | */ | |
d28513bc | 839 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 840 | { |
d28513bc | 841 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
842 | u32 spp = 0; |
843 | u32 **sbpm, *sbpp; | |
844 | ||
845 | if (ea >= spt->maxaddr) | |
846 | return 0; | |
847 | if (ea < 0x100000000) { | |
848 | /* addresses below 4GB use spt->low_prot */ | |
849 | sbpm = spt->low_prot; | |
850 | } else { | |
851 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
852 | if (!sbpm) | |
853 | return 0; | |
854 | } | |
855 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
856 | if (!sbpp) | |
857 | return 0; | |
858 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
859 | ||
860 | /* extract 2-bit bitfield for this 4k subpage */ | |
861 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
862 | ||
863 | /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */ | |
864 | spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0); | |
865 | return spp; | |
866 | } | |
867 | ||
868 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 869 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
870 | { |
871 | return 0; | |
872 | } | |
873 | #endif | |
874 | ||
4b8692c0 BH |
875 | void hash_failure_debug(unsigned long ea, unsigned long access, |
876 | unsigned long vsid, unsigned long trap, | |
877 | int ssize, int psize, unsigned long pte) | |
878 | { | |
879 | if (!printk_ratelimit()) | |
880 | return; | |
881 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
882 | ea, access, current->comm); | |
883 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n", | |
884 | trap, vsid, ssize, psize, pte); | |
885 | } | |
886 | ||
1da177e4 LT |
887 | /* Result code is: |
888 | * 0 - handled | |
889 | * 1 - normal page fault | |
890 | * -1 - critical hash insertion error | |
fa28237c | 891 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 LT |
892 | */ |
893 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap) | |
894 | { | |
a1128f8f | 895 | pgd_t *pgdir; |
1da177e4 LT |
896 | unsigned long vsid; |
897 | struct mm_struct *mm; | |
898 | pte_t *ptep; | |
a4fe3ce7 | 899 | unsigned hugeshift; |
56aa4129 | 900 | const struct cpumask *tmp; |
3c726f8d | 901 | int rc, user_region = 0, local = 0; |
1189be65 | 902 | int psize, ssize; |
1da177e4 | 903 | |
3c726f8d BH |
904 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
905 | ea, access, trap); | |
1f8d419e | 906 | |
3c726f8d BH |
907 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) { |
908 | DBG_LOW(" out of pgtable range !\n"); | |
909 | return 1; | |
910 | } | |
911 | ||
912 | /* Get region & vsid */ | |
1da177e4 LT |
913 | switch (REGION_ID(ea)) { |
914 | case USER_REGION_ID: | |
915 | user_region = 1; | |
916 | mm = current->mm; | |
3c726f8d BH |
917 | if (! mm) { |
918 | DBG_LOW(" user region with no mm !\n"); | |
1da177e4 | 919 | return 1; |
3c726f8d | 920 | } |
16c2d476 | 921 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
922 | ssize = user_segment_size(ea); |
923 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 924 | break; |
1da177e4 | 925 | case VMALLOC_REGION_ID: |
1da177e4 | 926 | mm = &init_mm; |
1189be65 | 927 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
928 | if (ea < VMALLOC_END) |
929 | psize = mmu_vmalloc_psize; | |
930 | else | |
931 | psize = mmu_io_psize; | |
1189be65 | 932 | ssize = mmu_kernel_ssize; |
1da177e4 | 933 | break; |
1da177e4 LT |
934 | default: |
935 | /* Not a valid range | |
936 | * Send the problem up to do_page_fault | |
937 | */ | |
938 | return 1; | |
1da177e4 | 939 | } |
3c726f8d | 940 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 941 | |
3c726f8d | 942 | /* Get pgdir */ |
1da177e4 | 943 | pgdir = mm->pgd; |
1da177e4 LT |
944 | if (pgdir == NULL) |
945 | return 1; | |
946 | ||
3c726f8d | 947 | /* Check CPU locality */ |
56aa4129 RR |
948 | tmp = cpumask_of(smp_processor_id()); |
949 | if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) | |
1da177e4 LT |
950 | local = 1; |
951 | ||
16c2d476 | 952 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
953 | /* If we use 4K pages and our psize is not 4K, then we might |
954 | * be hitting a special driver mapping, and need to align the | |
955 | * address before we fetch the PTE. | |
956 | * | |
957 | * It could also be a hugepage mapping, in which case this is | |
958 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
959 | */ |
960 | if (psize != MMU_PAGE_4K) | |
961 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
962 | #endif /* CONFIG_PPC_64K_PAGES */ | |
963 | ||
3c726f8d | 964 | /* Get PTE and page size from page tables */ |
a4fe3ce7 | 965 | ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift); |
3c726f8d BH |
966 | if (ptep == NULL || !pte_present(*ptep)) { |
967 | DBG_LOW(" no PTE !\n"); | |
968 | return 1; | |
969 | } | |
970 | ||
ca91e6c0 BH |
971 | /* Add _PAGE_PRESENT to the required access perm */ |
972 | access |= _PAGE_PRESENT; | |
973 | ||
974 | /* Pre-check access permissions (will be re-checked atomically | |
975 | * in __hash_page_XX but this pre-check is a fast path | |
976 | */ | |
977 | if (access & ~pte_val(*ptep)) { | |
978 | DBG_LOW(" no access !\n"); | |
979 | return 1; | |
980 | } | |
981 | ||
a4fe3ce7 DG |
982 | #ifdef CONFIG_HUGETLB_PAGE |
983 | if (hugeshift) | |
984 | return __hash_page_huge(ea, access, vsid, ptep, trap, local, | |
985 | ssize, hugeshift, psize); | |
986 | #endif /* CONFIG_HUGETLB_PAGE */ | |
987 | ||
3c726f8d BH |
988 | #ifndef CONFIG_PPC_64K_PAGES |
989 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
990 | #else | |
991 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
992 | pte_val(*(ptep + PTRS_PER_PTE))); | |
993 | #endif | |
3c726f8d | 994 | /* Do actual hashing */ |
16c2d476 | 995 | #ifdef CONFIG_PPC_64K_PAGES |
721151d0 | 996 | /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ |
3a8247cc | 997 | if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) { |
721151d0 PM |
998 | demote_segment_4k(mm, ea); |
999 | psize = MMU_PAGE_4K; | |
1000 | } | |
1001 | ||
16f1c746 BH |
1002 | /* If this PTE is non-cacheable and we have restrictions on |
1003 | * using non cacheable large pages, then we switch to 4k | |
1004 | */ | |
1005 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && | |
1006 | (pte_val(*ptep) & _PAGE_NO_CACHE)) { | |
1007 | if (user_region) { | |
1008 | demote_segment_4k(mm, ea); | |
1009 | psize = MMU_PAGE_4K; | |
1010 | } else if (ea < VMALLOC_END) { | |
1011 | /* | |
1012 | * some driver did a non-cacheable mapping | |
1013 | * in vmalloc space, so switch vmalloc | |
1014 | * to 4k pages | |
1015 | */ | |
1016 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1017 | "to 4kB pages because of " | |
1018 | "non-cacheable mapping\n"); | |
1019 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
1e57ba8d | 1020 | #ifdef CONFIG_SPU_BASE |
94b2a439 BH |
1021 | spu_flush_all_slbs(mm); |
1022 | #endif | |
bf72aeba | 1023 | } |
16f1c746 BH |
1024 | } |
1025 | if (user_region) { | |
3a8247cc | 1026 | if (psize != get_paca_psize(ea)) { |
f6ab0b92 | 1027 | get_paca()->context = mm->context; |
bf72aeba PM |
1028 | slb_flush_and_rebolt(); |
1029 | } | |
16f1c746 BH |
1030 | } else if (get_paca()->vmalloc_sllp != |
1031 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1032 | get_paca()->vmalloc_sllp = | |
1033 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
67439b76 | 1034 | slb_vmalloc_update(); |
bf72aeba | 1035 | } |
16c2d476 | 1036 | #endif /* CONFIG_PPC_64K_PAGES */ |
16f1c746 | 1037 | |
16c2d476 | 1038 | #ifdef CONFIG_PPC_HAS_HASH_64K |
bf72aeba | 1039 | if (psize == MMU_PAGE_64K) |
1189be65 | 1040 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
3c726f8d | 1041 | else |
16c2d476 | 1042 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
fa28237c | 1043 | { |
a1128f8f | 1044 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1045 | if (access & spp) |
1046 | rc = -2; | |
1047 | else | |
1048 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
1049 | local, ssize, spp); | |
1050 | } | |
3c726f8d | 1051 | |
4b8692c0 BH |
1052 | /* Dump some info in case of hash insertion failure, they should |
1053 | * never happen so it is really useful to know if/when they do | |
1054 | */ | |
1055 | if (rc == -1) | |
1056 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
1057 | pte_val(*ptep)); | |
3c726f8d BH |
1058 | #ifndef CONFIG_PPC_64K_PAGES |
1059 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1060 | #else | |
1061 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1062 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1063 | #endif | |
1064 | DBG_LOW(" -> rc=%d\n", rc); | |
1065 | return rc; | |
1da177e4 | 1066 | } |
67207b96 | 1067 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1068 | |
3c726f8d BH |
1069 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1070 | unsigned long access, unsigned long trap) | |
1da177e4 | 1071 | { |
3c726f8d | 1072 | unsigned long vsid; |
0b97fee0 | 1073 | pgd_t *pgdir; |
3c726f8d | 1074 | pte_t *ptep; |
3c726f8d | 1075 | unsigned long flags; |
4b8692c0 | 1076 | int rc, ssize, local = 0; |
3c726f8d | 1077 | |
d0f13e3c BH |
1078 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1079 | ||
1080 | #ifdef CONFIG_PPC_MM_SLICES | |
1081 | /* We only prefault standard pages for now */ | |
2b02d139 | 1082 | if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize)) |
3c726f8d | 1083 | return; |
d0f13e3c | 1084 | #endif |
3c726f8d BH |
1085 | |
1086 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1087 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1088 | |
16f1c746 | 1089 | /* Get Linux PTE if available */ |
3c726f8d BH |
1090 | pgdir = mm->pgd; |
1091 | if (pgdir == NULL) | |
1092 | return; | |
1093 | ptep = find_linux_pte(pgdir, ea); | |
1094 | if (!ptep) | |
1095 | return; | |
16f1c746 BH |
1096 | |
1097 | #ifdef CONFIG_PPC_64K_PAGES | |
1098 | /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on | |
1099 | * a 64K kernel), then we don't preload, hash_page() will take | |
1100 | * care of it once we actually try to access the page. | |
1101 | * That way we don't have to duplicate all of the logic for segment | |
1102 | * page size demotion here | |
1103 | */ | |
1104 | if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE)) | |
1105 | return; | |
1106 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1107 | ||
1108 | /* Get VSID */ | |
1189be65 PM |
1109 | ssize = user_segment_size(ea); |
1110 | vsid = get_vsid(mm->context.id, ea, ssize); | |
3c726f8d | 1111 | |
16c2d476 | 1112 | /* Hash doesn't like irqs */ |
3c726f8d | 1113 | local_irq_save(flags); |
16c2d476 BH |
1114 | |
1115 | /* Is that local to this CPU ? */ | |
56aa4129 | 1116 | if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) |
3c726f8d | 1117 | local = 1; |
16c2d476 BH |
1118 | |
1119 | /* Hash it in */ | |
1120 | #ifdef CONFIG_PPC_HAS_HASH_64K | |
bf72aeba | 1121 | if (mm->context.user_psize == MMU_PAGE_64K) |
4b8692c0 | 1122 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
1da177e4 | 1123 | else |
5b825831 | 1124 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
4b8692c0 | 1125 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize, |
1c2c25c7 | 1126 | subpage_protection(mm, ea)); |
4b8692c0 BH |
1127 | |
1128 | /* Dump some info in case of hash insertion failure, they should | |
1129 | * never happen so it is really useful to know if/when they do | |
1130 | */ | |
1131 | if (rc == -1) | |
1132 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
1133 | mm->context.user_psize, pte_val(*ptep)); | |
16c2d476 | 1134 | |
3c726f8d BH |
1135 | local_irq_restore(flags); |
1136 | } | |
1137 | ||
f6ab0b92 BH |
1138 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1139 | * do not forget to update the assembly call site ! | |
1140 | */ | |
1189be65 PM |
1141 | void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize, |
1142 | int local) | |
3c726f8d BH |
1143 | { |
1144 | unsigned long hash, index, shift, hidx, slot; | |
1145 | ||
5c339919 | 1146 | DBG_LOW("flush_hash_page(va=%016lx)\n", va); |
3c726f8d | 1147 | pte_iterate_hashed_subpages(pte, psize, va, index, shift) { |
1189be65 | 1148 | hash = hpt_hash(va, shift, ssize); |
3c726f8d BH |
1149 | hidx = __rpte_to_hidx(pte, index); |
1150 | if (hidx & _PTEIDX_SECONDARY) | |
1151 | hash = ~hash; | |
1152 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1153 | slot += hidx & _PTEIDX_GROUP_IX; | |
5c339919 | 1154 | DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx); |
1189be65 | 1155 | ppc_md.hpte_invalidate(slot, va, psize, ssize, local); |
3c726f8d | 1156 | } pte_iterate_hashed_end(); |
1da177e4 LT |
1157 | } |
1158 | ||
61b1a942 | 1159 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1160 | { |
3c726f8d | 1161 | if (ppc_md.flush_hash_range) |
61b1a942 | 1162 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 1163 | else { |
1da177e4 | 1164 | int i; |
61b1a942 BH |
1165 | struct ppc64_tlb_batch *batch = |
1166 | &__get_cpu_var(ppc64_tlb_batch); | |
1da177e4 LT |
1167 | |
1168 | for (i = 0; i < number; i++) | |
3c726f8d | 1169 | flush_hash_page(batch->vaddr[i], batch->pte[i], |
1189be65 | 1170 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1171 | } |
1172 | } | |
1173 | ||
1da177e4 LT |
1174 | /* |
1175 | * low_hash_fault is called when we the low level hash code failed | |
1176 | * to instert a PTE due to an hypervisor error | |
1177 | */ | |
fa28237c | 1178 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 LT |
1179 | { |
1180 | if (user_mode(regs)) { | |
fa28237c PM |
1181 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1182 | if (rc == -2) | |
1183 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1184 | else | |
1185 | #endif | |
1186 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1187 | } else | |
1188 | bad_page_fault(regs, address, SIGBUS); | |
1da177e4 | 1189 | } |
370a908d BH |
1190 | |
1191 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
1192 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1193 | { | |
1189be65 PM |
1194 | unsigned long hash, hpteg; |
1195 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1196 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
bc033b63 | 1197 | unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL); |
370a908d BH |
1198 | int ret; |
1199 | ||
1189be65 | 1200 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1201 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
1202 | ||
1203 | ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr), | |
1189be65 PM |
1204 | mode, HPTE_V_BOLTED, |
1205 | mmu_linear_psize, mmu_kernel_ssize); | |
370a908d BH |
1206 | BUG_ON (ret < 0); |
1207 | spin_lock(&linear_map_hash_lock); | |
1208 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1209 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1210 | spin_unlock(&linear_map_hash_lock); | |
1211 | } | |
1212 | ||
1213 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1214 | { | |
1189be65 PM |
1215 | unsigned long hash, hidx, slot; |
1216 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1217 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
370a908d | 1218 | |
1189be65 | 1219 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1220 | spin_lock(&linear_map_hash_lock); |
1221 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1222 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1223 | linear_map_hash_slots[lmi] = 0; | |
1224 | spin_unlock(&linear_map_hash_lock); | |
1225 | if (hidx & _PTEIDX_SECONDARY) | |
1226 | hash = ~hash; | |
1227 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1228 | slot += hidx & _PTEIDX_GROUP_IX; | |
1189be65 | 1229 | ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0); |
370a908d BH |
1230 | } |
1231 | ||
1232 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
1233 | { | |
1234 | unsigned long flags, vaddr, lmi; | |
1235 | int i; | |
1236 | ||
1237 | local_irq_save(flags); | |
1238 | for (i = 0; i < numpages; i++, page++) { | |
1239 | vaddr = (unsigned long)page_address(page); | |
1240 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1241 | if (lmi >= linear_map_hash_count) | |
1242 | continue; | |
1243 | if (enable) | |
1244 | kernel_map_linear_page(vaddr, lmi); | |
1245 | else | |
1246 | kernel_unmap_linear_page(vaddr, lmi); | |
1247 | } | |
1248 | local_irq_restore(flags); | |
1249 | } | |
1250 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 BH |
1251 | |
1252 | void setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
1253 | phys_addr_t first_memblock_size) | |
1254 | { | |
1255 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1256 | * physical on those processors | |
1257 | */ | |
1258 | BUG_ON(first_memblock_base != 0); | |
1259 | ||
1260 | /* On LPAR systems, the first entry is our RMA region, | |
1261 | * non-LPAR 64-bit hash MMU systems don't have a limitation | |
1262 | * on real mode access, but using the first entry works well | |
1263 | * enough. We also clamp it to 1G to avoid some funky things | |
1264 | * such as RTAS bugs etc... | |
1265 | */ | |
1266 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
1267 | ||
1268 | /* Finally limit subsequent allocations */ | |
1269 | memblock_set_current_limit(ppc64_rma_size); | |
1270 | } |