Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
7f142661 | 24 | #define pr_fmt(fmt) "hash-mmu: " fmt |
1da177e4 LT |
25 | #include <linux/spinlock.h> |
26 | #include <linux/errno.h> | |
589ee628 | 27 | #include <linux/sched/mm.h> |
1da177e4 LT |
28 | #include <linux/proc_fs.h> |
29 | #include <linux/stat.h> | |
30 | #include <linux/sysctl.h> | |
66b15db6 | 31 | #include <linux/export.h> |
1da177e4 LT |
32 | #include <linux/ctype.h> |
33 | #include <linux/cache.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/signal.h> | |
95f72d1e | 36 | #include <linux/memblock.h> |
ba12eede | 37 | #include <linux/context_tracking.h> |
5556ecf5 | 38 | #include <linux/libfdt.h> |
92e3da3c | 39 | #include <linux/pkeys.h> |
1da177e4 | 40 | |
7644d581 | 41 | #include <asm/debugfs.h> |
1da177e4 LT |
42 | #include <asm/processor.h> |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/mmu.h> | |
45 | #include <asm/mmu_context.h> | |
46 | #include <asm/page.h> | |
47 | #include <asm/types.h> | |
7c0f6ba6 | 48 | #include <linux/uaccess.h> |
1da177e4 | 49 | #include <asm/machdep.h> |
d9b2b2a2 | 50 | #include <asm/prom.h> |
1da177e4 LT |
51 | #include <asm/tlbflush.h> |
52 | #include <asm/io.h> | |
53 | #include <asm/eeh.h> | |
54 | #include <asm/tlb.h> | |
55 | #include <asm/cacheflush.h> | |
56 | #include <asm/cputable.h> | |
1da177e4 | 57 | #include <asm/sections.h> |
be3ebfe8 | 58 | #include <asm/copro.h> |
aa39be09 | 59 | #include <asm/udbg.h> |
b68a70c4 | 60 | #include <asm/code-patching.h> |
3ccc00a7 | 61 | #include <asm/fadump.h> |
f5339277 | 62 | #include <asm/firmware.h> |
bc2a9408 | 63 | #include <asm/tm.h> |
cfcb3d80 | 64 | #include <asm/trace.h> |
166dd7d3 | 65 | #include <asm/ps3.h> |
94171b19 | 66 | #include <asm/pte-walk.h> |
1da177e4 LT |
67 | |
68 | #ifdef DEBUG | |
69 | #define DBG(fmt...) udbg_printf(fmt) | |
70 | #else | |
71 | #define DBG(fmt...) | |
72 | #endif | |
73 | ||
3c726f8d BH |
74 | #ifdef DEBUG_LOW |
75 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
76 | #else | |
77 | #define DBG_LOW(fmt...) | |
78 | #endif | |
79 | ||
80 | #define KB (1024) | |
81 | #define MB (1024*KB) | |
658013e9 | 82 | #define GB (1024L*MB) |
3c726f8d | 83 | |
1da177e4 LT |
84 | /* |
85 | * Note: pte --> Linux PTE | |
86 | * HPTE --> PowerPC Hashed Page Table Entry | |
87 | * | |
88 | * Execution context: | |
89 | * htab_initialize is called with the MMU off (of course), but | |
90 | * the kernel has been copied down to zero so it can directly | |
91 | * reference global data. At this point it is very difficult | |
92 | * to print debug info. | |
93 | * | |
94 | */ | |
95 | ||
799d6046 PM |
96 | static unsigned long _SDR1; |
97 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 98 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 99 | |
0eeede0c PM |
100 | u8 hpte_page_sizes[1 << LP_BITS]; |
101 | EXPORT_SYMBOL_GPL(hpte_page_sizes); | |
102 | ||
8e561e7e | 103 | struct hash_pte *htab_address; |
337a7128 | 104 | unsigned long htab_size_bytes; |
96e28449 | 105 | unsigned long htab_hash_mask; |
4ab79aa8 | 106 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 107 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 108 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 109 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 110 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
111 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
112 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
113 | #endif | |
bf72aeba | 114 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 115 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 116 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 117 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 118 | u16 mmu_slb_size = 64; |
4ab79aa8 | 119 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
120 | #ifdef CONFIG_PPC_64K_PAGES |
121 | int mmu_ci_restrictions; | |
122 | #endif | |
370a908d BH |
123 | #ifdef CONFIG_DEBUG_PAGEALLOC |
124 | static u8 *linear_map_hash_slots; | |
125 | static unsigned long linear_map_hash_count; | |
ed166692 | 126 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 127 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
7025776e BH |
128 | struct mmu_hash_ops mmu_hash_ops; |
129 | EXPORT_SYMBOL(mmu_hash_ops); | |
1da177e4 | 130 | |
3c726f8d BH |
131 | /* There are definitions of page sizes arrays to be used when none |
132 | * is provided by the firmware. | |
133 | */ | |
1da177e4 | 134 | |
3c726f8d BH |
135 | /* Pre-POWER4 CPUs (4k pages only) |
136 | */ | |
09de9ff8 | 137 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
138 | [MMU_PAGE_4K] = { |
139 | .shift = 12, | |
140 | .sllp = 0, | |
b1022fbd | 141 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
142 | .avpnm = 0, |
143 | .tlbiel = 0, | |
144 | }, | |
145 | }; | |
146 | ||
147 | /* POWER4, GPUL, POWER5 | |
148 | * | |
149 | * Support for 16Mb large pages | |
150 | */ | |
09de9ff8 | 151 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
152 | [MMU_PAGE_4K] = { |
153 | .shift = 12, | |
154 | .sllp = 0, | |
b1022fbd | 155 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
156 | .avpnm = 0, |
157 | .tlbiel = 1, | |
158 | }, | |
159 | [MMU_PAGE_16M] = { | |
160 | .shift = 24, | |
161 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
162 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
163 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
164 | .avpnm = 0x1UL, |
165 | .tlbiel = 0, | |
166 | }, | |
167 | }; | |
168 | ||
dc47c0c1 AK |
169 | /* |
170 | * 'R' and 'C' update notes: | |
171 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
172 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
173 | * that we use in that case will not update C | |
174 | * - The above is however not a problem, because we also don't do that | |
175 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
176 | * do the right thing and thus we don't have the race I described earlier | |
177 | * | |
178 | * - Under bare metal, we do have the race, so we need R and C set | |
179 | * - We make sure R is always set and never lost | |
180 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
181 | */ | |
c6a3c495 | 182 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 183 | { |
c6a3c495 | 184 | unsigned long rflags = 0; |
bc033b63 BH |
185 | |
186 | /* _PAGE_EXEC -> NOEXEC */ | |
187 | if ((pteflags & _PAGE_EXEC) == 0) | |
188 | rflags |= HPTE_R_N; | |
c6a3c495 | 189 | /* |
e58e87ad | 190 | * PPP bits: |
1ec3f937 | 191 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
192 | * kernel RW areas are mapped with PPP=0b000 |
193 | * User area is mapped with PPP=0b010 for read/write | |
194 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 195 | */ |
e58e87ad AK |
196 | if (pteflags & _PAGE_PRIVILEGED) { |
197 | /* | |
198 | * Kernel read only mapped with ppp bits 0b110 | |
199 | */ | |
984d7a1e AK |
200 | if (!(pteflags & _PAGE_WRITE)) { |
201 | if (mmu_has_feature(MMU_FTR_KERNEL_RO)) | |
202 | rflags |= (HPTE_R_PP0 | 0x2); | |
203 | else | |
204 | rflags |= 0x3; | |
205 | } | |
e58e87ad | 206 | } else { |
c7d54842 AK |
207 | if (pteflags & _PAGE_RWX) |
208 | rflags |= 0x2; | |
209 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
210 | rflags |= 0x1; |
211 | } | |
c8c06f5a | 212 | /* |
dc47c0c1 AK |
213 | * We can't allow hardware to update hpte bits. Hence always |
214 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 215 | */ |
e568006b | 216 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
217 | |
218 | if (pteflags & _PAGE_DIRTY) | |
219 | rflags |= HPTE_R_C; | |
40e8550a AK |
220 | /* |
221 | * Add in WIG bits | |
222 | */ | |
30bda41a AK |
223 | |
224 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 225 | rflags |= HPTE_R_I; |
e568006b | 226 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 227 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
228 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
229 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
230 | else | |
231 | /* | |
232 | * Add memory coherence if cache inhibited is not set | |
233 | */ | |
234 | rflags |= HPTE_R_M; | |
40e8550a | 235 | |
a6590ca5 | 236 | rflags |= pte_to_hpte_pkey_bits(pteflags); |
40e8550a | 237 | return rflags; |
bc033b63 | 238 | } |
3c726f8d BH |
239 | |
240 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 241 | unsigned long pstart, unsigned long prot, |
1189be65 | 242 | int psize, int ssize) |
1da177e4 | 243 | { |
3c726f8d BH |
244 | unsigned long vaddr, paddr; |
245 | unsigned int step, shift; | |
3c726f8d | 246 | int ret = 0; |
1da177e4 | 247 | |
3c726f8d BH |
248 | shift = mmu_psize_defs[psize].shift; |
249 | step = 1 << shift; | |
1da177e4 | 250 | |
bc033b63 BH |
251 | prot = htab_convert_pte_flags(prot); |
252 | ||
253 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
254 | vstart, vend, pstart, prot, psize, ssize); | |
255 | ||
3c726f8d BH |
256 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
257 | vaddr += step, paddr += step) { | |
370a908d | 258 | unsigned long hash, hpteg; |
1189be65 | 259 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 260 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
261 | unsigned long tprot = prot; |
262 | ||
c60ac569 AK |
263 | /* |
264 | * If we hit a bad address return error. | |
265 | */ | |
266 | if (!vsid) | |
267 | return -1; | |
9e88ba4e | 268 | /* Make kernel text executable */ |
549e8152 | 269 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 270 | tprot &= ~HPTE_R_N; |
1da177e4 | 271 | |
b18db0b8 AG |
272 | /* Make kvm guest trampolines executable */ |
273 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
274 | tprot &= ~HPTE_R_N; | |
275 | ||
429d2e83 MS |
276 | /* |
277 | * If relocatable, check if it overlaps interrupt vectors that | |
278 | * are copied down to real 0. For relocatable kernel | |
279 | * (e.g. kdump case) we copy interrupt vectors down to real | |
280 | * address 0. Mark that region as executable. This is | |
281 | * because on p8 system with relocation on exception feature | |
282 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
283 | * in order to execute the interrupt handlers in virtual | |
284 | * mode the vector region need to be marked as executable. | |
285 | */ | |
286 | if ((PHYSICAL_START > MEMORY_START) && | |
287 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
288 | tprot &= ~HPTE_R_N; | |
289 | ||
5524a27d | 290 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
291 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
292 | ||
7025776e BH |
293 | BUG_ON(!mmu_hash_ops.hpte_insert); |
294 | ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, | |
295 | HPTE_V_BOLTED, psize, psize, | |
296 | ssize); | |
c30a4df3 | 297 | |
3c726f8d BH |
298 | if (ret < 0) |
299 | break; | |
e7df0d88 | 300 | |
370a908d | 301 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
302 | if (debug_pagealloc_enabled() && |
303 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
304 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
305 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
306 | } |
307 | return ret < 0 ? ret : 0; | |
308 | } | |
1da177e4 | 309 | |
ed5694a8 | 310 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
311 | int psize, int ssize) |
312 | { | |
313 | unsigned long vaddr; | |
314 | unsigned int step, shift; | |
27828f98 DG |
315 | int rc; |
316 | int ret = 0; | |
f8c8803b BP |
317 | |
318 | shift = mmu_psize_defs[psize].shift; | |
319 | step = 1 << shift; | |
320 | ||
7025776e | 321 | if (!mmu_hash_ops.hpte_removebolted) |
abd0a0e7 | 322 | return -ENODEV; |
f8c8803b | 323 | |
27828f98 | 324 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
7025776e | 325 | rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); |
27828f98 DG |
326 | if (rc == -ENOENT) { |
327 | ret = -ENOENT; | |
328 | continue; | |
329 | } | |
330 | if (rc < 0) | |
331 | return rc; | |
332 | } | |
52db9b44 | 333 | |
27828f98 | 334 | return ret; |
f8c8803b BP |
335 | } |
336 | ||
faf78829 OH |
337 | static bool disable_1tb_segments = false; |
338 | ||
339 | static int __init parse_disable_1tb_segments(char *p) | |
340 | { | |
341 | disable_1tb_segments = true; | |
342 | return 0; | |
343 | } | |
344 | early_param("disable_1tb_segments", parse_disable_1tb_segments); | |
345 | ||
1189be65 PM |
346 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
347 | const char *uname, int depth, | |
348 | void *data) | |
349 | { | |
9d0c4dfe RH |
350 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
351 | const __be32 *prop; | |
352 | int size = 0; | |
1189be65 PM |
353 | |
354 | /* We are scanning "cpu" nodes only */ | |
355 | if (type == NULL || strcmp(type, "cpu") != 0) | |
356 | return 0; | |
357 | ||
12f04f2b | 358 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
359 | if (prop == NULL) |
360 | return 0; | |
361 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 362 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 363 | DBG("1T segment support detected\n"); |
faf78829 OH |
364 | |
365 | if (disable_1tb_segments) { | |
366 | DBG("1T segments disabled by command line\n"); | |
367 | break; | |
368 | } | |
369 | ||
44ae3ab3 | 370 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 371 | return 1; |
1189be65 | 372 | } |
1189be65 | 373 | } |
44ae3ab3 | 374 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
375 | return 0; |
376 | } | |
377 | ||
b1022fbd AK |
378 | static int __init get_idx_from_shift(unsigned int shift) |
379 | { | |
380 | int idx = -1; | |
381 | ||
382 | switch (shift) { | |
383 | case 0xc: | |
384 | idx = MMU_PAGE_4K; | |
385 | break; | |
386 | case 0x10: | |
387 | idx = MMU_PAGE_64K; | |
388 | break; | |
389 | case 0x14: | |
390 | idx = MMU_PAGE_1M; | |
391 | break; | |
392 | case 0x18: | |
393 | idx = MMU_PAGE_16M; | |
394 | break; | |
395 | case 0x22: | |
396 | idx = MMU_PAGE_16G; | |
397 | break; | |
398 | } | |
399 | return idx; | |
400 | } | |
401 | ||
3c726f8d BH |
402 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
403 | const char *uname, int depth, | |
404 | void *data) | |
405 | { | |
9d0c4dfe RH |
406 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
407 | const __be32 *prop; | |
408 | int size = 0; | |
3c726f8d BH |
409 | |
410 | /* We are scanning "cpu" nodes only */ | |
411 | if (type == NULL || strcmp(type, "cpu") != 0) | |
412 | return 0; | |
413 | ||
12f04f2b | 414 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
415 | if (!prop) |
416 | return 0; | |
417 | ||
418 | pr_info("Page sizes from device-tree:\n"); | |
419 | size /= 4; | |
420 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
421 | while(size > 0) { | |
422 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
423 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
424 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
425 | struct mmu_psize_def *def; | |
426 | int idx, base_idx; | |
427 | ||
428 | size -= 3; prop += 3; | |
429 | base_idx = get_idx_from_shift(base_shift); | |
430 | if (base_idx < 0) { | |
431 | /* skip the pte encoding also */ | |
432 | prop += lpnum * 2; size -= lpnum * 2; | |
433 | continue; | |
434 | } | |
435 | def = &mmu_psize_defs[base_idx]; | |
436 | if (base_idx == MMU_PAGE_16M) | |
437 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
438 | ||
439 | def->shift = base_shift; | |
440 | if (base_shift <= 23) | |
441 | def->avpnm = 0; | |
442 | else | |
443 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
444 | def->sllp = slbenc; | |
445 | /* | |
446 | * We don't know for sure what's up with tlbiel, so | |
447 | * for now we only set it for 4K and 64K pages | |
448 | */ | |
449 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
450 | def->tlbiel = 1; | |
451 | else | |
452 | def->tlbiel = 0; | |
453 | ||
454 | while (size > 0 && lpnum) { | |
455 | unsigned int shift = be32_to_cpu(prop[0]); | |
456 | int penc = be32_to_cpu(prop[1]); | |
457 | ||
458 | prop += 2; size -= 2; | |
459 | lpnum--; | |
460 | ||
461 | idx = get_idx_from_shift(shift); | |
462 | if (idx < 0) | |
b1022fbd | 463 | continue; |
9e34992a ME |
464 | |
465 | if (penc == -1) | |
466 | pr_err("Invalid penc for base_shift=%d " | |
467 | "shift=%d\n", base_shift, shift); | |
468 | ||
469 | def->penc[idx] = penc; | |
470 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
471 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
472 | base_shift, shift, def->sllp, | |
473 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 474 | } |
3c726f8d | 475 | } |
9e34992a ME |
476 | |
477 | return 1; | |
3c726f8d BH |
478 | } |
479 | ||
e16a9c09 | 480 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
481 | /* Scan for 16G memory blocks that have been set aside for huge pages |
482 | * and reserve those blocks for 16G huge pages. | |
483 | */ | |
484 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
485 | const char *uname, int depth, | |
486 | void *data) { | |
9d0c4dfe RH |
487 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
488 | const __be64 *addr_prop; | |
489 | const __be32 *page_count_prop; | |
658013e9 JT |
490 | unsigned int expected_pages; |
491 | long unsigned int phys_addr; | |
492 | long unsigned int block_size; | |
493 | ||
494 | /* We are scanning "memory" nodes only */ | |
495 | if (type == NULL || strcmp(type, "memory") != 0) | |
496 | return 0; | |
497 | ||
498 | /* This property is the log base 2 of the number of virtual pages that | |
499 | * will represent this memory block. */ | |
500 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
501 | if (page_count_prop == NULL) | |
502 | return 0; | |
12f04f2b | 503 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
504 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
505 | if (addr_prop == NULL) | |
506 | return 0; | |
12f04f2b AB |
507 | phys_addr = be64_to_cpu(addr_prop[0]); |
508 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
509 | if (block_size != (16 * GB)) |
510 | return 0; | |
511 | printk(KERN_INFO "Huge page(16GB) memory: " | |
512 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
513 | phys_addr, block_size, expected_pages); | |
23493c12 | 514 | if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { |
95f72d1e | 515 | memblock_reserve(phys_addr, block_size * expected_pages); |
79cc38de | 516 | pseries_add_gpage(phys_addr, block_size, expected_pages); |
4792adba | 517 | } |
658013e9 JT |
518 | return 0; |
519 | } | |
e16a9c09 | 520 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 521 | |
b1022fbd AK |
522 | static void mmu_psize_set_default_penc(void) |
523 | { | |
524 | int bpsize, apsize; | |
525 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
526 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
527 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
528 | } | |
529 | ||
9048e648 AG |
530 | #ifdef CONFIG_PPC_64K_PAGES |
531 | ||
532 | static bool might_have_hea(void) | |
533 | { | |
534 | /* | |
535 | * The HEA ethernet adapter requires awareness of the | |
536 | * GX bus. Without that awareness we can easily assume | |
537 | * we will never see an HEA ethernet device. | |
538 | */ | |
539 | #ifdef CONFIG_IBMEBUS | |
2b4e3ad8 | 540 | return !cpu_has_feature(CPU_FTR_ARCH_207S) && |
08bf75ba | 541 | firmware_has_feature(FW_FEATURE_SPLPAR); |
9048e648 AG |
542 | #else |
543 | return false; | |
544 | #endif | |
545 | } | |
546 | ||
547 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
548 | ||
bacf9cf8 | 549 | static void __init htab_scan_page_sizes(void) |
3c726f8d BH |
550 | { |
551 | int rc; | |
552 | ||
b1022fbd AK |
553 | /* se the invalid penc to -1 */ |
554 | mmu_psize_set_default_penc(); | |
555 | ||
3c726f8d BH |
556 | /* Default to 4K pages only */ |
557 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
558 | sizeof(mmu_psize_defaults_old)); | |
559 | ||
560 | /* | |
561 | * Try to find the available page sizes in the device-tree | |
562 | */ | |
563 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
b8f1b4f8 | 564 | if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { |
bacf9cf8 ME |
565 | /* |
566 | * Nothing in the device-tree, but the CPU supports 16M pages, | |
567 | * so let's fallback on a known size list for 16M capable CPUs. | |
568 | */ | |
3c726f8d BH |
569 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
570 | sizeof(mmu_psize_defaults_gp)); | |
bacf9cf8 ME |
571 | } |
572 | ||
573 | #ifdef CONFIG_HUGETLB_PAGE | |
574 | /* Reserve 16G huge page memory sections for huge pages */ | |
575 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
576 | #endif /* CONFIG_HUGETLB_PAGE */ | |
577 | } | |
578 | ||
0eeede0c PM |
579 | /* |
580 | * Fill in the hpte_page_sizes[] array. | |
581 | * We go through the mmu_psize_defs[] array looking for all the | |
582 | * supported base/actual page size combinations. Each combination | |
583 | * has a unique pagesize encoding (penc) value in the low bits of | |
584 | * the LP field of the HPTE. For actual page sizes less than 1MB, | |
585 | * some of the upper LP bits are used for RPN bits, meaning that | |
586 | * we need to fill in several entries in hpte_page_sizes[]. | |
587 | * | |
588 | * In diagrammatic form, with r = RPN bits and z = page size bits: | |
589 | * PTE LP actual page size | |
590 | * rrrr rrrz >=8KB | |
591 | * rrrr rrzz >=16KB | |
592 | * rrrr rzzz >=32KB | |
593 | * rrrr zzzz >=64KB | |
594 | * ... | |
595 | * | |
596 | * The zzzz bits are implementation-specific but are chosen so that | |
597 | * no encoding for a larger page size uses the same value in its | |
598 | * low-order N bits as the encoding for the 2^(12+N) byte page size | |
599 | * (if it exists). | |
600 | */ | |
601 | static void init_hpte_page_sizes(void) | |
602 | { | |
603 | long int ap, bp; | |
604 | long int shift, penc; | |
605 | ||
606 | for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { | |
607 | if (!mmu_psize_defs[bp].shift) | |
608 | continue; /* not a supported page size */ | |
609 | for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { | |
610 | penc = mmu_psize_defs[bp].penc[ap]; | |
10527e80 | 611 | if (penc == -1 || !mmu_psize_defs[ap].shift) |
0eeede0c PM |
612 | continue; |
613 | shift = mmu_psize_defs[ap].shift - LP_SHIFT; | |
614 | if (shift <= 0) | |
615 | continue; /* should never happen */ | |
616 | /* | |
617 | * For page sizes less than 1MB, this loop | |
618 | * replicates the entry for all possible values | |
619 | * of the rrrr bits. | |
620 | */ | |
621 | while (penc < (1 << LP_BITS)) { | |
622 | hpte_page_sizes[penc] = (ap << 4) | bp; | |
623 | penc += 1 << shift; | |
624 | } | |
625 | } | |
626 | } | |
627 | } | |
628 | ||
bacf9cf8 ME |
629 | static void __init htab_init_page_sizes(void) |
630 | { | |
0eeede0c PM |
631 | init_hpte_page_sizes(); |
632 | ||
e7df0d88 JK |
633 | if (!debug_pagealloc_enabled()) { |
634 | /* | |
635 | * Pick a size for the linear mapping. Currently, we only | |
636 | * support 16M, 1M and 4K which is the default | |
637 | */ | |
638 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
639 | mmu_linear_psize = MMU_PAGE_16M; | |
640 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
641 | mmu_linear_psize = MMU_PAGE_1M; | |
642 | } | |
3c726f8d | 643 | |
bf72aeba | 644 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
645 | /* |
646 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
647 | * 64K for user mappings and vmalloc if supported by the processor. |
648 | * We only use 64k for ioremap if the processor | |
649 | * (and firmware) support cache-inhibited large pages. | |
650 | * If not, we use 4k and set mmu_ci_restrictions so that | |
651 | * hash_page knows to switch processes that use cache-inhibited | |
652 | * mappings to 4k pages. | |
3c726f8d | 653 | */ |
bf72aeba | 654 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 655 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 656 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
657 | if (mmu_linear_psize == MMU_PAGE_4K) |
658 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 659 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 660 | /* |
9048e648 AG |
661 | * When running on pSeries using 64k pages for ioremap |
662 | * would stop us accessing the HEA ethernet. So if we | |
663 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 664 | */ |
2b4e3ad8 | 665 | if (!might_have_hea()) |
cfe666b1 PM |
666 | mmu_io_psize = MMU_PAGE_64K; |
667 | } else | |
bf72aeba PM |
668 | mmu_ci_restrictions = 1; |
669 | } | |
370a908d | 670 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 671 | |
cec08e7a BH |
672 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
673 | /* We try to use 16M pages for vmemmap if that is supported | |
674 | * and we have at least 1G of RAM at boot | |
675 | */ | |
676 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 677 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
678 | mmu_vmemmap_psize = MMU_PAGE_16M; |
679 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
680 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
681 | else | |
682 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
683 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
684 | ||
bf72aeba | 685 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
686 | "virtual = %d, io = %d" |
687 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
688 | ", vmemmap = %d" | |
689 | #endif | |
690 | "\n", | |
3c726f8d | 691 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 692 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
693 | mmu_psize_defs[mmu_io_psize].shift |
694 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
695 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
696 | #endif | |
697 | ); | |
3c726f8d BH |
698 | } |
699 | ||
700 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
701 | const char *uname, int depth, | |
702 | void *data) | |
703 | { | |
9d0c4dfe RH |
704 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
705 | const __be32 *prop; | |
3c726f8d BH |
706 | |
707 | /* We are scanning "cpu" nodes only */ | |
708 | if (type == NULL || strcmp(type, "cpu") != 0) | |
709 | return 0; | |
710 | ||
12f04f2b | 711 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
712 | if (prop != NULL) { |
713 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 714 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 715 | return 1; |
1da177e4 | 716 | } |
3c726f8d | 717 | return 0; |
1da177e4 LT |
718 | } |
719 | ||
5c3c7ede | 720 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 721 | { |
5c3c7ede DG |
722 | unsigned memshift = __ilog2(mem_size); |
723 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
724 | unsigned pteg_shift; | |
725 | ||
726 | /* round mem_size up to next power of 2 */ | |
727 | if ((1UL << memshift) < mem_size) | |
728 | memshift += 1; | |
3eac8c69 | 729 | |
5c3c7ede DG |
730 | /* aim for 2 pages / pteg */ |
731 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 732 | |
5c3c7ede DG |
733 | /* |
734 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
735 | * size permitted by the architecture. | |
736 | */ | |
737 | return max(pteg_shift + 7, 18U); | |
738 | } | |
739 | ||
740 | static unsigned long __init htab_get_table_size(void) | |
741 | { | |
3c726f8d | 742 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 743 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 744 | * calculate it now based on the total RAM size |
3eac8c69 | 745 | */ |
3c726f8d BH |
746 | if (ppc64_pft_size == 0) |
747 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
748 | if (ppc64_pft_size) |
749 | return 1UL << ppc64_pft_size; | |
750 | ||
5c3c7ede | 751 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
752 | } |
753 | ||
54b79248 | 754 | #ifdef CONFIG_MEMORY_HOTPLUG |
438cc81a DG |
755 | void resize_hpt_for_hotplug(unsigned long new_mem_size) |
756 | { | |
757 | unsigned target_hpt_shift; | |
758 | ||
759 | if (!mmu_hash_ops.resize_hpt) | |
760 | return; | |
761 | ||
762 | target_hpt_shift = htab_shift_for_mem_size(new_mem_size); | |
763 | ||
764 | /* | |
765 | * To avoid lots of HPT resizes if memory size is fluctuating | |
766 | * across a boundary, we deliberately have some hysterisis | |
767 | * here: we immediately increase the HPT size if the target | |
768 | * shift exceeds the current shift, but we won't attempt to | |
769 | * reduce unless the target shift is at least 2 below the | |
770 | * current shift | |
771 | */ | |
772 | if ((target_hpt_shift > ppc64_pft_size) | |
773 | || (target_hpt_shift < (ppc64_pft_size - 1))) { | |
774 | int rc; | |
775 | ||
776 | rc = mmu_hash_ops.resize_hpt(target_hpt_shift); | |
777 | if (rc) | |
778 | printk(KERN_WARNING | |
779 | "Unable to resize hash page table to target order %d: %d\n", | |
780 | target_hpt_shift, rc); | |
781 | } | |
782 | } | |
783 | ||
32b53c01 | 784 | int hash__create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 785 | { |
1dace6c6 DG |
786 | int rc = htab_bolt_mapping(start, end, __pa(start), |
787 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
788 | mmu_kernel_ssize); | |
789 | ||
790 | if (rc < 0) { | |
791 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
792 | mmu_kernel_ssize); | |
793 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
794 | } | |
795 | return rc; | |
54b79248 | 796 | } |
f8c8803b | 797 | |
32b53c01 | 798 | int hash__remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 799 | { |
abd0a0e7 DG |
800 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
801 | mmu_kernel_ssize); | |
802 | WARN_ON(rc < 0); | |
803 | return rc; | |
f8c8803b | 804 | } |
54b79248 MK |
805 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
806 | ||
ad410674 AK |
807 | static void update_hid_for_hash(void) |
808 | { | |
809 | unsigned long hid0; | |
810 | unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */ | |
811 | ||
812 | asm volatile("ptesync": : :"memory"); | |
813 | /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */ | |
814 | asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) | |
815 | : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory"); | |
816 | asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory"); | |
0428491c BS |
817 | trace_tlbie(0, 0, rb, 0, 2, 0, 0); |
818 | ||
ad410674 AK |
819 | /* |
820 | * now switch the HID | |
821 | */ | |
822 | hid0 = mfspr(SPRN_HID0); | |
823 | hid0 &= ~HID0_POWER9_RADIX; | |
824 | mtspr(SPRN_HID0, hid0); | |
825 | asm volatile("isync": : :"memory"); | |
826 | ||
827 | /* Wait for it to happen */ | |
828 | while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX)) | |
829 | cpu_relax(); | |
830 | } | |
831 | ||
50de596d | 832 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
4b7a3504 | 833 | unsigned long htab_size) |
50de596d | 834 | { |
9d661958 | 835 | mmu_partition_table_init(); |
50de596d AK |
836 | |
837 | /* | |
9d661958 PM |
838 | * PS field (VRMA page size) is not used for LPID 0, hence set to 0. |
839 | * For now, UPRT is 0 and we have no segment table. | |
50de596d | 840 | */ |
4b7a3504 | 841 | htab_size = __ilog2(htab_size) - 18; |
9d661958 | 842 | mmu_partition_table_set_entry(0, hash_table | htab_size, 0); |
56547411 | 843 | pr_info("Partition table %p\n", partition_tb); |
ad410674 AK |
844 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) |
845 | update_hid_for_hash(); | |
50de596d AK |
846 | } |
847 | ||
757c74d2 | 848 | static void __init htab_initialize(void) |
1da177e4 | 849 | { |
337a7128 | 850 | unsigned long table; |
1da177e4 | 851 | unsigned long pteg_count; |
9e88ba4e | 852 | unsigned long prot; |
5556ecf5 | 853 | unsigned long base = 0, size = 0; |
28be7072 | 854 | struct memblock_region *reg; |
3c726f8d | 855 | |
1da177e4 LT |
856 | DBG(" -> htab_initialize()\n"); |
857 | ||
44ae3ab3 | 858 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
859 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
860 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
861 | printk(KERN_INFO "Using 1TB segments\n"); | |
862 | } | |
863 | ||
1da177e4 LT |
864 | /* |
865 | * Calculate the required size of the htab. We want the number of | |
866 | * PTEGs to equal one half the number of real pages. | |
867 | */ | |
3c726f8d | 868 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
869 | pteg_count = htab_size_bytes >> 7; |
870 | ||
1da177e4 LT |
871 | htab_hash_mask = pteg_count - 1; |
872 | ||
5556ecf5 BH |
873 | if (firmware_has_feature(FW_FEATURE_LPAR) || |
874 | firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
1da177e4 LT |
875 | /* Using a hypervisor which owns the htab */ |
876 | htab_address = NULL; | |
877 | _SDR1 = 0; | |
3ccc00a7 MS |
878 | #ifdef CONFIG_FA_DUMP |
879 | /* | |
880 | * If firmware assisted dump is active firmware preserves | |
881 | * the contents of htab along with entire partition memory. | |
882 | * Clear the htab if firmware assisted dump is active so | |
883 | * that we dont end up using old mappings. | |
884 | */ | |
7025776e BH |
885 | if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) |
886 | mmu_hash_ops.hpte_clear_all(); | |
3ccc00a7 | 887 | #endif |
1da177e4 | 888 | } else { |
5556ecf5 BH |
889 | unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; |
890 | ||
891 | #ifdef CONFIG_PPC_CELL | |
892 | /* | |
893 | * Cell may require the hash table down low when using the | |
894 | * Axon IOMMU in order to fit the dynamic region over it, see | |
895 | * comments in cell/iommu.c | |
1da177e4 | 896 | */ |
5556ecf5 | 897 | if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { |
31bf1119 | 898 | limit = 0x80000000; |
5556ecf5 BH |
899 | pr_info("Hash table forced below 2G for Axon IOMMU\n"); |
900 | } | |
901 | #endif /* CONFIG_PPC_CELL */ | |
41d824bf | 902 | |
5556ecf5 BH |
903 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, |
904 | limit); | |
1da177e4 LT |
905 | |
906 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
907 | htab_size_bytes); | |
908 | ||
70267a7f | 909 | htab_address = __va(table); |
1da177e4 LT |
910 | |
911 | /* htab absolute addr + encoded htabsize */ | |
4b7a3504 | 912 | _SDR1 = table + __ilog2(htab_size_bytes) - 18; |
1da177e4 LT |
913 | |
914 | /* Initialize the HPT with no entries */ | |
915 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 916 | |
50de596d AK |
917 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
918 | /* Set SDR1 */ | |
919 | mtspr(SPRN_SDR1, _SDR1); | |
920 | else | |
4b7a3504 | 921 | hash_init_partition_table(table, htab_size_bytes); |
1da177e4 LT |
922 | } |
923 | ||
f5ea64dc | 924 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 925 | |
370a908d | 926 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
927 | if (debug_pagealloc_enabled()) { |
928 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
929 | linear_map_hash_slots = __va(memblock_alloc_base( | |
930 | linear_map_hash_count, 1, ppc64_rma_size)); | |
931 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
932 | } | |
370a908d BH |
933 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
934 | ||
1da177e4 | 935 | /* create bolted the linear mapping in the hash table */ |
28be7072 BH |
936 | for_each_memblock(memory, reg) { |
937 | base = (unsigned long)__va(reg->base); | |
938 | size = reg->size; | |
1da177e4 | 939 | |
5c339919 | 940 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 941 | base, size, prot); |
1da177e4 | 942 | |
caf80e57 | 943 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 944 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
945 | } |
946 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
947 | |
948 | /* | |
949 | * If we have a memory_limit and we've allocated TCEs then we need to | |
950 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
951 | * case that the TCEs start below memory_limit. | |
952 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
953 | * for either 4K or 16MB pages. | |
954 | */ | |
955 | if (tce_alloc_start) { | |
b5666f70 ME |
956 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
957 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
958 | |
959 | if (base + size >= tce_alloc_start) | |
960 | tce_alloc_start = base + size + 1; | |
961 | ||
caf80e57 | 962 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 963 | __pa(tce_alloc_start), prot, |
1189be65 | 964 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
965 | } |
966 | ||
7d0daae4 | 967 | |
1da177e4 LT |
968 | DBG(" <- htab_initialize()\n"); |
969 | } | |
970 | #undef KB | |
971 | #undef MB | |
1da177e4 | 972 | |
bacf9cf8 ME |
973 | void __init hash__early_init_devtree(void) |
974 | { | |
975 | /* Initialize segment sizes */ | |
976 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
977 | ||
978 | /* Initialize page sizes */ | |
979 | htab_scan_page_sizes(); | |
980 | } | |
981 | ||
756d08d1 | 982 | void __init hash__early_init_mmu(void) |
799d6046 | 983 | { |
9d2edb18 | 984 | #ifndef CONFIG_PPC_64K_PAGES |
6aa59f51 | 985 | /* |
9d2edb18 | 986 | * We have code in __hash_page_4K() and elsewhere, which assumes it can |
6aa59f51 AK |
987 | * do the following: |
988 | * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); | |
989 | * | |
990 | * Where the slot number is between 0-15, and values of 8-15 indicate | |
991 | * the secondary bucket. For that code to work H_PAGE_F_SECOND and | |
992 | * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and | |
993 | * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here | |
994 | * with a BUILD_BUG_ON(). | |
995 | */ | |
996 | BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); | |
9d2edb18 | 997 | #endif /* CONFIG_PPC_64K_PAGES */ |
6aa59f51 | 998 | |
bacf9cf8 ME |
999 | htab_init_page_sizes(); |
1000 | ||
dd1842a2 AK |
1001 | /* |
1002 | * initialize page table size | |
1003 | */ | |
5ed7ecd0 AK |
1004 | __pte_frag_nr = H_PTE_FRAG_NR; |
1005 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
1006 | ||
dd1842a2 AK |
1007 | __pte_index_size = H_PTE_INDEX_SIZE; |
1008 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
1009 | __pud_index_size = H_PUD_INDEX_SIZE; | |
1010 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
1011 | __pmd_cache_index = H_PMD_CACHE_INDEX; | |
1012 | __pte_table_size = H_PTE_TABLE_SIZE; | |
1013 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
1014 | __pud_table_size = H_PUD_TABLE_SIZE; | |
1015 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
1016 | /* |
1017 | * 4k use hugepd format, so for hash set then to | |
1018 | * zero | |
1019 | */ | |
1020 | __pmd_val_bits = 0; | |
1021 | __pud_val_bits = 0; | |
1022 | __pgd_val_bits = 0; | |
d6a9996e AK |
1023 | |
1024 | __kernel_virt_start = H_KERN_VIRT_START; | |
1025 | __kernel_virt_size = H_KERN_VIRT_SIZE; | |
1026 | __vmalloc_start = H_VMALLOC_START; | |
1027 | __vmalloc_end = H_VMALLOC_END; | |
63ee9b2f | 1028 | __kernel_io_start = H_KERN_IO_START; |
d6a9996e AK |
1029 | vmemmap = (struct page *)H_VMEMMAP_BASE; |
1030 | ioremap_bot = IOREMAP_BASE; | |
1031 | ||
bfa37087 DS |
1032 | #ifdef CONFIG_PCI |
1033 | pci_io_base = ISA_IO_BASE; | |
1034 | #endif | |
1035 | ||
166dd7d3 BH |
1036 | /* Select appropriate backend */ |
1037 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
1038 | ps3_early_mm_init(); | |
1039 | else if (firmware_has_feature(FW_FEATURE_LPAR)) | |
6364e84e | 1040 | hpte_init_pseries(); |
fbef66f0 | 1041 | else if (IS_ENABLED(CONFIG_PPC_NATIVE)) |
166dd7d3 BH |
1042 | hpte_init_native(); |
1043 | ||
7353644f ME |
1044 | if (!mmu_hash_ops.hpte_insert) |
1045 | panic("hash__early_init_mmu: No MMU hash ops defined!\n"); | |
1046 | ||
757c74d2 | 1047 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
1048 | * of memory. Has to be done before SLB initialization as this is |
1049 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
1050 | */ |
1051 | htab_initialize(); | |
1052 | ||
56547411 | 1053 | pr_info("Initializing hash mmu with SLB\n"); |
376af594 | 1054 | /* Initialize SLB management */ |
13b3d13b | 1055 | slb_initialize(); |
d4748276 NP |
1056 | |
1057 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1058 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1059 | tlbiel_all(); | |
757c74d2 BH |
1060 | } |
1061 | ||
1062 | #ifdef CONFIG_SMP | |
756d08d1 | 1063 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
1064 | { |
1065 | /* Initialize hash table for that CPU */ | |
b5dcc609 | 1066 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
cac4a185 AK |
1067 | |
1068 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | |
1069 | update_hid_for_hash(); | |
1070 | ||
b5dcc609 AK |
1071 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
1072 | mtspr(SPRN_SDR1, _SDR1); | |
1073 | else | |
1074 | mtspr(SPRN_PTCR, | |
1075 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
1076 | } | |
376af594 | 1077 | /* Initialize SLB */ |
13b3d13b | 1078 | slb_initialize(); |
d4748276 NP |
1079 | |
1080 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1081 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1082 | tlbiel_all(); | |
799d6046 | 1083 | } |
757c74d2 | 1084 | #endif /* CONFIG_SMP */ |
799d6046 | 1085 | |
1da177e4 LT |
1086 | /* |
1087 | * Called by asm hashtable.S for doing lazy icache flush | |
1088 | */ | |
1089 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
1090 | { | |
1091 | struct page *page; | |
1092 | ||
76c8e25b BH |
1093 | if (!pfn_valid(pte_pfn(pte))) |
1094 | return pp; | |
1095 | ||
1da177e4 LT |
1096 | page = pte_page(pte); |
1097 | ||
1098 | /* page is dirty */ | |
1099 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
1100 | if (trap == 0x400) { | |
0895ecda | 1101 | flush_dcache_icache_page(page); |
1da177e4 LT |
1102 | set_bit(PG_arch_1, &page->flags); |
1103 | } else | |
3c726f8d | 1104 | pp |= HPTE_R_N; |
1da177e4 LT |
1105 | } |
1106 | return pp; | |
1107 | } | |
1108 | ||
3a8247cc | 1109 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 1110 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1111 | { |
7aa0727f AK |
1112 | u64 lpsizes; |
1113 | unsigned char *hpsizes; | |
1114 | unsigned long index, mask_index; | |
3a8247cc PM |
1115 | |
1116 | if (addr < SLICE_LOW_TOP) { | |
2fc251a8 | 1117 | lpsizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 1118 | index = GET_LOW_SLICE_INDEX(addr); |
7aa0727f | 1119 | return (lpsizes >> (index * 4)) & 0xF; |
3a8247cc | 1120 | } |
2fc251a8 | 1121 | hpsizes = get_paca()->mm_ctx_high_slices_psize; |
7aa0727f AK |
1122 | index = GET_HIGH_SLICE_INDEX(addr); |
1123 | mask_index = index & 0x1; | |
1124 | return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF; | |
3a8247cc PM |
1125 | } |
1126 | ||
1127 | #else | |
1128 | unsigned int get_paca_psize(unsigned long addr) | |
1129 | { | |
c33e54fa | 1130 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
1131 | } |
1132 | #endif | |
1133 | ||
721151d0 PM |
1134 | /* |
1135 | * Demote a segment to using 4k pages. | |
1136 | * For now this makes the whole process use 4k pages. | |
1137 | */ | |
721151d0 | 1138 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1139 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1140 | { |
3a8247cc | 1141 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1142 | return; |
3a8247cc | 1143 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1144 | copro_flush_all_slbs(mm); |
a1dca346 | 1145 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
c395465d | 1146 | |
52b1e665 | 1147 | copy_mm_to_paca(mm); |
fa28237c PM |
1148 | slb_flush_and_rebolt(); |
1149 | } | |
721151d0 | 1150 | } |
16f1c746 | 1151 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1152 | |
fa28237c PM |
1153 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1154 | /* | |
1155 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1156 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1157 | * | |
1158 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1159 | * _PAGE_RWX: no access. |
fa28237c | 1160 | */ |
d28513bc | 1161 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1162 | { |
d28513bc | 1163 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
1164 | u32 spp = 0; |
1165 | u32 **sbpm, *sbpp; | |
1166 | ||
1167 | if (ea >= spt->maxaddr) | |
1168 | return 0; | |
b0d436c7 | 1169 | if (ea < 0x100000000UL) { |
fa28237c PM |
1170 | /* addresses below 4GB use spt->low_prot */ |
1171 | sbpm = spt->low_prot; | |
1172 | } else { | |
1173 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1174 | if (!sbpm) | |
1175 | return 0; | |
1176 | } | |
1177 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1178 | if (!sbpp) | |
1179 | return 0; | |
1180 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1181 | ||
1182 | /* extract 2-bit bitfield for this 4k subpage */ | |
1183 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1184 | ||
73a1441a AK |
1185 | /* |
1186 | * 0 -> full premission | |
1187 | * 1 -> Read only | |
1188 | * 2 -> no access. | |
1189 | * We return the flag that need to be cleared. | |
1190 | */ | |
1191 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1192 | return spp; |
1193 | } | |
1194 | ||
1195 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1196 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1197 | { |
1198 | return 0; | |
1199 | } | |
1200 | #endif | |
1201 | ||
4b8692c0 BH |
1202 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1203 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1204 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1205 | { |
1206 | if (!printk_ratelimit()) | |
1207 | return; | |
1208 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1209 | ea, access, current->comm); | |
d8139ebf AK |
1210 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1211 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1212 | } |
1213 | ||
09567e7f ME |
1214 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1215 | int psize, bool user_region) | |
1216 | { | |
1217 | if (user_region) { | |
1218 | if (psize != get_paca_psize(ea)) { | |
52b1e665 | 1219 | copy_mm_to_paca(mm); |
09567e7f ME |
1220 | slb_flush_and_rebolt(); |
1221 | } | |
1222 | } else if (get_paca()->vmalloc_sllp != | |
1223 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1224 | get_paca()->vmalloc_sllp = | |
1225 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1226 | slb_vmalloc_update(); | |
1227 | } | |
1228 | } | |
1229 | ||
1da177e4 LT |
1230 | /* Result code is: |
1231 | * 0 - handled | |
1232 | * 1 - normal page fault | |
1233 | * -1 - critical hash insertion error | |
fa28237c | 1234 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1235 | */ |
aefa5688 AK |
1236 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1237 | unsigned long access, unsigned long trap, | |
1238 | unsigned long flags) | |
1da177e4 | 1239 | { |
891121e6 | 1240 | bool is_thp; |
ba12eede | 1241 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1242 | pgd_t *pgdir; |
1da177e4 | 1243 | unsigned long vsid; |
1da177e4 | 1244 | pte_t *ptep; |
a4fe3ce7 | 1245 | unsigned hugeshift; |
aefa5688 | 1246 | int rc, user_region = 0; |
1189be65 | 1247 | int psize, ssize; |
1da177e4 | 1248 | |
3c726f8d BH |
1249 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1250 | ea, access, trap); | |
cfcb3d80 | 1251 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1252 | |
3c726f8d | 1253 | /* Get region & vsid */ |
1da177e4 LT |
1254 | switch (REGION_ID(ea)) { |
1255 | case USER_REGION_ID: | |
1256 | user_region = 1; | |
3c726f8d BH |
1257 | if (! mm) { |
1258 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1259 | rc = 1; |
1260 | goto bail; | |
3c726f8d | 1261 | } |
16c2d476 | 1262 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
1263 | ssize = user_segment_size(ea); |
1264 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 1265 | break; |
1da177e4 | 1266 | case VMALLOC_REGION_ID: |
1189be65 | 1267 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1268 | if (ea < VMALLOC_END) |
1269 | psize = mmu_vmalloc_psize; | |
1270 | else | |
1271 | psize = mmu_io_psize; | |
1189be65 | 1272 | ssize = mmu_kernel_ssize; |
1da177e4 | 1273 | break; |
1da177e4 LT |
1274 | default: |
1275 | /* Not a valid range | |
1276 | * Send the problem up to do_page_fault | |
1277 | */ | |
ba12eede LZ |
1278 | rc = 1; |
1279 | goto bail; | |
1da177e4 | 1280 | } |
3c726f8d | 1281 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1282 | |
c60ac569 AK |
1283 | /* Bad address. */ |
1284 | if (!vsid) { | |
1285 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1286 | rc = 1; |
1287 | goto bail; | |
c60ac569 | 1288 | } |
3c726f8d | 1289 | /* Get pgdir */ |
1da177e4 | 1290 | pgdir = mm->pgd; |
ba12eede LZ |
1291 | if (pgdir == NULL) { |
1292 | rc = 1; | |
1293 | goto bail; | |
1294 | } | |
1da177e4 | 1295 | |
3c726f8d | 1296 | /* Check CPU locality */ |
b426e4bd | 1297 | if (user_region && mm_is_thread_local(mm)) |
aefa5688 | 1298 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1299 | |
16c2d476 | 1300 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1301 | /* If we use 4K pages and our psize is not 4K, then we might |
1302 | * be hitting a special driver mapping, and need to align the | |
1303 | * address before we fetch the PTE. | |
1304 | * | |
1305 | * It could also be a hugepage mapping, in which case this is | |
1306 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1307 | */ |
1308 | if (psize != MMU_PAGE_4K) | |
1309 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1310 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1311 | ||
3c726f8d | 1312 | /* Get PTE and page size from page tables */ |
94171b19 | 1313 | ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1314 | if (ptep == NULL || !pte_present(*ptep)) { |
1315 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1316 | rc = 1; |
1317 | goto bail; | |
3c726f8d BH |
1318 | } |
1319 | ||
ca91e6c0 BH |
1320 | /* Add _PAGE_PRESENT to the required access perm */ |
1321 | access |= _PAGE_PRESENT; | |
1322 | ||
1323 | /* Pre-check access permissions (will be re-checked atomically | |
1324 | * in __hash_page_XX but this pre-check is a fast path | |
1325 | */ | |
ac29c640 | 1326 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1327 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1328 | rc = 1; |
1329 | goto bail; | |
ca91e6c0 BH |
1330 | } |
1331 | ||
ba12eede | 1332 | if (hugeshift) { |
891121e6 | 1333 | if (is_thp) |
6d492ecc | 1334 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1335 | trap, flags, ssize, psize); |
6d492ecc AK |
1336 | #ifdef CONFIG_HUGETLB_PAGE |
1337 | else | |
1338 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1339 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1340 | #else |
1341 | else { | |
1342 | /* | |
1343 | * if we have hugeshift, and is not transhuge with | |
1344 | * hugetlb disabled, something is really wrong. | |
1345 | */ | |
1346 | rc = 1; | |
1347 | WARN_ON(1); | |
1348 | } | |
1349 | #endif | |
a1dca346 IM |
1350 | if (current->mm == mm) |
1351 | check_paca_psize(ea, mm, psize, user_region); | |
09567e7f | 1352 | |
ba12eede LZ |
1353 | goto bail; |
1354 | } | |
a4fe3ce7 | 1355 | |
3c726f8d BH |
1356 | #ifndef CONFIG_PPC_64K_PAGES |
1357 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1358 | #else | |
1359 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1360 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1361 | #endif | |
3c726f8d | 1362 | /* Do actual hashing */ |
16c2d476 | 1363 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1364 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1365 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1366 | demote_segment_4k(mm, ea); |
1367 | psize = MMU_PAGE_4K; | |
1368 | } | |
1369 | ||
16f1c746 BH |
1370 | /* If this PTE is non-cacheable and we have restrictions on |
1371 | * using non cacheable large pages, then we switch to 4k | |
1372 | */ | |
30bda41a | 1373 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1374 | if (user_region) { |
1375 | demote_segment_4k(mm, ea); | |
1376 | psize = MMU_PAGE_4K; | |
1377 | } else if (ea < VMALLOC_END) { | |
1378 | /* | |
1379 | * some driver did a non-cacheable mapping | |
1380 | * in vmalloc space, so switch vmalloc | |
1381 | * to 4k pages | |
1382 | */ | |
1383 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1384 | "to 4kB pages because of " | |
1385 | "non-cacheable mapping\n"); | |
1386 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1387 | copro_flush_all_slbs(mm); |
bf72aeba | 1388 | } |
16f1c746 | 1389 | } |
09567e7f | 1390 | |
0863d7f2 AK |
1391 | #endif /* CONFIG_PPC_64K_PAGES */ |
1392 | ||
a1dca346 IM |
1393 | if (current->mm == mm) |
1394 | check_paca_psize(ea, mm, psize, user_region); | |
16f1c746 | 1395 | |
73b341ef | 1396 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1397 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1398 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1399 | flags, ssize); | |
3c726f8d | 1400 | else |
73b341ef | 1401 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1402 | { |
a1128f8f | 1403 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1404 | if (access & spp) |
1405 | rc = -2; | |
1406 | else | |
1407 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1408 | flags, ssize, spp); |
fa28237c | 1409 | } |
3c726f8d | 1410 | |
4b8692c0 BH |
1411 | /* Dump some info in case of hash insertion failure, they should |
1412 | * never happen so it is really useful to know if/when they do | |
1413 | */ | |
1414 | if (rc == -1) | |
1415 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1416 | psize, pte_val(*ptep)); |
3c726f8d BH |
1417 | #ifndef CONFIG_PPC_64K_PAGES |
1418 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1419 | #else | |
1420 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1421 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1422 | #endif | |
1423 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1424 | |
1425 | bail: | |
1426 | exception_exit(prev_state); | |
3c726f8d | 1427 | return rc; |
1da177e4 | 1428 | } |
a1dca346 IM |
1429 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1430 | ||
aefa5688 AK |
1431 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1432 | unsigned long dsisr) | |
a1dca346 | 1433 | { |
aefa5688 | 1434 | unsigned long flags = 0; |
a1dca346 IM |
1435 | struct mm_struct *mm = current->mm; |
1436 | ||
1437 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1438 | mm = &init_mm; | |
1439 | ||
aefa5688 AK |
1440 | if (dsisr & DSISR_NOHPTE) |
1441 | flags |= HPTE_NOHPTE_UPDATE; | |
1442 | ||
1443 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1444 | } |
67207b96 | 1445 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1446 | |
106713a1 AK |
1447 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1448 | unsigned long dsisr) | |
1449 | { | |
c7d54842 | 1450 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1451 | unsigned long flags = 0; |
1452 | struct mm_struct *mm = current->mm; | |
1453 | ||
1454 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1455 | mm = &init_mm; | |
1456 | ||
1457 | if (dsisr & DSISR_NOHPTE) | |
1458 | flags |= HPTE_NOHPTE_UPDATE; | |
1459 | ||
1460 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1461 | access |= _PAGE_WRITE; |
106713a1 | 1462 | /* |
ac29c640 AK |
1463 | * We set _PAGE_PRIVILEGED only when |
1464 | * kernel mode access kernel space. | |
1465 | * | |
1466 | * _PAGE_PRIVILEGED is NOT set | |
1467 | * 1) when kernel mode access user space | |
1468 | * 2) user space access kernel space. | |
106713a1 | 1469 | */ |
ac29c640 | 1470 | access |= _PAGE_PRIVILEGED; |
106713a1 | 1471 | if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID)) |
ac29c640 | 1472 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1473 | |
1474 | if (trap == 0x400) | |
1475 | access |= _PAGE_EXEC; | |
1476 | ||
1477 | return hash_page_mm(mm, ea, access, trap, flags); | |
1478 | } | |
1479 | ||
8bbc9b7b ME |
1480 | #ifdef CONFIG_PPC_MM_SLICES |
1481 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1482 | { | |
aac55d75 ME |
1483 | int psize = get_slice_psize(mm, ea); |
1484 | ||
8bbc9b7b | 1485 | /* We only prefault standard pages for now */ |
aac55d75 ME |
1486 | if (unlikely(psize != mm->context.user_psize)) |
1487 | return false; | |
1488 | ||
1489 | /* | |
1490 | * Don't prefault if subpage protection is enabled for the EA. | |
1491 | */ | |
1492 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1493 | return false; |
1494 | ||
1495 | return true; | |
1496 | } | |
1497 | #else | |
1498 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1499 | { | |
1500 | return true; | |
1501 | } | |
1502 | #endif | |
1503 | ||
3c726f8d BH |
1504 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1505 | unsigned long access, unsigned long trap) | |
1da177e4 | 1506 | { |
12bc9f6f | 1507 | int hugepage_shift; |
3c726f8d | 1508 | unsigned long vsid; |
0b97fee0 | 1509 | pgd_t *pgdir; |
3c726f8d | 1510 | pte_t *ptep; |
3c726f8d | 1511 | unsigned long flags; |
aefa5688 | 1512 | int rc, ssize, update_flags = 0; |
3c726f8d | 1513 | |
d0f13e3c BH |
1514 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1515 | ||
8bbc9b7b | 1516 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1517 | return; |
1518 | ||
1519 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1520 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1521 | |
16f1c746 | 1522 | /* Get Linux PTE if available */ |
3c726f8d BH |
1523 | pgdir = mm->pgd; |
1524 | if (pgdir == NULL) | |
1525 | return; | |
0ac52dd7 AK |
1526 | |
1527 | /* Get VSID */ | |
1528 | ssize = user_segment_size(ea); | |
1529 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1530 | if (!vsid) | |
1531 | return; | |
1532 | /* | |
1533 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1534 | * saves us from holding multiple locks. | |
1535 | */ | |
1536 | local_irq_save(flags); | |
1537 | ||
12bc9f6f AK |
1538 | /* |
1539 | * THP pages use update_mmu_cache_pmd. We don't do | |
1540 | * hash preload there. Hence can ignore THP here | |
1541 | */ | |
94171b19 | 1542 | ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1543 | if (!ptep) |
0ac52dd7 | 1544 | goto out_exit; |
16f1c746 | 1545 | |
12bc9f6f | 1546 | WARN_ON(hugepage_shift); |
16f1c746 | 1547 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1548 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1549 | * a 64K kernel), then we don't preload, hash_page() will take |
1550 | * care of it once we actually try to access the page. | |
1551 | * That way we don't have to duplicate all of the logic for segment | |
1552 | * page size demotion here | |
1553 | */ | |
945537df | 1554 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1555 | goto out_exit; |
16f1c746 BH |
1556 | #endif /* CONFIG_PPC_64K_PAGES */ |
1557 | ||
16c2d476 | 1558 | /* Is that local to this CPU ? */ |
b426e4bd | 1559 | if (mm_is_thread_local(mm)) |
aefa5688 | 1560 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1561 | |
1562 | /* Hash it in */ | |
73b341ef | 1563 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1564 | if (mm->context.user_psize == MMU_PAGE_64K) |
aefa5688 AK |
1565 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1566 | update_flags, ssize); | |
1da177e4 | 1567 | else |
73b341ef | 1568 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1569 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1570 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1571 | |
1572 | /* Dump some info in case of hash insertion failure, they should | |
1573 | * never happen so it is really useful to know if/when they do | |
1574 | */ | |
1575 | if (rc == -1) | |
1576 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1577 | mm->context.user_psize, |
1578 | mm->context.user_psize, | |
1579 | pte_val(*ptep)); | |
0ac52dd7 | 1580 | out_exit: |
3c726f8d BH |
1581 | local_irq_restore(flags); |
1582 | } | |
1583 | ||
087003e9 RP |
1584 | #ifdef CONFIG_PPC_MEM_KEYS |
1585 | /* | |
1586 | * Return the protection key associated with the given address and the | |
1587 | * mm_struct. | |
1588 | */ | |
1589 | u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address) | |
1590 | { | |
1591 | pte_t *ptep; | |
1592 | u16 pkey = 0; | |
1593 | unsigned long flags; | |
1594 | ||
1595 | if (!mm || !mm->pgd) | |
1596 | return 0; | |
1597 | ||
1598 | local_irq_save(flags); | |
1599 | ptep = find_linux_pte(mm->pgd, address, NULL, NULL); | |
1600 | if (ptep) | |
1601 | pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep))); | |
1602 | local_irq_restore(flags); | |
1603 | ||
1604 | return pkey; | |
1605 | } | |
1606 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
1607 | ||
f1a55ce0 RT |
1608 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1609 | static inline void tm_flush_hash_page(int local) | |
1610 | { | |
1611 | /* | |
1612 | * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a | |
1613 | * page back to a block device w/PIO could pick up transactional data | |
1614 | * (bad!) so we force an abort here. Before the sync the page will be | |
1615 | * made read-only, which will flush_hash_page. BIG ISSUE here: if the | |
1616 | * kernel uses a page from userspace without unmapping it first, it may | |
1617 | * see the speculated version. | |
1618 | */ | |
1619 | if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && | |
1620 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1621 | tm_enable(); | |
1622 | tm_abort(TM_CAUSE_TLBI); | |
1623 | } | |
1624 | } | |
1625 | #else | |
1626 | static inline void tm_flush_hash_page(int local) | |
1627 | { | |
1628 | } | |
1629 | #endif | |
1630 | ||
318995b4 RP |
1631 | /* |
1632 | * Return the global hash slot, corresponding to the given PTE, which contains | |
1633 | * the HPTE. | |
1634 | */ | |
1635 | unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, | |
1636 | int ssize, real_pte_t rpte, unsigned int subpg_index) | |
1637 | { | |
1638 | unsigned long hash, gslot, hidx; | |
1639 | ||
1640 | hash = hpt_hash(vpn, shift, ssize); | |
1641 | hidx = __rpte_to_hidx(rpte, subpg_index); | |
1642 | if (hidx & _PTEIDX_SECONDARY) | |
1643 | hash = ~hash; | |
1644 | gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1645 | gslot += hidx & _PTEIDX_GROUP_IX; | |
1646 | return gslot; | |
1647 | } | |
1648 | ||
f6ab0b92 BH |
1649 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1650 | * do not forget to update the assembly call site ! | |
1651 | */ | |
5524a27d | 1652 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1653 | unsigned long flags) |
3c726f8d | 1654 | { |
a8548686 | 1655 | unsigned long index, shift, gslot; |
aefa5688 | 1656 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1657 | |
5524a27d AK |
1658 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1659 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
a8548686 RP |
1660 | gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); |
1661 | DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); | |
db3d8534 AK |
1662 | /* |
1663 | * We use same base page size and actual psize, because we don't | |
1664 | * use these functions for hugepage | |
1665 | */ | |
a8548686 | 1666 | mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, |
7025776e | 1667 | ssize, local); |
3c726f8d | 1668 | } pte_iterate_hashed_end(); |
bc2a9408 | 1669 | |
f1a55ce0 | 1670 | tm_flush_hash_page(local); |
1da177e4 LT |
1671 | } |
1672 | ||
f1581bf1 AK |
1673 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1674 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1675 | pmd_t *pmdp, unsigned int psize, int ssize, |
1676 | unsigned long flags) | |
f1581bf1 AK |
1677 | { |
1678 | int i, max_hpte_count, valid; | |
1679 | unsigned long s_addr; | |
1680 | unsigned char *hpte_slot_array; | |
1681 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1682 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1683 | |
1684 | s_addr = addr & HPAGE_PMD_MASK; | |
1685 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1686 | /* | |
1687 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1688 | * we will find the below NULL. This happens when we do | |
1689 | * split_huge_page_pmd | |
1690 | */ | |
1691 | if (!hpte_slot_array) | |
1692 | return; | |
1693 | ||
7025776e BH |
1694 | if (mmu_hash_ops.hugepage_invalidate) { |
1695 | mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1696 | psize, ssize, local); | |
d557b098 AK |
1697 | goto tm_abort; |
1698 | } | |
f1581bf1 AK |
1699 | /* |
1700 | * No bluk hpte removal support, invalidate each entry | |
1701 | */ | |
1702 | shift = mmu_psize_defs[psize].shift; | |
1703 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1704 | for (i = 0; i < max_hpte_count; i++) { | |
1705 | /* | |
1706 | * 8 bits per each hpte entries | |
1707 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1708 | */ | |
1709 | valid = hpte_valid(hpte_slot_array, i); | |
1710 | if (!valid) | |
1711 | continue; | |
1712 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1713 | ||
1714 | /* get the vpn */ | |
1715 | addr = s_addr + (i * (1ul << shift)); | |
1716 | vpn = hpt_vpn(addr, vsid, ssize); | |
1717 | hash = hpt_hash(vpn, shift, ssize); | |
1718 | if (hidx & _PTEIDX_SECONDARY) | |
1719 | hash = ~hash; | |
1720 | ||
1721 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1722 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1723 | mmu_hash_ops.hpte_invalidate(slot, vpn, psize, |
1724 | MMU_PAGE_16M, ssize, local); | |
d557b098 AK |
1725 | } |
1726 | tm_abort: | |
f1a55ce0 | 1727 | tm_flush_hash_page(local); |
f1581bf1 AK |
1728 | } |
1729 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1730 | ||
61b1a942 | 1731 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1732 | { |
7025776e BH |
1733 | if (mmu_hash_ops.flush_hash_range) |
1734 | mmu_hash_ops.flush_hash_range(number, local); | |
3c726f8d | 1735 | else { |
1da177e4 | 1736 | int i; |
61b1a942 | 1737 | struct ppc64_tlb_batch *batch = |
69111bac | 1738 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1739 | |
1740 | for (i = 0; i < number; i++) | |
5524a27d | 1741 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1742 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1743 | } |
1744 | } | |
1745 | ||
1da177e4 LT |
1746 | /* |
1747 | * low_hash_fault is called when we the low level hash code failed | |
1748 | * to instert a PTE due to an hypervisor error | |
1749 | */ | |
fa28237c | 1750 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1751 | { |
ba12eede LZ |
1752 | enum ctx_state prev_state = exception_enter(); |
1753 | ||
1da177e4 | 1754 | if (user_mode(regs)) { |
fa28237c PM |
1755 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1756 | if (rc == -2) | |
1757 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1758 | else | |
1759 | #endif | |
1760 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1761 | } else | |
1762 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1763 | |
1764 | exception_exit(prev_state); | |
1da177e4 | 1765 | } |
370a908d | 1766 | |
b170bd3d LZ |
1767 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1768 | unsigned long pa, unsigned long rflags, | |
1769 | unsigned long vflags, int psize, int ssize) | |
1770 | { | |
1771 | unsigned long hpte_group; | |
1772 | long slot; | |
1773 | ||
1774 | repeat: | |
1775 | hpte_group = ((hash & htab_hash_mask) * | |
1776 | HPTES_PER_GROUP) & ~0x7UL; | |
1777 | ||
1778 | /* Insert into the hash table, primary slot */ | |
7025776e BH |
1779 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, |
1780 | psize, psize, ssize); | |
b170bd3d LZ |
1781 | |
1782 | /* Primary is full, try the secondary */ | |
1783 | if (unlikely(slot == -1)) { | |
1784 | hpte_group = ((~hash & htab_hash_mask) * | |
1785 | HPTES_PER_GROUP) & ~0x7UL; | |
7025776e BH |
1786 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, |
1787 | vflags | HPTE_V_SECONDARY, | |
1788 | psize, psize, ssize); | |
b170bd3d LZ |
1789 | if (slot == -1) { |
1790 | if (mftb() & 0x1) | |
1791 | hpte_group = ((hash & htab_hash_mask) * | |
1792 | HPTES_PER_GROUP)&~0x7UL; | |
1793 | ||
7025776e | 1794 | mmu_hash_ops.hpte_remove(hpte_group); |
b170bd3d LZ |
1795 | goto repeat; |
1796 | } | |
1797 | } | |
1798 | ||
1799 | return slot; | |
1800 | } | |
1801 | ||
370a908d BH |
1802 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1803 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1804 | { | |
016af59f | 1805 | unsigned long hash; |
1189be65 | 1806 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1807 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1808 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1809 | long ret; |
370a908d | 1810 | |
5524a27d | 1811 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1812 | |
c60ac569 AK |
1813 | /* Don't create HPTE entries for bad address */ |
1814 | if (!vsid) | |
1815 | return; | |
016af59f LZ |
1816 | |
1817 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1818 | HPTE_V_BOLTED, | |
1819 | mmu_linear_psize, mmu_kernel_ssize); | |
1820 | ||
370a908d BH |
1821 | BUG_ON (ret < 0); |
1822 | spin_lock(&linear_map_hash_lock); | |
1823 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1824 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1825 | spin_unlock(&linear_map_hash_lock); | |
1826 | } | |
1827 | ||
1828 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1829 | { | |
1189be65 PM |
1830 | unsigned long hash, hidx, slot; |
1831 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1832 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1833 | |
5524a27d | 1834 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1835 | spin_lock(&linear_map_hash_lock); |
1836 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1837 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1838 | linear_map_hash_slots[lmi] = 0; | |
1839 | spin_unlock(&linear_map_hash_lock); | |
1840 | if (hidx & _PTEIDX_SECONDARY) | |
1841 | hash = ~hash; | |
1842 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1843 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1844 | mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, |
1845 | mmu_linear_psize, | |
1846 | mmu_kernel_ssize, 0); | |
370a908d BH |
1847 | } |
1848 | ||
031bc574 | 1849 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1850 | { |
1851 | unsigned long flags, vaddr, lmi; | |
1852 | int i; | |
1853 | ||
1854 | local_irq_save(flags); | |
1855 | for (i = 0; i < numpages; i++, page++) { | |
1856 | vaddr = (unsigned long)page_address(page); | |
1857 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1858 | if (lmi >= linear_map_hash_count) | |
1859 | continue; | |
1860 | if (enable) | |
1861 | kernel_map_linear_page(vaddr, lmi); | |
1862 | else | |
1863 | kernel_unmap_linear_page(vaddr, lmi); | |
1864 | } | |
1865 | local_irq_restore(flags); | |
1866 | } | |
1867 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1868 | |
756d08d1 | 1869 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1870 | phys_addr_t first_memblock_size) |
1871 | { | |
1872 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1873 | * physical on those processors | |
1874 | */ | |
1875 | BUG_ON(first_memblock_base != 0); | |
1876 | ||
1513c33d NP |
1877 | /* |
1878 | * On virtualized systems the first entry is our RMA region aka VRMA, | |
1879 | * non-virtualized 64-bit hash MMU systems don't have a limitation | |
1880 | * on real mode access. | |
1881 | * | |
c610d65c NP |
1882 | * For guests on platforms before POWER9, we clamp the it limit to 1G |
1883 | * to avoid some funky things such as RTAS bugs etc... | |
cd3db0c4 | 1884 | */ |
1513c33d | 1885 | if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { |
c610d65c NP |
1886 | ppc64_rma_size = first_memblock_size; |
1887 | if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) | |
1888 | ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); | |
cd3db0c4 | 1889 | |
1513c33d NP |
1890 | /* Finally limit subsequent allocations */ |
1891 | memblock_set_current_limit(ppc64_rma_size); | |
1892 | } else { | |
1893 | ppc64_rma_size = ULONG_MAX; | |
1894 | } | |
cd3db0c4 | 1895 | } |
dbcf929c DG |
1896 | |
1897 | #ifdef CONFIG_DEBUG_FS | |
1898 | ||
1899 | static int hpt_order_get(void *data, u64 *val) | |
1900 | { | |
1901 | *val = ppc64_pft_size; | |
1902 | return 0; | |
1903 | } | |
1904 | ||
1905 | static int hpt_order_set(void *data, u64 val) | |
1906 | { | |
1907 | if (!mmu_hash_ops.resize_hpt) | |
1908 | return -ENODEV; | |
1909 | ||
1910 | return mmu_hash_ops.resize_hpt(val); | |
1911 | } | |
1912 | ||
1913 | DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); | |
1914 | ||
1915 | static int __init hash64_debugfs(void) | |
1916 | { | |
1917 | if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, | |
1918 | NULL, &fops_hpt_order)) { | |
1919 | pr_err("lpar: unable to create hpt_order debugsfs file\n"); | |
1920 | } | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | machine_device_initcall(pseries, hash64_debugfs); | |
dbcf929c | 1925 | #endif /* CONFIG_DEBUG_FS */ |