Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
66b15db6 | 30 | #include <linux/export.h> |
1da177e4 LT |
31 | #include <linux/ctype.h> |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
95f72d1e | 35 | #include <linux/memblock.h> |
ba12eede | 36 | #include <linux/context_tracking.h> |
1da177e4 | 37 | |
1da177e4 LT |
38 | #include <asm/processor.h> |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/mmu.h> | |
41 | #include <asm/mmu_context.h> | |
42 | #include <asm/page.h> | |
43 | #include <asm/types.h> | |
1da177e4 LT |
44 | #include <asm/uaccess.h> |
45 | #include <asm/machdep.h> | |
d9b2b2a2 | 46 | #include <asm/prom.h> |
1da177e4 LT |
47 | #include <asm/tlbflush.h> |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
1da177e4 | 53 | #include <asm/sections.h> |
be3ebfe8 | 54 | #include <asm/copro.h> |
aa39be09 | 55 | #include <asm/udbg.h> |
b68a70c4 | 56 | #include <asm/code-patching.h> |
3ccc00a7 | 57 | #include <asm/fadump.h> |
f5339277 | 58 | #include <asm/firmware.h> |
bc2a9408 | 59 | #include <asm/tm.h> |
cfcb3d80 | 60 | #include <asm/trace.h> |
166dd7d3 | 61 | #include <asm/ps3.h> |
1da177e4 LT |
62 | |
63 | #ifdef DEBUG | |
64 | #define DBG(fmt...) udbg_printf(fmt) | |
65 | #else | |
66 | #define DBG(fmt...) | |
67 | #endif | |
68 | ||
3c726f8d BH |
69 | #ifdef DEBUG_LOW |
70 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
71 | #else | |
72 | #define DBG_LOW(fmt...) | |
73 | #endif | |
74 | ||
75 | #define KB (1024) | |
76 | #define MB (1024*KB) | |
658013e9 | 77 | #define GB (1024L*MB) |
3c726f8d | 78 | |
1da177e4 LT |
79 | /* |
80 | * Note: pte --> Linux PTE | |
81 | * HPTE --> PowerPC Hashed Page Table Entry | |
82 | * | |
83 | * Execution context: | |
84 | * htab_initialize is called with the MMU off (of course), but | |
85 | * the kernel has been copied down to zero so it can directly | |
86 | * reference global data. At this point it is very difficult | |
87 | * to print debug info. | |
88 | * | |
89 | */ | |
90 | ||
799d6046 PM |
91 | static unsigned long _SDR1; |
92 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 93 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 94 | |
8e561e7e | 95 | struct hash_pte *htab_address; |
337a7128 | 96 | unsigned long htab_size_bytes; |
96e28449 | 97 | unsigned long htab_hash_mask; |
4ab79aa8 | 98 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 99 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 100 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 101 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 102 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
103 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
104 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
105 | #endif | |
bf72aeba | 106 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 107 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 108 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 109 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 110 | u16 mmu_slb_size = 64; |
4ab79aa8 | 111 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
112 | #ifdef CONFIG_PPC_64K_PAGES |
113 | int mmu_ci_restrictions; | |
114 | #endif | |
370a908d BH |
115 | #ifdef CONFIG_DEBUG_PAGEALLOC |
116 | static u8 *linear_map_hash_slots; | |
117 | static unsigned long linear_map_hash_count; | |
ed166692 | 118 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 119 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 120 | |
3c726f8d BH |
121 | /* There are definitions of page sizes arrays to be used when none |
122 | * is provided by the firmware. | |
123 | */ | |
1da177e4 | 124 | |
3c726f8d BH |
125 | /* Pre-POWER4 CPUs (4k pages only) |
126 | */ | |
09de9ff8 | 127 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
128 | [MMU_PAGE_4K] = { |
129 | .shift = 12, | |
130 | .sllp = 0, | |
b1022fbd | 131 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
132 | .avpnm = 0, |
133 | .tlbiel = 0, | |
134 | }, | |
135 | }; | |
136 | ||
137 | /* POWER4, GPUL, POWER5 | |
138 | * | |
139 | * Support for 16Mb large pages | |
140 | */ | |
09de9ff8 | 141 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
142 | [MMU_PAGE_4K] = { |
143 | .shift = 12, | |
144 | .sllp = 0, | |
b1022fbd | 145 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
146 | .avpnm = 0, |
147 | .tlbiel = 1, | |
148 | }, | |
149 | [MMU_PAGE_16M] = { | |
150 | .shift = 24, | |
151 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
152 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
153 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
154 | .avpnm = 0x1UL, |
155 | .tlbiel = 0, | |
156 | }, | |
157 | }; | |
158 | ||
dc47c0c1 AK |
159 | /* |
160 | * 'R' and 'C' update notes: | |
161 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
162 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
163 | * that we use in that case will not update C | |
164 | * - The above is however not a problem, because we also don't do that | |
165 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
166 | * do the right thing and thus we don't have the race I described earlier | |
167 | * | |
168 | * - Under bare metal, we do have the race, so we need R and C set | |
169 | * - We make sure R is always set and never lost | |
170 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
171 | */ | |
c6a3c495 | 172 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 173 | { |
c6a3c495 | 174 | unsigned long rflags = 0; |
bc033b63 BH |
175 | |
176 | /* _PAGE_EXEC -> NOEXEC */ | |
177 | if ((pteflags & _PAGE_EXEC) == 0) | |
178 | rflags |= HPTE_R_N; | |
c6a3c495 | 179 | /* |
e58e87ad | 180 | * PPP bits: |
1ec3f937 | 181 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
182 | * kernel RW areas are mapped with PPP=0b000 |
183 | * User area is mapped with PPP=0b010 for read/write | |
184 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 185 | */ |
e58e87ad AK |
186 | if (pteflags & _PAGE_PRIVILEGED) { |
187 | /* | |
188 | * Kernel read only mapped with ppp bits 0b110 | |
189 | */ | |
190 | if (!(pteflags & _PAGE_WRITE)) | |
191 | rflags |= (HPTE_R_PP0 | 0x2); | |
192 | } else { | |
c7d54842 AK |
193 | if (pteflags & _PAGE_RWX) |
194 | rflags |= 0x2; | |
195 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
196 | rflags |= 0x1; |
197 | } | |
c8c06f5a | 198 | /* |
dc47c0c1 AK |
199 | * We can't allow hardware to update hpte bits. Hence always |
200 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 201 | */ |
e568006b | 202 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
203 | |
204 | if (pteflags & _PAGE_DIRTY) | |
205 | rflags |= HPTE_R_C; | |
40e8550a AK |
206 | /* |
207 | * Add in WIG bits | |
208 | */ | |
30bda41a AK |
209 | |
210 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 211 | rflags |= HPTE_R_I; |
e568006b | 212 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 213 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
214 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
215 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
216 | else | |
217 | /* | |
218 | * Add memory coherence if cache inhibited is not set | |
219 | */ | |
220 | rflags |= HPTE_R_M; | |
40e8550a AK |
221 | |
222 | return rflags; | |
bc033b63 | 223 | } |
3c726f8d BH |
224 | |
225 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 226 | unsigned long pstart, unsigned long prot, |
1189be65 | 227 | int psize, int ssize) |
1da177e4 | 228 | { |
3c726f8d BH |
229 | unsigned long vaddr, paddr; |
230 | unsigned int step, shift; | |
3c726f8d | 231 | int ret = 0; |
1da177e4 | 232 | |
3c726f8d BH |
233 | shift = mmu_psize_defs[psize].shift; |
234 | step = 1 << shift; | |
1da177e4 | 235 | |
bc033b63 BH |
236 | prot = htab_convert_pte_flags(prot); |
237 | ||
238 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
239 | vstart, vend, pstart, prot, psize, ssize); | |
240 | ||
3c726f8d BH |
241 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
242 | vaddr += step, paddr += step) { | |
370a908d | 243 | unsigned long hash, hpteg; |
1189be65 | 244 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 245 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
246 | unsigned long tprot = prot; |
247 | ||
c60ac569 AK |
248 | /* |
249 | * If we hit a bad address return error. | |
250 | */ | |
251 | if (!vsid) | |
252 | return -1; | |
9e88ba4e | 253 | /* Make kernel text executable */ |
549e8152 | 254 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 255 | tprot &= ~HPTE_R_N; |
1da177e4 | 256 | |
b18db0b8 AG |
257 | /* Make kvm guest trampolines executable */ |
258 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
259 | tprot &= ~HPTE_R_N; | |
260 | ||
429d2e83 MS |
261 | /* |
262 | * If relocatable, check if it overlaps interrupt vectors that | |
263 | * are copied down to real 0. For relocatable kernel | |
264 | * (e.g. kdump case) we copy interrupt vectors down to real | |
265 | * address 0. Mark that region as executable. This is | |
266 | * because on p8 system with relocation on exception feature | |
267 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
268 | * in order to execute the interrupt handlers in virtual | |
269 | * mode the vector region need to be marked as executable. | |
270 | */ | |
271 | if ((PHYSICAL_START > MEMORY_START) && | |
272 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
273 | tprot &= ~HPTE_R_N; | |
274 | ||
5524a27d | 275 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
276 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
277 | ||
c30a4df3 | 278 | BUG_ON(!ppc_md.hpte_insert); |
5524a27d | 279 | ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot, |
b1022fbd | 280 | HPTE_V_BOLTED, psize, psize, ssize); |
c30a4df3 | 281 | |
3c726f8d BH |
282 | if (ret < 0) |
283 | break; | |
e7df0d88 | 284 | |
370a908d | 285 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
286 | if (debug_pagealloc_enabled() && |
287 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
288 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
289 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
290 | } |
291 | return ret < 0 ? ret : 0; | |
292 | } | |
1da177e4 | 293 | |
ed5694a8 | 294 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
295 | int psize, int ssize) |
296 | { | |
297 | unsigned long vaddr; | |
298 | unsigned int step, shift; | |
27828f98 DG |
299 | int rc; |
300 | int ret = 0; | |
f8c8803b BP |
301 | |
302 | shift = mmu_psize_defs[psize].shift; | |
303 | step = 1 << shift; | |
304 | ||
abd0a0e7 DG |
305 | if (!ppc_md.hpte_removebolted) |
306 | return -ENODEV; | |
f8c8803b | 307 | |
27828f98 DG |
308 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
309 | rc = ppc_md.hpte_removebolted(vaddr, psize, ssize); | |
310 | if (rc == -ENOENT) { | |
311 | ret = -ENOENT; | |
312 | continue; | |
313 | } | |
314 | if (rc < 0) | |
315 | return rc; | |
316 | } | |
52db9b44 | 317 | |
27828f98 | 318 | return ret; |
f8c8803b BP |
319 | } |
320 | ||
faf78829 OH |
321 | static bool disable_1tb_segments = false; |
322 | ||
323 | static int __init parse_disable_1tb_segments(char *p) | |
324 | { | |
325 | disable_1tb_segments = true; | |
326 | return 0; | |
327 | } | |
328 | early_param("disable_1tb_segments", parse_disable_1tb_segments); | |
329 | ||
1189be65 PM |
330 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
331 | const char *uname, int depth, | |
332 | void *data) | |
333 | { | |
9d0c4dfe RH |
334 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
335 | const __be32 *prop; | |
336 | int size = 0; | |
1189be65 PM |
337 | |
338 | /* We are scanning "cpu" nodes only */ | |
339 | if (type == NULL || strcmp(type, "cpu") != 0) | |
340 | return 0; | |
341 | ||
12f04f2b | 342 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
343 | if (prop == NULL) |
344 | return 0; | |
345 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 346 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 347 | DBG("1T segment support detected\n"); |
faf78829 OH |
348 | |
349 | if (disable_1tb_segments) { | |
350 | DBG("1T segments disabled by command line\n"); | |
351 | break; | |
352 | } | |
353 | ||
44ae3ab3 | 354 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 355 | return 1; |
1189be65 | 356 | } |
1189be65 | 357 | } |
44ae3ab3 | 358 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
359 | return 0; |
360 | } | |
361 | ||
362 | static void __init htab_init_seg_sizes(void) | |
363 | { | |
364 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
365 | } | |
366 | ||
b1022fbd AK |
367 | static int __init get_idx_from_shift(unsigned int shift) |
368 | { | |
369 | int idx = -1; | |
370 | ||
371 | switch (shift) { | |
372 | case 0xc: | |
373 | idx = MMU_PAGE_4K; | |
374 | break; | |
375 | case 0x10: | |
376 | idx = MMU_PAGE_64K; | |
377 | break; | |
378 | case 0x14: | |
379 | idx = MMU_PAGE_1M; | |
380 | break; | |
381 | case 0x18: | |
382 | idx = MMU_PAGE_16M; | |
383 | break; | |
384 | case 0x22: | |
385 | idx = MMU_PAGE_16G; | |
386 | break; | |
387 | } | |
388 | return idx; | |
389 | } | |
390 | ||
3c726f8d BH |
391 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
392 | const char *uname, int depth, | |
393 | void *data) | |
394 | { | |
9d0c4dfe RH |
395 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
396 | const __be32 *prop; | |
397 | int size = 0; | |
3c726f8d BH |
398 | |
399 | /* We are scanning "cpu" nodes only */ | |
400 | if (type == NULL || strcmp(type, "cpu") != 0) | |
401 | return 0; | |
402 | ||
12f04f2b | 403 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
404 | if (!prop) |
405 | return 0; | |
406 | ||
407 | pr_info("Page sizes from device-tree:\n"); | |
408 | size /= 4; | |
409 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
410 | while(size > 0) { | |
411 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
412 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
413 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
414 | struct mmu_psize_def *def; | |
415 | int idx, base_idx; | |
416 | ||
417 | size -= 3; prop += 3; | |
418 | base_idx = get_idx_from_shift(base_shift); | |
419 | if (base_idx < 0) { | |
420 | /* skip the pte encoding also */ | |
421 | prop += lpnum * 2; size -= lpnum * 2; | |
422 | continue; | |
423 | } | |
424 | def = &mmu_psize_defs[base_idx]; | |
425 | if (base_idx == MMU_PAGE_16M) | |
426 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
427 | ||
428 | def->shift = base_shift; | |
429 | if (base_shift <= 23) | |
430 | def->avpnm = 0; | |
431 | else | |
432 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
433 | def->sllp = slbenc; | |
434 | /* | |
435 | * We don't know for sure what's up with tlbiel, so | |
436 | * for now we only set it for 4K and 64K pages | |
437 | */ | |
438 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
439 | def->tlbiel = 1; | |
440 | else | |
441 | def->tlbiel = 0; | |
442 | ||
443 | while (size > 0 && lpnum) { | |
444 | unsigned int shift = be32_to_cpu(prop[0]); | |
445 | int penc = be32_to_cpu(prop[1]); | |
446 | ||
447 | prop += 2; size -= 2; | |
448 | lpnum--; | |
449 | ||
450 | idx = get_idx_from_shift(shift); | |
451 | if (idx < 0) | |
b1022fbd | 452 | continue; |
9e34992a ME |
453 | |
454 | if (penc == -1) | |
455 | pr_err("Invalid penc for base_shift=%d " | |
456 | "shift=%d\n", base_shift, shift); | |
457 | ||
458 | def->penc[idx] = penc; | |
459 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
460 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
461 | base_shift, shift, def->sllp, | |
462 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 463 | } |
3c726f8d | 464 | } |
9e34992a ME |
465 | |
466 | return 1; | |
3c726f8d BH |
467 | } |
468 | ||
e16a9c09 | 469 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
470 | /* Scan for 16G memory blocks that have been set aside for huge pages |
471 | * and reserve those blocks for 16G huge pages. | |
472 | */ | |
473 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
474 | const char *uname, int depth, | |
475 | void *data) { | |
9d0c4dfe RH |
476 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
477 | const __be64 *addr_prop; | |
478 | const __be32 *page_count_prop; | |
658013e9 JT |
479 | unsigned int expected_pages; |
480 | long unsigned int phys_addr; | |
481 | long unsigned int block_size; | |
482 | ||
483 | /* We are scanning "memory" nodes only */ | |
484 | if (type == NULL || strcmp(type, "memory") != 0) | |
485 | return 0; | |
486 | ||
487 | /* This property is the log base 2 of the number of virtual pages that | |
488 | * will represent this memory block. */ | |
489 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
490 | if (page_count_prop == NULL) | |
491 | return 0; | |
12f04f2b | 492 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
493 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
494 | if (addr_prop == NULL) | |
495 | return 0; | |
12f04f2b AB |
496 | phys_addr = be64_to_cpu(addr_prop[0]); |
497 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
498 | if (block_size != (16 * GB)) |
499 | return 0; | |
500 | printk(KERN_INFO "Huge page(16GB) memory: " | |
501 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
502 | phys_addr, block_size, expected_pages); | |
95f72d1e YL |
503 | if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) { |
504 | memblock_reserve(phys_addr, block_size * expected_pages); | |
4792adba JT |
505 | add_gpage(phys_addr, block_size, expected_pages); |
506 | } | |
658013e9 JT |
507 | return 0; |
508 | } | |
e16a9c09 | 509 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 510 | |
b1022fbd AK |
511 | static void mmu_psize_set_default_penc(void) |
512 | { | |
513 | int bpsize, apsize; | |
514 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
515 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
516 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
517 | } | |
518 | ||
9048e648 AG |
519 | #ifdef CONFIG_PPC_64K_PAGES |
520 | ||
521 | static bool might_have_hea(void) | |
522 | { | |
523 | /* | |
524 | * The HEA ethernet adapter requires awareness of the | |
525 | * GX bus. Without that awareness we can easily assume | |
526 | * we will never see an HEA ethernet device. | |
527 | */ | |
528 | #ifdef CONFIG_IBMEBUS | |
529 | return !cpu_has_feature(CPU_FTR_ARCH_207S); | |
530 | #else | |
531 | return false; | |
532 | #endif | |
533 | } | |
534 | ||
535 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
536 | ||
3c726f8d BH |
537 | static void __init htab_init_page_sizes(void) |
538 | { | |
539 | int rc; | |
540 | ||
b1022fbd AK |
541 | /* se the invalid penc to -1 */ |
542 | mmu_psize_set_default_penc(); | |
543 | ||
3c726f8d BH |
544 | /* Default to 4K pages only */ |
545 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
546 | sizeof(mmu_psize_defaults_old)); | |
547 | ||
548 | /* | |
549 | * Try to find the available page sizes in the device-tree | |
550 | */ | |
551 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
552 | if (rc != 0) /* Found */ | |
553 | goto found; | |
554 | ||
555 | /* | |
556 | * Not in the device-tree, let's fallback on known size | |
557 | * list for 16M capable GP & GR | |
558 | */ | |
44ae3ab3 | 559 | if (mmu_has_feature(MMU_FTR_16M_PAGE)) |
3c726f8d BH |
560 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
561 | sizeof(mmu_psize_defaults_gp)); | |
e7df0d88 JK |
562 | found: |
563 | if (!debug_pagealloc_enabled()) { | |
564 | /* | |
565 | * Pick a size for the linear mapping. Currently, we only | |
566 | * support 16M, 1M and 4K which is the default | |
567 | */ | |
568 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
569 | mmu_linear_psize = MMU_PAGE_16M; | |
570 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
571 | mmu_linear_psize = MMU_PAGE_1M; | |
572 | } | |
3c726f8d | 573 | |
bf72aeba | 574 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
575 | /* |
576 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
577 | * 64K for user mappings and vmalloc if supported by the processor. |
578 | * We only use 64k for ioremap if the processor | |
579 | * (and firmware) support cache-inhibited large pages. | |
580 | * If not, we use 4k and set mmu_ci_restrictions so that | |
581 | * hash_page knows to switch processes that use cache-inhibited | |
582 | * mappings to 4k pages. | |
3c726f8d | 583 | */ |
bf72aeba | 584 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 585 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 586 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
587 | if (mmu_linear_psize == MMU_PAGE_4K) |
588 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 589 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 590 | /* |
9048e648 AG |
591 | * When running on pSeries using 64k pages for ioremap |
592 | * would stop us accessing the HEA ethernet. So if we | |
593 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 594 | */ |
9048e648 | 595 | if (!might_have_hea() || !machine_is(pseries)) |
cfe666b1 PM |
596 | mmu_io_psize = MMU_PAGE_64K; |
597 | } else | |
bf72aeba PM |
598 | mmu_ci_restrictions = 1; |
599 | } | |
370a908d | 600 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 601 | |
cec08e7a BH |
602 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
603 | /* We try to use 16M pages for vmemmap if that is supported | |
604 | * and we have at least 1G of RAM at boot | |
605 | */ | |
606 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 607 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
608 | mmu_vmemmap_psize = MMU_PAGE_16M; |
609 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
610 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
611 | else | |
612 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
613 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
614 | ||
bf72aeba | 615 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
616 | "virtual = %d, io = %d" |
617 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
618 | ", vmemmap = %d" | |
619 | #endif | |
620 | "\n", | |
3c726f8d | 621 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 622 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
623 | mmu_psize_defs[mmu_io_psize].shift |
624 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
625 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
626 | #endif | |
627 | ); | |
3c726f8d BH |
628 | |
629 | #ifdef CONFIG_HUGETLB_PAGE | |
658013e9 JT |
630 | /* Reserve 16G huge page memory sections for huge pages */ |
631 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
3c726f8d BH |
632 | #endif /* CONFIG_HUGETLB_PAGE */ |
633 | } | |
634 | ||
635 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
636 | const char *uname, int depth, | |
637 | void *data) | |
638 | { | |
9d0c4dfe RH |
639 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
640 | const __be32 *prop; | |
3c726f8d BH |
641 | |
642 | /* We are scanning "cpu" nodes only */ | |
643 | if (type == NULL || strcmp(type, "cpu") != 0) | |
644 | return 0; | |
645 | ||
12f04f2b | 646 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
647 | if (prop != NULL) { |
648 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 649 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 650 | return 1; |
1da177e4 | 651 | } |
3c726f8d | 652 | return 0; |
1da177e4 LT |
653 | } |
654 | ||
5c3c7ede | 655 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 656 | { |
5c3c7ede DG |
657 | unsigned memshift = __ilog2(mem_size); |
658 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
659 | unsigned pteg_shift; | |
660 | ||
661 | /* round mem_size up to next power of 2 */ | |
662 | if ((1UL << memshift) < mem_size) | |
663 | memshift += 1; | |
3eac8c69 | 664 | |
5c3c7ede DG |
665 | /* aim for 2 pages / pteg */ |
666 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 667 | |
5c3c7ede DG |
668 | /* |
669 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
670 | * size permitted by the architecture. | |
671 | */ | |
672 | return max(pteg_shift + 7, 18U); | |
673 | } | |
674 | ||
675 | static unsigned long __init htab_get_table_size(void) | |
676 | { | |
3c726f8d | 677 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 678 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 679 | * calculate it now based on the total RAM size |
3eac8c69 | 680 | */ |
3c726f8d BH |
681 | if (ppc64_pft_size == 0) |
682 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
683 | if (ppc64_pft_size) |
684 | return 1UL << ppc64_pft_size; | |
685 | ||
5c3c7ede | 686 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
687 | } |
688 | ||
54b79248 | 689 | #ifdef CONFIG_MEMORY_HOTPLUG |
a1194097 | 690 | int create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 691 | { |
1dace6c6 DG |
692 | int rc = htab_bolt_mapping(start, end, __pa(start), |
693 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
694 | mmu_kernel_ssize); | |
695 | ||
696 | if (rc < 0) { | |
697 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
698 | mmu_kernel_ssize); | |
699 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
700 | } | |
701 | return rc; | |
54b79248 | 702 | } |
f8c8803b | 703 | |
52db9b44 | 704 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 705 | { |
abd0a0e7 DG |
706 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
707 | mmu_kernel_ssize); | |
708 | WARN_ON(rc < 0); | |
709 | return rc; | |
f8c8803b | 710 | } |
54b79248 MK |
711 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
712 | ||
50de596d | 713 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
4b7a3504 | 714 | unsigned long htab_size) |
50de596d AK |
715 | { |
716 | unsigned long ps_field; | |
50de596d AK |
717 | unsigned long patb_size = 1UL << PATB_SIZE_SHIFT; |
718 | ||
719 | /* | |
720 | * slb llp encoding for the page size used in VPM real mode. | |
721 | * We can ignore that for lpid 0 | |
722 | */ | |
723 | ps_field = 0; | |
4b7a3504 | 724 | htab_size = __ilog2(htab_size) - 18; |
50de596d AK |
725 | |
726 | BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large."); | |
727 | partition_tb = __va(memblock_alloc_base(patb_size, patb_size, | |
728 | MEMBLOCK_ALLOC_ANYWHERE)); | |
729 | ||
730 | /* Initialize the Partition Table with no entries */ | |
731 | memset((void *)partition_tb, 0, patb_size); | |
732 | partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size); | |
733 | /* | |
734 | * FIXME!! This should be done via update_partition table | |
735 | * For now UPRT is 0 for us. | |
736 | */ | |
737 | partition_tb->patb1 = 0; | |
56547411 | 738 | pr_info("Partition table %p\n", partition_tb); |
50de596d AK |
739 | /* |
740 | * update partition table control register, | |
741 | * 64 K size. | |
742 | */ | |
743 | mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
744 | ||
745 | } | |
746 | ||
757c74d2 | 747 | static void __init htab_initialize(void) |
1da177e4 | 748 | { |
337a7128 | 749 | unsigned long table; |
1da177e4 | 750 | unsigned long pteg_count; |
9e88ba4e | 751 | unsigned long prot; |
41d824bf | 752 | unsigned long base = 0, size = 0, limit; |
28be7072 | 753 | struct memblock_region *reg; |
3c726f8d | 754 | |
1da177e4 LT |
755 | DBG(" -> htab_initialize()\n"); |
756 | ||
1189be65 PM |
757 | /* Initialize segment sizes */ |
758 | htab_init_seg_sizes(); | |
759 | ||
3c726f8d BH |
760 | /* Initialize page sizes */ |
761 | htab_init_page_sizes(); | |
762 | ||
44ae3ab3 | 763 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
764 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
765 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
766 | printk(KERN_INFO "Using 1TB segments\n"); | |
767 | } | |
768 | ||
1da177e4 LT |
769 | /* |
770 | * Calculate the required size of the htab. We want the number of | |
771 | * PTEGs to equal one half the number of real pages. | |
772 | */ | |
3c726f8d | 773 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
774 | pteg_count = htab_size_bytes >> 7; |
775 | ||
1da177e4 LT |
776 | htab_hash_mask = pteg_count - 1; |
777 | ||
57cfb814 | 778 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
779 | /* Using a hypervisor which owns the htab */ |
780 | htab_address = NULL; | |
781 | _SDR1 = 0; | |
3ccc00a7 MS |
782 | #ifdef CONFIG_FA_DUMP |
783 | /* | |
784 | * If firmware assisted dump is active firmware preserves | |
785 | * the contents of htab along with entire partition memory. | |
786 | * Clear the htab if firmware assisted dump is active so | |
787 | * that we dont end up using old mappings. | |
788 | */ | |
789 | if (is_fadump_active() && ppc_md.hpte_clear_all) | |
790 | ppc_md.hpte_clear_all(); | |
791 | #endif | |
1da177e4 LT |
792 | } else { |
793 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf | 794 | * the absolute address space. On cell we want it to be |
31bf1119 | 795 | * in the first 2 Gig so we can use it for IOMMU hacks. |
1da177e4 | 796 | */ |
41d824bf | 797 | if (machine_is(cell)) |
31bf1119 | 798 | limit = 0x80000000; |
41d824bf | 799 | else |
27f574c2 | 800 | limit = MEMBLOCK_ALLOC_ANYWHERE; |
41d824bf | 801 | |
95f72d1e | 802 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit); |
1da177e4 LT |
803 | |
804 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
805 | htab_size_bytes); | |
806 | ||
70267a7f | 807 | htab_address = __va(table); |
1da177e4 LT |
808 | |
809 | /* htab absolute addr + encoded htabsize */ | |
4b7a3504 | 810 | _SDR1 = table + __ilog2(htab_size_bytes) - 18; |
1da177e4 LT |
811 | |
812 | /* Initialize the HPT with no entries */ | |
813 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 814 | |
50de596d AK |
815 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
816 | /* Set SDR1 */ | |
817 | mtspr(SPRN_SDR1, _SDR1); | |
818 | else | |
4b7a3504 | 819 | hash_init_partition_table(table, htab_size_bytes); |
1da177e4 LT |
820 | } |
821 | ||
f5ea64dc | 822 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 823 | |
370a908d | 824 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
825 | if (debug_pagealloc_enabled()) { |
826 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
827 | linear_map_hash_slots = __va(memblock_alloc_base( | |
828 | linear_map_hash_count, 1, ppc64_rma_size)); | |
829 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
830 | } | |
370a908d BH |
831 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
832 | ||
1da177e4 LT |
833 | /* On U3 based machines, we need to reserve the DART area and |
834 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
835 | * cacheable later on | |
836 | */ | |
1da177e4 LT |
837 | |
838 | /* create bolted the linear mapping in the hash table */ | |
28be7072 BH |
839 | for_each_memblock(memory, reg) { |
840 | base = (unsigned long)__va(reg->base); | |
841 | size = reg->size; | |
1da177e4 | 842 | |
5c339919 | 843 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 844 | base, size, prot); |
1da177e4 | 845 | |
caf80e57 | 846 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 847 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
848 | } |
849 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
850 | |
851 | /* | |
852 | * If we have a memory_limit and we've allocated TCEs then we need to | |
853 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
854 | * case that the TCEs start below memory_limit. | |
855 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
856 | * for either 4K or 16MB pages. | |
857 | */ | |
858 | if (tce_alloc_start) { | |
b5666f70 ME |
859 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
860 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
861 | |
862 | if (base + size >= tce_alloc_start) | |
863 | tce_alloc_start = base + size + 1; | |
864 | ||
caf80e57 | 865 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 866 | __pa(tce_alloc_start), prot, |
1189be65 | 867 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
868 | } |
869 | ||
7d0daae4 | 870 | |
1da177e4 LT |
871 | DBG(" <- htab_initialize()\n"); |
872 | } | |
873 | #undef KB | |
874 | #undef MB | |
1da177e4 | 875 | |
166dd7d3 BH |
876 | void __init __weak hpte_init_lpar(void) |
877 | { | |
878 | panic("FW_FEATURE_LPAR set but no LPAR support compiled\n"); | |
879 | } | |
880 | ||
756d08d1 | 881 | void __init hash__early_init_mmu(void) |
799d6046 | 882 | { |
dd1842a2 AK |
883 | /* |
884 | * initialize page table size | |
885 | */ | |
5ed7ecd0 AK |
886 | __pte_frag_nr = H_PTE_FRAG_NR; |
887 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
888 | ||
dd1842a2 AK |
889 | __pte_index_size = H_PTE_INDEX_SIZE; |
890 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
891 | __pud_index_size = H_PUD_INDEX_SIZE; | |
892 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
893 | __pmd_cache_index = H_PMD_CACHE_INDEX; | |
894 | __pte_table_size = H_PTE_TABLE_SIZE; | |
895 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
896 | __pud_table_size = H_PUD_TABLE_SIZE; | |
897 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
898 | /* |
899 | * 4k use hugepd format, so for hash set then to | |
900 | * zero | |
901 | */ | |
902 | __pmd_val_bits = 0; | |
903 | __pud_val_bits = 0; | |
904 | __pgd_val_bits = 0; | |
d6a9996e AK |
905 | |
906 | __kernel_virt_start = H_KERN_VIRT_START; | |
907 | __kernel_virt_size = H_KERN_VIRT_SIZE; | |
908 | __vmalloc_start = H_VMALLOC_START; | |
909 | __vmalloc_end = H_VMALLOC_END; | |
910 | vmemmap = (struct page *)H_VMEMMAP_BASE; | |
911 | ioremap_bot = IOREMAP_BASE; | |
912 | ||
bfa37087 DS |
913 | #ifdef CONFIG_PCI |
914 | pci_io_base = ISA_IO_BASE; | |
915 | #endif | |
916 | ||
166dd7d3 BH |
917 | /* Select appropriate backend */ |
918 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
919 | ps3_early_mm_init(); | |
920 | else if (firmware_has_feature(FW_FEATURE_LPAR)) | |
921 | hpte_init_lpar(); | |
922 | else | |
923 | hpte_init_native(); | |
924 | ||
757c74d2 | 925 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
926 | * of memory. Has to be done before SLB initialization as this is |
927 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
928 | */ |
929 | htab_initialize(); | |
930 | ||
56547411 | 931 | pr_info("Initializing hash mmu with SLB\n"); |
376af594 | 932 | /* Initialize SLB management */ |
13b3d13b | 933 | slb_initialize(); |
757c74d2 BH |
934 | } |
935 | ||
936 | #ifdef CONFIG_SMP | |
756d08d1 | 937 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
938 | { |
939 | /* Initialize hash table for that CPU */ | |
b5dcc609 AK |
940 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
941 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) | |
942 | mtspr(SPRN_SDR1, _SDR1); | |
943 | else | |
944 | mtspr(SPRN_PTCR, | |
945 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
946 | } | |
376af594 | 947 | /* Initialize SLB */ |
13b3d13b | 948 | slb_initialize(); |
799d6046 | 949 | } |
757c74d2 | 950 | #endif /* CONFIG_SMP */ |
799d6046 | 951 | |
1da177e4 LT |
952 | /* |
953 | * Called by asm hashtable.S for doing lazy icache flush | |
954 | */ | |
955 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
956 | { | |
957 | struct page *page; | |
958 | ||
76c8e25b BH |
959 | if (!pfn_valid(pte_pfn(pte))) |
960 | return pp; | |
961 | ||
1da177e4 LT |
962 | page = pte_page(pte); |
963 | ||
964 | /* page is dirty */ | |
965 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
966 | if (trap == 0x400) { | |
0895ecda | 967 | flush_dcache_icache_page(page); |
1da177e4 LT |
968 | set_bit(PG_arch_1, &page->flags); |
969 | } else | |
3c726f8d | 970 | pp |= HPTE_R_N; |
1da177e4 LT |
971 | } |
972 | return pp; | |
973 | } | |
974 | ||
3a8247cc | 975 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 976 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 977 | { |
7aa0727f AK |
978 | u64 lpsizes; |
979 | unsigned char *hpsizes; | |
980 | unsigned long index, mask_index; | |
3a8247cc PM |
981 | |
982 | if (addr < SLICE_LOW_TOP) { | |
2fc251a8 | 983 | lpsizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 984 | index = GET_LOW_SLICE_INDEX(addr); |
7aa0727f | 985 | return (lpsizes >> (index * 4)) & 0xF; |
3a8247cc | 986 | } |
2fc251a8 | 987 | hpsizes = get_paca()->mm_ctx_high_slices_psize; |
7aa0727f AK |
988 | index = GET_HIGH_SLICE_INDEX(addr); |
989 | mask_index = index & 0x1; | |
990 | return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF; | |
3a8247cc PM |
991 | } |
992 | ||
993 | #else | |
994 | unsigned int get_paca_psize(unsigned long addr) | |
995 | { | |
c33e54fa | 996 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
997 | } |
998 | #endif | |
999 | ||
721151d0 PM |
1000 | /* |
1001 | * Demote a segment to using 4k pages. | |
1002 | * For now this makes the whole process use 4k pages. | |
1003 | */ | |
721151d0 | 1004 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1005 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1006 | { |
3a8247cc | 1007 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1008 | return; |
3a8247cc | 1009 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1010 | copro_flush_all_slbs(mm); |
a1dca346 | 1011 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
c395465d MN |
1012 | |
1013 | copy_mm_to_paca(&mm->context); | |
fa28237c PM |
1014 | slb_flush_and_rebolt(); |
1015 | } | |
721151d0 | 1016 | } |
16f1c746 | 1017 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1018 | |
fa28237c PM |
1019 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1020 | /* | |
1021 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1022 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1023 | * | |
1024 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1025 | * _PAGE_RWX: no access. |
fa28237c | 1026 | */ |
d28513bc | 1027 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1028 | { |
d28513bc | 1029 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
1030 | u32 spp = 0; |
1031 | u32 **sbpm, *sbpp; | |
1032 | ||
1033 | if (ea >= spt->maxaddr) | |
1034 | return 0; | |
b0d436c7 | 1035 | if (ea < 0x100000000UL) { |
fa28237c PM |
1036 | /* addresses below 4GB use spt->low_prot */ |
1037 | sbpm = spt->low_prot; | |
1038 | } else { | |
1039 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1040 | if (!sbpm) | |
1041 | return 0; | |
1042 | } | |
1043 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1044 | if (!sbpp) | |
1045 | return 0; | |
1046 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1047 | ||
1048 | /* extract 2-bit bitfield for this 4k subpage */ | |
1049 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1050 | ||
73a1441a AK |
1051 | /* |
1052 | * 0 -> full premission | |
1053 | * 1 -> Read only | |
1054 | * 2 -> no access. | |
1055 | * We return the flag that need to be cleared. | |
1056 | */ | |
1057 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1058 | return spp; |
1059 | } | |
1060 | ||
1061 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1062 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1063 | { |
1064 | return 0; | |
1065 | } | |
1066 | #endif | |
1067 | ||
4b8692c0 BH |
1068 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1069 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1070 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1071 | { |
1072 | if (!printk_ratelimit()) | |
1073 | return; | |
1074 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1075 | ea, access, current->comm); | |
d8139ebf AK |
1076 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1077 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1078 | } |
1079 | ||
09567e7f ME |
1080 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1081 | int psize, bool user_region) | |
1082 | { | |
1083 | if (user_region) { | |
1084 | if (psize != get_paca_psize(ea)) { | |
c395465d | 1085 | copy_mm_to_paca(&mm->context); |
09567e7f ME |
1086 | slb_flush_and_rebolt(); |
1087 | } | |
1088 | } else if (get_paca()->vmalloc_sllp != | |
1089 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1090 | get_paca()->vmalloc_sllp = | |
1091 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1092 | slb_vmalloc_update(); | |
1093 | } | |
1094 | } | |
1095 | ||
1da177e4 LT |
1096 | /* Result code is: |
1097 | * 0 - handled | |
1098 | * 1 - normal page fault | |
1099 | * -1 - critical hash insertion error | |
fa28237c | 1100 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1101 | */ |
aefa5688 AK |
1102 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1103 | unsigned long access, unsigned long trap, | |
1104 | unsigned long flags) | |
1da177e4 | 1105 | { |
891121e6 | 1106 | bool is_thp; |
ba12eede | 1107 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1108 | pgd_t *pgdir; |
1da177e4 | 1109 | unsigned long vsid; |
1da177e4 | 1110 | pte_t *ptep; |
a4fe3ce7 | 1111 | unsigned hugeshift; |
56aa4129 | 1112 | const struct cpumask *tmp; |
aefa5688 | 1113 | int rc, user_region = 0; |
1189be65 | 1114 | int psize, ssize; |
1da177e4 | 1115 | |
3c726f8d BH |
1116 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1117 | ea, access, trap); | |
cfcb3d80 | 1118 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1119 | |
3c726f8d | 1120 | /* Get region & vsid */ |
1da177e4 LT |
1121 | switch (REGION_ID(ea)) { |
1122 | case USER_REGION_ID: | |
1123 | user_region = 1; | |
3c726f8d BH |
1124 | if (! mm) { |
1125 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1126 | rc = 1; |
1127 | goto bail; | |
3c726f8d | 1128 | } |
16c2d476 | 1129 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
1130 | ssize = user_segment_size(ea); |
1131 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 1132 | break; |
1da177e4 | 1133 | case VMALLOC_REGION_ID: |
1189be65 | 1134 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1135 | if (ea < VMALLOC_END) |
1136 | psize = mmu_vmalloc_psize; | |
1137 | else | |
1138 | psize = mmu_io_psize; | |
1189be65 | 1139 | ssize = mmu_kernel_ssize; |
1da177e4 | 1140 | break; |
1da177e4 LT |
1141 | default: |
1142 | /* Not a valid range | |
1143 | * Send the problem up to do_page_fault | |
1144 | */ | |
ba12eede LZ |
1145 | rc = 1; |
1146 | goto bail; | |
1da177e4 | 1147 | } |
3c726f8d | 1148 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1149 | |
c60ac569 AK |
1150 | /* Bad address. */ |
1151 | if (!vsid) { | |
1152 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1153 | rc = 1; |
1154 | goto bail; | |
c60ac569 | 1155 | } |
3c726f8d | 1156 | /* Get pgdir */ |
1da177e4 | 1157 | pgdir = mm->pgd; |
ba12eede LZ |
1158 | if (pgdir == NULL) { |
1159 | rc = 1; | |
1160 | goto bail; | |
1161 | } | |
1da177e4 | 1162 | |
3c726f8d | 1163 | /* Check CPU locality */ |
56aa4129 RR |
1164 | tmp = cpumask_of(smp_processor_id()); |
1165 | if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) | |
aefa5688 | 1166 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1167 | |
16c2d476 | 1168 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1169 | /* If we use 4K pages and our psize is not 4K, then we might |
1170 | * be hitting a special driver mapping, and need to align the | |
1171 | * address before we fetch the PTE. | |
1172 | * | |
1173 | * It could also be a hugepage mapping, in which case this is | |
1174 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1175 | */ |
1176 | if (psize != MMU_PAGE_4K) | |
1177 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1178 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1179 | ||
3c726f8d | 1180 | /* Get PTE and page size from page tables */ |
891121e6 | 1181 | ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1182 | if (ptep == NULL || !pte_present(*ptep)) { |
1183 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1184 | rc = 1; |
1185 | goto bail; | |
3c726f8d BH |
1186 | } |
1187 | ||
ca91e6c0 BH |
1188 | /* Add _PAGE_PRESENT to the required access perm */ |
1189 | access |= _PAGE_PRESENT; | |
1190 | ||
1191 | /* Pre-check access permissions (will be re-checked atomically | |
1192 | * in __hash_page_XX but this pre-check is a fast path | |
1193 | */ | |
ac29c640 | 1194 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1195 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1196 | rc = 1; |
1197 | goto bail; | |
ca91e6c0 BH |
1198 | } |
1199 | ||
ba12eede | 1200 | if (hugeshift) { |
891121e6 | 1201 | if (is_thp) |
6d492ecc | 1202 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1203 | trap, flags, ssize, psize); |
6d492ecc AK |
1204 | #ifdef CONFIG_HUGETLB_PAGE |
1205 | else | |
1206 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1207 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1208 | #else |
1209 | else { | |
1210 | /* | |
1211 | * if we have hugeshift, and is not transhuge with | |
1212 | * hugetlb disabled, something is really wrong. | |
1213 | */ | |
1214 | rc = 1; | |
1215 | WARN_ON(1); | |
1216 | } | |
1217 | #endif | |
a1dca346 IM |
1218 | if (current->mm == mm) |
1219 | check_paca_psize(ea, mm, psize, user_region); | |
09567e7f | 1220 | |
ba12eede LZ |
1221 | goto bail; |
1222 | } | |
a4fe3ce7 | 1223 | |
3c726f8d BH |
1224 | #ifndef CONFIG_PPC_64K_PAGES |
1225 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1226 | #else | |
1227 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1228 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1229 | #endif | |
3c726f8d | 1230 | /* Do actual hashing */ |
16c2d476 | 1231 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1232 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1233 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1234 | demote_segment_4k(mm, ea); |
1235 | psize = MMU_PAGE_4K; | |
1236 | } | |
1237 | ||
16f1c746 BH |
1238 | /* If this PTE is non-cacheable and we have restrictions on |
1239 | * using non cacheable large pages, then we switch to 4k | |
1240 | */ | |
30bda41a | 1241 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1242 | if (user_region) { |
1243 | demote_segment_4k(mm, ea); | |
1244 | psize = MMU_PAGE_4K; | |
1245 | } else if (ea < VMALLOC_END) { | |
1246 | /* | |
1247 | * some driver did a non-cacheable mapping | |
1248 | * in vmalloc space, so switch vmalloc | |
1249 | * to 4k pages | |
1250 | */ | |
1251 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1252 | "to 4kB pages because of " | |
1253 | "non-cacheable mapping\n"); | |
1254 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1255 | copro_flush_all_slbs(mm); |
bf72aeba | 1256 | } |
16f1c746 | 1257 | } |
09567e7f | 1258 | |
0863d7f2 AK |
1259 | #endif /* CONFIG_PPC_64K_PAGES */ |
1260 | ||
a1dca346 IM |
1261 | if (current->mm == mm) |
1262 | check_paca_psize(ea, mm, psize, user_region); | |
16f1c746 | 1263 | |
73b341ef | 1264 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1265 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1266 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1267 | flags, ssize); | |
3c726f8d | 1268 | else |
73b341ef | 1269 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1270 | { |
a1128f8f | 1271 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1272 | if (access & spp) |
1273 | rc = -2; | |
1274 | else | |
1275 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1276 | flags, ssize, spp); |
fa28237c | 1277 | } |
3c726f8d | 1278 | |
4b8692c0 BH |
1279 | /* Dump some info in case of hash insertion failure, they should |
1280 | * never happen so it is really useful to know if/when they do | |
1281 | */ | |
1282 | if (rc == -1) | |
1283 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1284 | psize, pte_val(*ptep)); |
3c726f8d BH |
1285 | #ifndef CONFIG_PPC_64K_PAGES |
1286 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1287 | #else | |
1288 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1289 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1290 | #endif | |
1291 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1292 | |
1293 | bail: | |
1294 | exception_exit(prev_state); | |
3c726f8d | 1295 | return rc; |
1da177e4 | 1296 | } |
a1dca346 IM |
1297 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1298 | ||
aefa5688 AK |
1299 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1300 | unsigned long dsisr) | |
a1dca346 | 1301 | { |
aefa5688 | 1302 | unsigned long flags = 0; |
a1dca346 IM |
1303 | struct mm_struct *mm = current->mm; |
1304 | ||
1305 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1306 | mm = &init_mm; | |
1307 | ||
aefa5688 AK |
1308 | if (dsisr & DSISR_NOHPTE) |
1309 | flags |= HPTE_NOHPTE_UPDATE; | |
1310 | ||
1311 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1312 | } |
67207b96 | 1313 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1314 | |
106713a1 AK |
1315 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1316 | unsigned long dsisr) | |
1317 | { | |
c7d54842 | 1318 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1319 | unsigned long flags = 0; |
1320 | struct mm_struct *mm = current->mm; | |
1321 | ||
1322 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1323 | mm = &init_mm; | |
1324 | ||
1325 | if (dsisr & DSISR_NOHPTE) | |
1326 | flags |= HPTE_NOHPTE_UPDATE; | |
1327 | ||
1328 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1329 | access |= _PAGE_WRITE; |
106713a1 | 1330 | /* |
ac29c640 AK |
1331 | * We set _PAGE_PRIVILEGED only when |
1332 | * kernel mode access kernel space. | |
1333 | * | |
1334 | * _PAGE_PRIVILEGED is NOT set | |
1335 | * 1) when kernel mode access user space | |
1336 | * 2) user space access kernel space. | |
106713a1 | 1337 | */ |
ac29c640 | 1338 | access |= _PAGE_PRIVILEGED; |
106713a1 | 1339 | if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID)) |
ac29c640 | 1340 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1341 | |
1342 | if (trap == 0x400) | |
1343 | access |= _PAGE_EXEC; | |
1344 | ||
1345 | return hash_page_mm(mm, ea, access, trap, flags); | |
1346 | } | |
1347 | ||
8bbc9b7b ME |
1348 | #ifdef CONFIG_PPC_MM_SLICES |
1349 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1350 | { | |
aac55d75 ME |
1351 | int psize = get_slice_psize(mm, ea); |
1352 | ||
8bbc9b7b | 1353 | /* We only prefault standard pages for now */ |
aac55d75 ME |
1354 | if (unlikely(psize != mm->context.user_psize)) |
1355 | return false; | |
1356 | ||
1357 | /* | |
1358 | * Don't prefault if subpage protection is enabled for the EA. | |
1359 | */ | |
1360 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1361 | return false; |
1362 | ||
1363 | return true; | |
1364 | } | |
1365 | #else | |
1366 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1367 | { | |
1368 | return true; | |
1369 | } | |
1370 | #endif | |
1371 | ||
3c726f8d BH |
1372 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1373 | unsigned long access, unsigned long trap) | |
1da177e4 | 1374 | { |
12bc9f6f | 1375 | int hugepage_shift; |
3c726f8d | 1376 | unsigned long vsid; |
0b97fee0 | 1377 | pgd_t *pgdir; |
3c726f8d | 1378 | pte_t *ptep; |
3c726f8d | 1379 | unsigned long flags; |
aefa5688 | 1380 | int rc, ssize, update_flags = 0; |
3c726f8d | 1381 | |
d0f13e3c BH |
1382 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1383 | ||
8bbc9b7b | 1384 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1385 | return; |
1386 | ||
1387 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1388 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1389 | |
16f1c746 | 1390 | /* Get Linux PTE if available */ |
3c726f8d BH |
1391 | pgdir = mm->pgd; |
1392 | if (pgdir == NULL) | |
1393 | return; | |
0ac52dd7 AK |
1394 | |
1395 | /* Get VSID */ | |
1396 | ssize = user_segment_size(ea); | |
1397 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1398 | if (!vsid) | |
1399 | return; | |
1400 | /* | |
1401 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1402 | * saves us from holding multiple locks. | |
1403 | */ | |
1404 | local_irq_save(flags); | |
1405 | ||
12bc9f6f AK |
1406 | /* |
1407 | * THP pages use update_mmu_cache_pmd. We don't do | |
1408 | * hash preload there. Hence can ignore THP here | |
1409 | */ | |
891121e6 | 1410 | ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1411 | if (!ptep) |
0ac52dd7 | 1412 | goto out_exit; |
16f1c746 | 1413 | |
12bc9f6f | 1414 | WARN_ON(hugepage_shift); |
16f1c746 | 1415 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1416 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1417 | * a 64K kernel), then we don't preload, hash_page() will take |
1418 | * care of it once we actually try to access the page. | |
1419 | * That way we don't have to duplicate all of the logic for segment | |
1420 | * page size demotion here | |
1421 | */ | |
945537df | 1422 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1423 | goto out_exit; |
16f1c746 BH |
1424 | #endif /* CONFIG_PPC_64K_PAGES */ |
1425 | ||
16c2d476 | 1426 | /* Is that local to this CPU ? */ |
56aa4129 | 1427 | if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) |
aefa5688 | 1428 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1429 | |
1430 | /* Hash it in */ | |
73b341ef | 1431 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1432 | if (mm->context.user_psize == MMU_PAGE_64K) |
aefa5688 AK |
1433 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1434 | update_flags, ssize); | |
1da177e4 | 1435 | else |
73b341ef | 1436 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1437 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1438 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1439 | |
1440 | /* Dump some info in case of hash insertion failure, they should | |
1441 | * never happen so it is really useful to know if/when they do | |
1442 | */ | |
1443 | if (rc == -1) | |
1444 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1445 | mm->context.user_psize, |
1446 | mm->context.user_psize, | |
1447 | pte_val(*ptep)); | |
0ac52dd7 | 1448 | out_exit: |
3c726f8d BH |
1449 | local_irq_restore(flags); |
1450 | } | |
1451 | ||
f6ab0b92 BH |
1452 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1453 | * do not forget to update the assembly call site ! | |
1454 | */ | |
5524a27d | 1455 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1456 | unsigned long flags) |
3c726f8d BH |
1457 | { |
1458 | unsigned long hash, index, shift, hidx, slot; | |
aefa5688 | 1459 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1460 | |
5524a27d AK |
1461 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1462 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
1463 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
1464 | hidx = __rpte_to_hidx(pte, index); |
1465 | if (hidx & _PTEIDX_SECONDARY) | |
1466 | hash = ~hash; | |
1467 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1468 | slot += hidx & _PTEIDX_GROUP_IX; | |
5c339919 | 1469 | DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx); |
db3d8534 AK |
1470 | /* |
1471 | * We use same base page size and actual psize, because we don't | |
1472 | * use these functions for hugepage | |
1473 | */ | |
1474 | ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local); | |
3c726f8d | 1475 | } pte_iterate_hashed_end(); |
bc2a9408 MN |
1476 | |
1477 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1478 | /* Transactions are not aborted by tlbiel, only tlbie. | |
1479 | * Without, syncing a page back to a block device w/ PIO could pick up | |
1480 | * transactional data (bad!) so we force an abort here. Before the | |
1481 | * sync the page will be made read-only, which will flush_hash_page. | |
1482 | * BIG ISSUE here: if the kernel uses a page from userspace without | |
1483 | * unmapping it first, it may see the speculated version. | |
1484 | */ | |
1485 | if (local && cpu_has_feature(CPU_FTR_TM) && | |
c2fd22df | 1486 | current->thread.regs && |
bc2a9408 MN |
1487 | MSR_TM_ACTIVE(current->thread.regs->msr)) { |
1488 | tm_enable(); | |
1489 | tm_abort(TM_CAUSE_TLBI); | |
1490 | } | |
1491 | #endif | |
1da177e4 LT |
1492 | } |
1493 | ||
f1581bf1 AK |
1494 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1495 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1496 | pmd_t *pmdp, unsigned int psize, int ssize, |
1497 | unsigned long flags) | |
f1581bf1 AK |
1498 | { |
1499 | int i, max_hpte_count, valid; | |
1500 | unsigned long s_addr; | |
1501 | unsigned char *hpte_slot_array; | |
1502 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1503 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1504 | |
1505 | s_addr = addr & HPAGE_PMD_MASK; | |
1506 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1507 | /* | |
1508 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1509 | * we will find the below NULL. This happens when we do | |
1510 | * split_huge_page_pmd | |
1511 | */ | |
1512 | if (!hpte_slot_array) | |
1513 | return; | |
1514 | ||
d557b098 AK |
1515 | if (ppc_md.hugepage_invalidate) { |
1516 | ppc_md.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1517 | psize, ssize, local); | |
1518 | goto tm_abort; | |
1519 | } | |
f1581bf1 AK |
1520 | /* |
1521 | * No bluk hpte removal support, invalidate each entry | |
1522 | */ | |
1523 | shift = mmu_psize_defs[psize].shift; | |
1524 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1525 | for (i = 0; i < max_hpte_count; i++) { | |
1526 | /* | |
1527 | * 8 bits per each hpte entries | |
1528 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1529 | */ | |
1530 | valid = hpte_valid(hpte_slot_array, i); | |
1531 | if (!valid) | |
1532 | continue; | |
1533 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1534 | ||
1535 | /* get the vpn */ | |
1536 | addr = s_addr + (i * (1ul << shift)); | |
1537 | vpn = hpt_vpn(addr, vsid, ssize); | |
1538 | hash = hpt_hash(vpn, shift, ssize); | |
1539 | if (hidx & _PTEIDX_SECONDARY) | |
1540 | hash = ~hash; | |
1541 | ||
1542 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1543 | slot += hidx & _PTEIDX_GROUP_IX; | |
1544 | ppc_md.hpte_invalidate(slot, vpn, psize, | |
d557b098 AK |
1545 | MMU_PAGE_16M, ssize, local); |
1546 | } | |
1547 | tm_abort: | |
1548 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1549 | /* Transactions are not aborted by tlbiel, only tlbie. | |
1550 | * Without, syncing a page back to a block device w/ PIO could pick up | |
1551 | * transactional data (bad!) so we force an abort here. Before the | |
1552 | * sync the page will be made read-only, which will flush_hash_page. | |
1553 | * BIG ISSUE here: if the kernel uses a page from userspace without | |
1554 | * unmapping it first, it may see the speculated version. | |
1555 | */ | |
1556 | if (local && cpu_has_feature(CPU_FTR_TM) && | |
1557 | current->thread.regs && | |
1558 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1559 | tm_enable(); | |
1560 | tm_abort(TM_CAUSE_TLBI); | |
f1581bf1 | 1561 | } |
d557b098 | 1562 | #endif |
2e826695 | 1563 | return; |
f1581bf1 AK |
1564 | } |
1565 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1566 | ||
61b1a942 | 1567 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1568 | { |
3c726f8d | 1569 | if (ppc_md.flush_hash_range) |
61b1a942 | 1570 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 1571 | else { |
1da177e4 | 1572 | int i; |
61b1a942 | 1573 | struct ppc64_tlb_batch *batch = |
69111bac | 1574 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1575 | |
1576 | for (i = 0; i < number; i++) | |
5524a27d | 1577 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1578 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1579 | } |
1580 | } | |
1581 | ||
1da177e4 LT |
1582 | /* |
1583 | * low_hash_fault is called when we the low level hash code failed | |
1584 | * to instert a PTE due to an hypervisor error | |
1585 | */ | |
fa28237c | 1586 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1587 | { |
ba12eede LZ |
1588 | enum ctx_state prev_state = exception_enter(); |
1589 | ||
1da177e4 | 1590 | if (user_mode(regs)) { |
fa28237c PM |
1591 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1592 | if (rc == -2) | |
1593 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1594 | else | |
1595 | #endif | |
1596 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1597 | } else | |
1598 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1599 | |
1600 | exception_exit(prev_state); | |
1da177e4 | 1601 | } |
370a908d | 1602 | |
b170bd3d LZ |
1603 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1604 | unsigned long pa, unsigned long rflags, | |
1605 | unsigned long vflags, int psize, int ssize) | |
1606 | { | |
1607 | unsigned long hpte_group; | |
1608 | long slot; | |
1609 | ||
1610 | repeat: | |
1611 | hpte_group = ((hash & htab_hash_mask) * | |
1612 | HPTES_PER_GROUP) & ~0x7UL; | |
1613 | ||
1614 | /* Insert into the hash table, primary slot */ | |
1615 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags, | |
b1022fbd | 1616 | psize, psize, ssize); |
b170bd3d LZ |
1617 | |
1618 | /* Primary is full, try the secondary */ | |
1619 | if (unlikely(slot == -1)) { | |
1620 | hpte_group = ((~hash & htab_hash_mask) * | |
1621 | HPTES_PER_GROUP) & ~0x7UL; | |
1622 | slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, | |
1623 | vflags | HPTE_V_SECONDARY, | |
b1022fbd | 1624 | psize, psize, ssize); |
b170bd3d LZ |
1625 | if (slot == -1) { |
1626 | if (mftb() & 0x1) | |
1627 | hpte_group = ((hash & htab_hash_mask) * | |
1628 | HPTES_PER_GROUP)&~0x7UL; | |
1629 | ||
1630 | ppc_md.hpte_remove(hpte_group); | |
1631 | goto repeat; | |
1632 | } | |
1633 | } | |
1634 | ||
1635 | return slot; | |
1636 | } | |
1637 | ||
370a908d BH |
1638 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1639 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1640 | { | |
016af59f | 1641 | unsigned long hash; |
1189be65 | 1642 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1643 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1644 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1645 | long ret; |
370a908d | 1646 | |
5524a27d | 1647 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1648 | |
c60ac569 AK |
1649 | /* Don't create HPTE entries for bad address */ |
1650 | if (!vsid) | |
1651 | return; | |
016af59f LZ |
1652 | |
1653 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1654 | HPTE_V_BOLTED, | |
1655 | mmu_linear_psize, mmu_kernel_ssize); | |
1656 | ||
370a908d BH |
1657 | BUG_ON (ret < 0); |
1658 | spin_lock(&linear_map_hash_lock); | |
1659 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1660 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1661 | spin_unlock(&linear_map_hash_lock); | |
1662 | } | |
1663 | ||
1664 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1665 | { | |
1189be65 PM |
1666 | unsigned long hash, hidx, slot; |
1667 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1668 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1669 | |
5524a27d | 1670 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1671 | spin_lock(&linear_map_hash_lock); |
1672 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1673 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1674 | linear_map_hash_slots[lmi] = 0; | |
1675 | spin_unlock(&linear_map_hash_lock); | |
1676 | if (hidx & _PTEIDX_SECONDARY) | |
1677 | hash = ~hash; | |
1678 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1679 | slot += hidx & _PTEIDX_GROUP_IX; | |
db3d8534 AK |
1680 | ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize, |
1681 | mmu_kernel_ssize, 0); | |
370a908d BH |
1682 | } |
1683 | ||
031bc574 | 1684 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1685 | { |
1686 | unsigned long flags, vaddr, lmi; | |
1687 | int i; | |
1688 | ||
1689 | local_irq_save(flags); | |
1690 | for (i = 0; i < numpages; i++, page++) { | |
1691 | vaddr = (unsigned long)page_address(page); | |
1692 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1693 | if (lmi >= linear_map_hash_count) | |
1694 | continue; | |
1695 | if (enable) | |
1696 | kernel_map_linear_page(vaddr, lmi); | |
1697 | else | |
1698 | kernel_unmap_linear_page(vaddr, lmi); | |
1699 | } | |
1700 | local_irq_restore(flags); | |
1701 | } | |
1702 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1703 | |
756d08d1 | 1704 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1705 | phys_addr_t first_memblock_size) |
1706 | { | |
1707 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1708 | * physical on those processors | |
1709 | */ | |
1710 | BUG_ON(first_memblock_base != 0); | |
1711 | ||
1712 | /* On LPAR systems, the first entry is our RMA region, | |
1713 | * non-LPAR 64-bit hash MMU systems don't have a limitation | |
1714 | * on real mode access, but using the first entry works well | |
1715 | * enough. We also clamp it to 1G to avoid some funky things | |
1716 | * such as RTAS bugs etc... | |
1717 | */ | |
1718 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
1719 | ||
1720 | /* Finally limit subsequent allocations */ | |
1721 | memblock_set_current_limit(ppc64_rma_size); | |
1722 | } |