Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
7f142661 | 24 | #define pr_fmt(fmt) "hash-mmu: " fmt |
1da177e4 LT |
25 | #include <linux/spinlock.h> |
26 | #include <linux/errno.h> | |
589ee628 | 27 | #include <linux/sched/mm.h> |
1da177e4 LT |
28 | #include <linux/proc_fs.h> |
29 | #include <linux/stat.h> | |
30 | #include <linux/sysctl.h> | |
66b15db6 | 31 | #include <linux/export.h> |
1da177e4 LT |
32 | #include <linux/ctype.h> |
33 | #include <linux/cache.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/signal.h> | |
95f72d1e | 36 | #include <linux/memblock.h> |
ba12eede | 37 | #include <linux/context_tracking.h> |
5556ecf5 | 38 | #include <linux/libfdt.h> |
92e3da3c | 39 | #include <linux/pkeys.h> |
1da177e4 | 40 | |
7644d581 | 41 | #include <asm/debugfs.h> |
1da177e4 LT |
42 | #include <asm/processor.h> |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/mmu.h> | |
45 | #include <asm/mmu_context.h> | |
46 | #include <asm/page.h> | |
47 | #include <asm/types.h> | |
7c0f6ba6 | 48 | #include <linux/uaccess.h> |
1da177e4 | 49 | #include <asm/machdep.h> |
d9b2b2a2 | 50 | #include <asm/prom.h> |
1da177e4 LT |
51 | #include <asm/tlbflush.h> |
52 | #include <asm/io.h> | |
53 | #include <asm/eeh.h> | |
54 | #include <asm/tlb.h> | |
55 | #include <asm/cacheflush.h> | |
56 | #include <asm/cputable.h> | |
1da177e4 | 57 | #include <asm/sections.h> |
be3ebfe8 | 58 | #include <asm/copro.h> |
aa39be09 | 59 | #include <asm/udbg.h> |
b68a70c4 | 60 | #include <asm/code-patching.h> |
3ccc00a7 | 61 | #include <asm/fadump.h> |
f5339277 | 62 | #include <asm/firmware.h> |
bc2a9408 | 63 | #include <asm/tm.h> |
cfcb3d80 | 64 | #include <asm/trace.h> |
166dd7d3 | 65 | #include <asm/ps3.h> |
94171b19 | 66 | #include <asm/pte-walk.h> |
eacbb218 | 67 | #include <asm/asm-prototypes.h> |
1da177e4 LT |
68 | |
69 | #ifdef DEBUG | |
70 | #define DBG(fmt...) udbg_printf(fmt) | |
71 | #else | |
72 | #define DBG(fmt...) | |
73 | #endif | |
74 | ||
3c726f8d BH |
75 | #ifdef DEBUG_LOW |
76 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
77 | #else | |
78 | #define DBG_LOW(fmt...) | |
79 | #endif | |
80 | ||
81 | #define KB (1024) | |
82 | #define MB (1024*KB) | |
658013e9 | 83 | #define GB (1024L*MB) |
3c726f8d | 84 | |
1da177e4 LT |
85 | /* |
86 | * Note: pte --> Linux PTE | |
87 | * HPTE --> PowerPC Hashed Page Table Entry | |
88 | * | |
89 | * Execution context: | |
90 | * htab_initialize is called with the MMU off (of course), but | |
91 | * the kernel has been copied down to zero so it can directly | |
92 | * reference global data. At this point it is very difficult | |
93 | * to print debug info. | |
94 | * | |
95 | */ | |
96 | ||
799d6046 PM |
97 | static unsigned long _SDR1; |
98 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
e1802b06 | 99 | EXPORT_SYMBOL_GPL(mmu_psize_defs); |
799d6046 | 100 | |
0eeede0c PM |
101 | u8 hpte_page_sizes[1 << LP_BITS]; |
102 | EXPORT_SYMBOL_GPL(hpte_page_sizes); | |
103 | ||
8e561e7e | 104 | struct hash_pte *htab_address; |
337a7128 | 105 | unsigned long htab_size_bytes; |
96e28449 | 106 | unsigned long htab_hash_mask; |
4ab79aa8 | 107 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d | 108 | int mmu_linear_psize = MMU_PAGE_4K; |
8ca7a82f | 109 | EXPORT_SYMBOL_GPL(mmu_linear_psize); |
3c726f8d | 110 | int mmu_virtual_psize = MMU_PAGE_4K; |
bf72aeba | 111 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
112 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
113 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
114 | #endif | |
bf72aeba | 115 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 | 116 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
8ca7a82f | 117 | EXPORT_SYMBOL_GPL(mmu_kernel_ssize); |
1189be65 | 118 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; |
584f8b71 | 119 | u16 mmu_slb_size = 64; |
4ab79aa8 | 120 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
121 | #ifdef CONFIG_PPC_64K_PAGES |
122 | int mmu_ci_restrictions; | |
123 | #endif | |
370a908d BH |
124 | #ifdef CONFIG_DEBUG_PAGEALLOC |
125 | static u8 *linear_map_hash_slots; | |
126 | static unsigned long linear_map_hash_count; | |
ed166692 | 127 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 128 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
7025776e BH |
129 | struct mmu_hash_ops mmu_hash_ops; |
130 | EXPORT_SYMBOL(mmu_hash_ops); | |
1da177e4 | 131 | |
3c726f8d BH |
132 | /* There are definitions of page sizes arrays to be used when none |
133 | * is provided by the firmware. | |
134 | */ | |
1da177e4 | 135 | |
471d7ff8 NP |
136 | /* |
137 | * Fallback (4k pages only) | |
3c726f8d | 138 | */ |
471d7ff8 | 139 | static struct mmu_psize_def mmu_psize_defaults[] = { |
3c726f8d BH |
140 | [MMU_PAGE_4K] = { |
141 | .shift = 12, | |
142 | .sllp = 0, | |
b1022fbd | 143 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
144 | .avpnm = 0, |
145 | .tlbiel = 0, | |
146 | }, | |
147 | }; | |
148 | ||
149 | /* POWER4, GPUL, POWER5 | |
150 | * | |
151 | * Support for 16Mb large pages | |
152 | */ | |
09de9ff8 | 153 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
154 | [MMU_PAGE_4K] = { |
155 | .shift = 12, | |
156 | .sllp = 0, | |
b1022fbd | 157 | .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1}, |
3c726f8d BH |
158 | .avpnm = 0, |
159 | .tlbiel = 1, | |
160 | }, | |
161 | [MMU_PAGE_16M] = { | |
162 | .shift = 24, | |
163 | .sllp = SLB_VSID_L, | |
b1022fbd AK |
164 | .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0, |
165 | [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 }, | |
3c726f8d BH |
166 | .avpnm = 0x1UL, |
167 | .tlbiel = 0, | |
168 | }, | |
169 | }; | |
170 | ||
dc47c0c1 AK |
171 | /* |
172 | * 'R' and 'C' update notes: | |
173 | * - Under pHyp or KVM, the updatepp path will not set C, thus it *will* | |
174 | * create writeable HPTEs without C set, because the hcall H_PROTECT | |
175 | * that we use in that case will not update C | |
176 | * - The above is however not a problem, because we also don't do that | |
177 | * fancy "no flush" variant of eviction and we use H_REMOVE which will | |
178 | * do the right thing and thus we don't have the race I described earlier | |
179 | * | |
180 | * - Under bare metal, we do have the race, so we need R and C set | |
181 | * - We make sure R is always set and never lost | |
182 | * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping | |
183 | */ | |
c6a3c495 | 184 | unsigned long htab_convert_pte_flags(unsigned long pteflags) |
bc033b63 | 185 | { |
c6a3c495 | 186 | unsigned long rflags = 0; |
bc033b63 BH |
187 | |
188 | /* _PAGE_EXEC -> NOEXEC */ | |
189 | if ((pteflags & _PAGE_EXEC) == 0) | |
190 | rflags |= HPTE_R_N; | |
c6a3c495 | 191 | /* |
e58e87ad | 192 | * PPP bits: |
1ec3f937 | 193 | * Linux uses slb key 0 for kernel and 1 for user. |
e58e87ad AK |
194 | * kernel RW areas are mapped with PPP=0b000 |
195 | * User area is mapped with PPP=0b010 for read/write | |
196 | * or PPP=0b011 for read-only (including writeable but clean pages). | |
bc033b63 | 197 | */ |
e58e87ad AK |
198 | if (pteflags & _PAGE_PRIVILEGED) { |
199 | /* | |
200 | * Kernel read only mapped with ppp bits 0b110 | |
201 | */ | |
984d7a1e AK |
202 | if (!(pteflags & _PAGE_WRITE)) { |
203 | if (mmu_has_feature(MMU_FTR_KERNEL_RO)) | |
204 | rflags |= (HPTE_R_PP0 | 0x2); | |
205 | else | |
206 | rflags |= 0x3; | |
207 | } | |
e58e87ad | 208 | } else { |
c7d54842 AK |
209 | if (pteflags & _PAGE_RWX) |
210 | rflags |= 0x2; | |
211 | if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY))) | |
c6a3c495 AK |
212 | rflags |= 0x1; |
213 | } | |
c8c06f5a | 214 | /* |
dc47c0c1 AK |
215 | * We can't allow hardware to update hpte bits. Hence always |
216 | * set 'R' bit and set 'C' if it is a write fault | |
c8c06f5a | 217 | */ |
e568006b | 218 | rflags |= HPTE_R_R; |
dc47c0c1 AK |
219 | |
220 | if (pteflags & _PAGE_DIRTY) | |
221 | rflags |= HPTE_R_C; | |
40e8550a AK |
222 | /* |
223 | * Add in WIG bits | |
224 | */ | |
30bda41a AK |
225 | |
226 | if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) | |
40e8550a | 227 | rflags |= HPTE_R_I; |
e568006b | 228 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT) |
30bda41a | 229 | rflags |= (HPTE_R_I | HPTE_R_G); |
e568006b AK |
230 | else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO) |
231 | rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M); | |
232 | else | |
233 | /* | |
234 | * Add memory coherence if cache inhibited is not set | |
235 | */ | |
236 | rflags |= HPTE_R_M; | |
40e8550a | 237 | |
a6590ca5 | 238 | rflags |= pte_to_hpte_pkey_bits(pteflags); |
40e8550a | 239 | return rflags; |
bc033b63 | 240 | } |
3c726f8d BH |
241 | |
242 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 243 | unsigned long pstart, unsigned long prot, |
1189be65 | 244 | int psize, int ssize) |
1da177e4 | 245 | { |
3c726f8d BH |
246 | unsigned long vaddr, paddr; |
247 | unsigned int step, shift; | |
3c726f8d | 248 | int ret = 0; |
1da177e4 | 249 | |
3c726f8d BH |
250 | shift = mmu_psize_defs[psize].shift; |
251 | step = 1 << shift; | |
1da177e4 | 252 | |
bc033b63 BH |
253 | prot = htab_convert_pte_flags(prot); |
254 | ||
255 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
256 | vstart, vend, pstart, prot, psize, ssize); | |
257 | ||
3c726f8d BH |
258 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
259 | vaddr += step, paddr += step) { | |
370a908d | 260 | unsigned long hash, hpteg; |
1189be65 | 261 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
5524a27d | 262 | unsigned long vpn = hpt_vpn(vaddr, vsid, ssize); |
9e88ba4e PM |
263 | unsigned long tprot = prot; |
264 | ||
c60ac569 AK |
265 | /* |
266 | * If we hit a bad address return error. | |
267 | */ | |
268 | if (!vsid) | |
269 | return -1; | |
9e88ba4e | 270 | /* Make kernel text executable */ |
549e8152 | 271 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 272 | tprot &= ~HPTE_R_N; |
1da177e4 | 273 | |
b18db0b8 AG |
274 | /* Make kvm guest trampolines executable */ |
275 | if (overlaps_kvm_tmp(vaddr, vaddr + step)) | |
276 | tprot &= ~HPTE_R_N; | |
277 | ||
429d2e83 MS |
278 | /* |
279 | * If relocatable, check if it overlaps interrupt vectors that | |
280 | * are copied down to real 0. For relocatable kernel | |
281 | * (e.g. kdump case) we copy interrupt vectors down to real | |
282 | * address 0. Mark that region as executable. This is | |
283 | * because on p8 system with relocation on exception feature | |
284 | * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence | |
285 | * in order to execute the interrupt handlers in virtual | |
286 | * mode the vector region need to be marked as executable. | |
287 | */ | |
288 | if ((PHYSICAL_START > MEMORY_START) && | |
289 | overlaps_interrupt_vector_text(vaddr, vaddr + step)) | |
290 | tprot &= ~HPTE_R_N; | |
291 | ||
5524a27d | 292 | hash = hpt_hash(vpn, shift, ssize); |
1da177e4 LT |
293 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
294 | ||
7025776e BH |
295 | BUG_ON(!mmu_hash_ops.hpte_insert); |
296 | ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot, | |
297 | HPTE_V_BOLTED, psize, psize, | |
298 | ssize); | |
c30a4df3 | 299 | |
3c726f8d BH |
300 | if (ret < 0) |
301 | break; | |
e7df0d88 | 302 | |
370a908d | 303 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
304 | if (debug_pagealloc_enabled() && |
305 | (paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
370a908d BH |
306 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; |
307 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
308 | } |
309 | return ret < 0 ? ret : 0; | |
310 | } | |
1da177e4 | 311 | |
ed5694a8 | 312 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
313 | int psize, int ssize) |
314 | { | |
315 | unsigned long vaddr; | |
316 | unsigned int step, shift; | |
27828f98 DG |
317 | int rc; |
318 | int ret = 0; | |
f8c8803b BP |
319 | |
320 | shift = mmu_psize_defs[psize].shift; | |
321 | step = 1 << shift; | |
322 | ||
7025776e | 323 | if (!mmu_hash_ops.hpte_removebolted) |
abd0a0e7 | 324 | return -ENODEV; |
f8c8803b | 325 | |
27828f98 | 326 | for (vaddr = vstart; vaddr < vend; vaddr += step) { |
7025776e | 327 | rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize); |
27828f98 DG |
328 | if (rc == -ENOENT) { |
329 | ret = -ENOENT; | |
330 | continue; | |
331 | } | |
332 | if (rc < 0) | |
333 | return rc; | |
334 | } | |
52db9b44 | 335 | |
27828f98 | 336 | return ret; |
f8c8803b BP |
337 | } |
338 | ||
faf78829 OH |
339 | static bool disable_1tb_segments = false; |
340 | ||
341 | static int __init parse_disable_1tb_segments(char *p) | |
342 | { | |
343 | disable_1tb_segments = true; | |
344 | return 0; | |
345 | } | |
346 | early_param("disable_1tb_segments", parse_disable_1tb_segments); | |
347 | ||
1189be65 PM |
348 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
349 | const char *uname, int depth, | |
350 | void *data) | |
351 | { | |
9d0c4dfe RH |
352 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
353 | const __be32 *prop; | |
354 | int size = 0; | |
1189be65 PM |
355 | |
356 | /* We are scanning "cpu" nodes only */ | |
357 | if (type == NULL || strcmp(type, "cpu") != 0) | |
358 | return 0; | |
359 | ||
12f04f2b | 360 | prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size); |
1189be65 PM |
361 | if (prop == NULL) |
362 | return 0; | |
363 | for (; size >= 4; size -= 4, ++prop) { | |
12f04f2b | 364 | if (be32_to_cpu(prop[0]) == 40) { |
1189be65 | 365 | DBG("1T segment support detected\n"); |
faf78829 OH |
366 | |
367 | if (disable_1tb_segments) { | |
368 | DBG("1T segments disabled by command line\n"); | |
369 | break; | |
370 | } | |
371 | ||
44ae3ab3 | 372 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 373 | return 1; |
1189be65 | 374 | } |
1189be65 | 375 | } |
44ae3ab3 | 376 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
377 | return 0; |
378 | } | |
379 | ||
b1022fbd AK |
380 | static int __init get_idx_from_shift(unsigned int shift) |
381 | { | |
382 | int idx = -1; | |
383 | ||
384 | switch (shift) { | |
385 | case 0xc: | |
386 | idx = MMU_PAGE_4K; | |
387 | break; | |
388 | case 0x10: | |
389 | idx = MMU_PAGE_64K; | |
390 | break; | |
391 | case 0x14: | |
392 | idx = MMU_PAGE_1M; | |
393 | break; | |
394 | case 0x18: | |
395 | idx = MMU_PAGE_16M; | |
396 | break; | |
397 | case 0x22: | |
398 | idx = MMU_PAGE_16G; | |
399 | break; | |
400 | } | |
401 | return idx; | |
402 | } | |
403 | ||
3c726f8d BH |
404 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
405 | const char *uname, int depth, | |
406 | void *data) | |
407 | { | |
9d0c4dfe RH |
408 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
409 | const __be32 *prop; | |
410 | int size = 0; | |
3c726f8d BH |
411 | |
412 | /* We are scanning "cpu" nodes only */ | |
413 | if (type == NULL || strcmp(type, "cpu") != 0) | |
414 | return 0; | |
415 | ||
12f04f2b | 416 | prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size); |
9e34992a ME |
417 | if (!prop) |
418 | return 0; | |
419 | ||
420 | pr_info("Page sizes from device-tree:\n"); | |
421 | size /= 4; | |
422 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); | |
423 | while(size > 0) { | |
424 | unsigned int base_shift = be32_to_cpu(prop[0]); | |
425 | unsigned int slbenc = be32_to_cpu(prop[1]); | |
426 | unsigned int lpnum = be32_to_cpu(prop[2]); | |
427 | struct mmu_psize_def *def; | |
428 | int idx, base_idx; | |
429 | ||
430 | size -= 3; prop += 3; | |
431 | base_idx = get_idx_from_shift(base_shift); | |
432 | if (base_idx < 0) { | |
433 | /* skip the pte encoding also */ | |
434 | prop += lpnum * 2; size -= lpnum * 2; | |
435 | continue; | |
436 | } | |
437 | def = &mmu_psize_defs[base_idx]; | |
438 | if (base_idx == MMU_PAGE_16M) | |
439 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; | |
440 | ||
441 | def->shift = base_shift; | |
442 | if (base_shift <= 23) | |
443 | def->avpnm = 0; | |
444 | else | |
445 | def->avpnm = (1 << (base_shift - 23)) - 1; | |
446 | def->sllp = slbenc; | |
447 | /* | |
448 | * We don't know for sure what's up with tlbiel, so | |
449 | * for now we only set it for 4K and 64K pages | |
450 | */ | |
451 | if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K) | |
452 | def->tlbiel = 1; | |
453 | else | |
454 | def->tlbiel = 0; | |
455 | ||
456 | while (size > 0 && lpnum) { | |
457 | unsigned int shift = be32_to_cpu(prop[0]); | |
458 | int penc = be32_to_cpu(prop[1]); | |
459 | ||
460 | prop += 2; size -= 2; | |
461 | lpnum--; | |
462 | ||
463 | idx = get_idx_from_shift(shift); | |
464 | if (idx < 0) | |
b1022fbd | 465 | continue; |
9e34992a ME |
466 | |
467 | if (penc == -1) | |
468 | pr_err("Invalid penc for base_shift=%d " | |
469 | "shift=%d\n", base_shift, shift); | |
470 | ||
471 | def->penc[idx] = penc; | |
472 | pr_info("base_shift=%d: shift=%d, sllp=0x%04lx," | |
473 | " avpnm=0x%08lx, tlbiel=%d, penc=%d\n", | |
474 | base_shift, shift, def->sllp, | |
475 | def->avpnm, def->tlbiel, def->penc[idx]); | |
1da177e4 | 476 | } |
3c726f8d | 477 | } |
9e34992a ME |
478 | |
479 | return 1; | |
3c726f8d BH |
480 | } |
481 | ||
e16a9c09 | 482 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
483 | /* Scan for 16G memory blocks that have been set aside for huge pages |
484 | * and reserve those blocks for 16G huge pages. | |
485 | */ | |
486 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
487 | const char *uname, int depth, | |
488 | void *data) { | |
9d0c4dfe RH |
489 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
490 | const __be64 *addr_prop; | |
491 | const __be32 *page_count_prop; | |
658013e9 JT |
492 | unsigned int expected_pages; |
493 | long unsigned int phys_addr; | |
494 | long unsigned int block_size; | |
495 | ||
496 | /* We are scanning "memory" nodes only */ | |
497 | if (type == NULL || strcmp(type, "memory") != 0) | |
498 | return 0; | |
499 | ||
500 | /* This property is the log base 2 of the number of virtual pages that | |
501 | * will represent this memory block. */ | |
502 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
503 | if (page_count_prop == NULL) | |
504 | return 0; | |
12f04f2b | 505 | expected_pages = (1 << be32_to_cpu(page_count_prop[0])); |
658013e9 JT |
506 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); |
507 | if (addr_prop == NULL) | |
508 | return 0; | |
12f04f2b AB |
509 | phys_addr = be64_to_cpu(addr_prop[0]); |
510 | block_size = be64_to_cpu(addr_prop[1]); | |
658013e9 JT |
511 | if (block_size != (16 * GB)) |
512 | return 0; | |
513 | printk(KERN_INFO "Huge page(16GB) memory: " | |
514 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
515 | phys_addr, block_size, expected_pages); | |
23493c12 | 516 | if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) { |
95f72d1e | 517 | memblock_reserve(phys_addr, block_size * expected_pages); |
79cc38de | 518 | pseries_add_gpage(phys_addr, block_size, expected_pages); |
4792adba | 519 | } |
658013e9 JT |
520 | return 0; |
521 | } | |
e16a9c09 | 522 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 523 | |
b1022fbd AK |
524 | static void mmu_psize_set_default_penc(void) |
525 | { | |
526 | int bpsize, apsize; | |
527 | for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) | |
528 | for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++) | |
529 | mmu_psize_defs[bpsize].penc[apsize] = -1; | |
530 | } | |
531 | ||
9048e648 AG |
532 | #ifdef CONFIG_PPC_64K_PAGES |
533 | ||
534 | static bool might_have_hea(void) | |
535 | { | |
536 | /* | |
537 | * The HEA ethernet adapter requires awareness of the | |
538 | * GX bus. Without that awareness we can easily assume | |
539 | * we will never see an HEA ethernet device. | |
540 | */ | |
541 | #ifdef CONFIG_IBMEBUS | |
2b4e3ad8 | 542 | return !cpu_has_feature(CPU_FTR_ARCH_207S) && |
08bf75ba | 543 | firmware_has_feature(FW_FEATURE_SPLPAR); |
9048e648 AG |
544 | #else |
545 | return false; | |
546 | #endif | |
547 | } | |
548 | ||
549 | #endif /* #ifdef CONFIG_PPC_64K_PAGES */ | |
550 | ||
bacf9cf8 | 551 | static void __init htab_scan_page_sizes(void) |
3c726f8d BH |
552 | { |
553 | int rc; | |
554 | ||
b1022fbd AK |
555 | /* se the invalid penc to -1 */ |
556 | mmu_psize_set_default_penc(); | |
557 | ||
3c726f8d | 558 | /* Default to 4K pages only */ |
471d7ff8 NP |
559 | memcpy(mmu_psize_defs, mmu_psize_defaults, |
560 | sizeof(mmu_psize_defaults)); | |
3c726f8d BH |
561 | |
562 | /* | |
563 | * Try to find the available page sizes in the device-tree | |
564 | */ | |
565 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
b8f1b4f8 | 566 | if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) { |
bacf9cf8 ME |
567 | /* |
568 | * Nothing in the device-tree, but the CPU supports 16M pages, | |
569 | * so let's fallback on a known size list for 16M capable CPUs. | |
570 | */ | |
3c726f8d BH |
571 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
572 | sizeof(mmu_psize_defaults_gp)); | |
bacf9cf8 ME |
573 | } |
574 | ||
575 | #ifdef CONFIG_HUGETLB_PAGE | |
85975387 HB |
576 | if (!hugetlb_disabled) { |
577 | /* Reserve 16G huge page memory sections for huge pages */ | |
578 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
579 | } | |
bacf9cf8 ME |
580 | #endif /* CONFIG_HUGETLB_PAGE */ |
581 | } | |
582 | ||
0eeede0c PM |
583 | /* |
584 | * Fill in the hpte_page_sizes[] array. | |
585 | * We go through the mmu_psize_defs[] array looking for all the | |
586 | * supported base/actual page size combinations. Each combination | |
587 | * has a unique pagesize encoding (penc) value in the low bits of | |
588 | * the LP field of the HPTE. For actual page sizes less than 1MB, | |
589 | * some of the upper LP bits are used for RPN bits, meaning that | |
590 | * we need to fill in several entries in hpte_page_sizes[]. | |
591 | * | |
592 | * In diagrammatic form, with r = RPN bits and z = page size bits: | |
593 | * PTE LP actual page size | |
594 | * rrrr rrrz >=8KB | |
595 | * rrrr rrzz >=16KB | |
596 | * rrrr rzzz >=32KB | |
597 | * rrrr zzzz >=64KB | |
598 | * ... | |
599 | * | |
600 | * The zzzz bits are implementation-specific but are chosen so that | |
601 | * no encoding for a larger page size uses the same value in its | |
602 | * low-order N bits as the encoding for the 2^(12+N) byte page size | |
603 | * (if it exists). | |
604 | */ | |
605 | static void init_hpte_page_sizes(void) | |
606 | { | |
607 | long int ap, bp; | |
608 | long int shift, penc; | |
609 | ||
610 | for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) { | |
611 | if (!mmu_psize_defs[bp].shift) | |
612 | continue; /* not a supported page size */ | |
613 | for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) { | |
614 | penc = mmu_psize_defs[bp].penc[ap]; | |
10527e80 | 615 | if (penc == -1 || !mmu_psize_defs[ap].shift) |
0eeede0c PM |
616 | continue; |
617 | shift = mmu_psize_defs[ap].shift - LP_SHIFT; | |
618 | if (shift <= 0) | |
619 | continue; /* should never happen */ | |
620 | /* | |
621 | * For page sizes less than 1MB, this loop | |
622 | * replicates the entry for all possible values | |
623 | * of the rrrr bits. | |
624 | */ | |
625 | while (penc < (1 << LP_BITS)) { | |
626 | hpte_page_sizes[penc] = (ap << 4) | bp; | |
627 | penc += 1 << shift; | |
628 | } | |
629 | } | |
630 | } | |
631 | } | |
632 | ||
bacf9cf8 ME |
633 | static void __init htab_init_page_sizes(void) |
634 | { | |
0eeede0c PM |
635 | init_hpte_page_sizes(); |
636 | ||
e7df0d88 JK |
637 | if (!debug_pagealloc_enabled()) { |
638 | /* | |
639 | * Pick a size for the linear mapping. Currently, we only | |
640 | * support 16M, 1M and 4K which is the default | |
641 | */ | |
642 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
643 | mmu_linear_psize = MMU_PAGE_16M; | |
644 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
645 | mmu_linear_psize = MMU_PAGE_1M; | |
646 | } | |
3c726f8d | 647 | |
bf72aeba | 648 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
649 | /* |
650 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
651 | * 64K for user mappings and vmalloc if supported by the processor. |
652 | * We only use 64k for ioremap if the processor | |
653 | * (and firmware) support cache-inhibited large pages. | |
654 | * If not, we use 4k and set mmu_ci_restrictions so that | |
655 | * hash_page knows to switch processes that use cache-inhibited | |
656 | * mappings to 4k pages. | |
3c726f8d | 657 | */ |
bf72aeba | 658 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 659 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 660 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
661 | if (mmu_linear_psize == MMU_PAGE_4K) |
662 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 663 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 | 664 | /* |
9048e648 AG |
665 | * When running on pSeries using 64k pages for ioremap |
666 | * would stop us accessing the HEA ethernet. So if we | |
667 | * have the chance of ever seeing one, stay at 4k. | |
cfe666b1 | 668 | */ |
2b4e3ad8 | 669 | if (!might_have_hea()) |
cfe666b1 PM |
670 | mmu_io_psize = MMU_PAGE_64K; |
671 | } else | |
bf72aeba PM |
672 | mmu_ci_restrictions = 1; |
673 | } | |
370a908d | 674 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 675 | |
cec08e7a BH |
676 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
677 | /* We try to use 16M pages for vmemmap if that is supported | |
678 | * and we have at least 1G of RAM at boot | |
679 | */ | |
680 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 681 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
682 | mmu_vmemmap_psize = MMU_PAGE_16M; |
683 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
684 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
685 | else | |
686 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
687 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
688 | ||
bf72aeba | 689 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
690 | "virtual = %d, io = %d" |
691 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
692 | ", vmemmap = %d" | |
693 | #endif | |
694 | "\n", | |
3c726f8d | 695 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 696 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
697 | mmu_psize_defs[mmu_io_psize].shift |
698 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
699 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
700 | #endif | |
701 | ); | |
3c726f8d BH |
702 | } |
703 | ||
704 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
705 | const char *uname, int depth, | |
706 | void *data) | |
707 | { | |
9d0c4dfe RH |
708 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); |
709 | const __be32 *prop; | |
3c726f8d BH |
710 | |
711 | /* We are scanning "cpu" nodes only */ | |
712 | if (type == NULL || strcmp(type, "cpu") != 0) | |
713 | return 0; | |
714 | ||
12f04f2b | 715 | prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL); |
3c726f8d BH |
716 | if (prop != NULL) { |
717 | /* pft_size[0] is the NUMA CEC cookie */ | |
12f04f2b | 718 | ppc64_pft_size = be32_to_cpu(prop[1]); |
3c726f8d | 719 | return 1; |
1da177e4 | 720 | } |
3c726f8d | 721 | return 0; |
1da177e4 LT |
722 | } |
723 | ||
5c3c7ede | 724 | unsigned htab_shift_for_mem_size(unsigned long mem_size) |
3eac8c69 | 725 | { |
5c3c7ede DG |
726 | unsigned memshift = __ilog2(mem_size); |
727 | unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift; | |
728 | unsigned pteg_shift; | |
729 | ||
730 | /* round mem_size up to next power of 2 */ | |
731 | if ((1UL << memshift) < mem_size) | |
732 | memshift += 1; | |
3eac8c69 | 733 | |
5c3c7ede DG |
734 | /* aim for 2 pages / pteg */ |
735 | pteg_shift = memshift - (pshift + 1); | |
3eac8c69 | 736 | |
5c3c7ede DG |
737 | /* |
738 | * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab | |
739 | * size permitted by the architecture. | |
740 | */ | |
741 | return max(pteg_shift + 7, 18U); | |
742 | } | |
743 | ||
744 | static unsigned long __init htab_get_table_size(void) | |
745 | { | |
3c726f8d | 746 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 747 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 748 | * calculate it now based on the total RAM size |
3eac8c69 | 749 | */ |
3c726f8d BH |
750 | if (ppc64_pft_size == 0) |
751 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
752 | if (ppc64_pft_size) |
753 | return 1UL << ppc64_pft_size; | |
754 | ||
5c3c7ede | 755 | return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size()); |
3eac8c69 PM |
756 | } |
757 | ||
54b79248 | 758 | #ifdef CONFIG_MEMORY_HOTPLUG |
438cc81a DG |
759 | void resize_hpt_for_hotplug(unsigned long new_mem_size) |
760 | { | |
761 | unsigned target_hpt_shift; | |
762 | ||
763 | if (!mmu_hash_ops.resize_hpt) | |
764 | return; | |
765 | ||
766 | target_hpt_shift = htab_shift_for_mem_size(new_mem_size); | |
767 | ||
768 | /* | |
769 | * To avoid lots of HPT resizes if memory size is fluctuating | |
770 | * across a boundary, we deliberately have some hysterisis | |
771 | * here: we immediately increase the HPT size if the target | |
772 | * shift exceeds the current shift, but we won't attempt to | |
773 | * reduce unless the target shift is at least 2 below the | |
774 | * current shift | |
775 | */ | |
776 | if ((target_hpt_shift > ppc64_pft_size) | |
777 | || (target_hpt_shift < (ppc64_pft_size - 1))) { | |
778 | int rc; | |
779 | ||
780 | rc = mmu_hash_ops.resize_hpt(target_hpt_shift); | |
7339390d | 781 | if (rc && (rc != -ENODEV)) |
438cc81a DG |
782 | printk(KERN_WARNING |
783 | "Unable to resize hash page table to target order %d: %d\n", | |
784 | target_hpt_shift, rc); | |
785 | } | |
786 | } | |
787 | ||
29ab6c47 | 788 | int hash__create_section_mapping(unsigned long start, unsigned long end, int nid) |
54b79248 | 789 | { |
1dace6c6 DG |
790 | int rc = htab_bolt_mapping(start, end, __pa(start), |
791 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, | |
792 | mmu_kernel_ssize); | |
793 | ||
794 | if (rc < 0) { | |
795 | int rc2 = htab_remove_mapping(start, end, mmu_linear_psize, | |
796 | mmu_kernel_ssize); | |
797 | BUG_ON(rc2 && (rc2 != -ENOENT)); | |
798 | } | |
799 | return rc; | |
54b79248 | 800 | } |
f8c8803b | 801 | |
32b53c01 | 802 | int hash__remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 803 | { |
abd0a0e7 DG |
804 | int rc = htab_remove_mapping(start, end, mmu_linear_psize, |
805 | mmu_kernel_ssize); | |
806 | WARN_ON(rc < 0); | |
807 | return rc; | |
f8c8803b | 808 | } |
54b79248 MK |
809 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
810 | ||
50de596d | 811 | static void __init hash_init_partition_table(phys_addr_t hash_table, |
4b7a3504 | 812 | unsigned long htab_size) |
50de596d | 813 | { |
9d661958 | 814 | mmu_partition_table_init(); |
50de596d AK |
815 | |
816 | /* | |
9d661958 PM |
817 | * PS field (VRMA page size) is not used for LPID 0, hence set to 0. |
818 | * For now, UPRT is 0 and we have no segment table. | |
50de596d | 819 | */ |
4b7a3504 | 820 | htab_size = __ilog2(htab_size) - 18; |
9d661958 | 821 | mmu_partition_table_set_entry(0, hash_table | htab_size, 0); |
56547411 | 822 | pr_info("Partition table %p\n", partition_tb); |
50de596d AK |
823 | } |
824 | ||
757c74d2 | 825 | static void __init htab_initialize(void) |
1da177e4 | 826 | { |
337a7128 | 827 | unsigned long table; |
1da177e4 | 828 | unsigned long pteg_count; |
9e88ba4e | 829 | unsigned long prot; |
5556ecf5 | 830 | unsigned long base = 0, size = 0; |
28be7072 | 831 | struct memblock_region *reg; |
3c726f8d | 832 | |
1da177e4 LT |
833 | DBG(" -> htab_initialize()\n"); |
834 | ||
44ae3ab3 | 835 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
836 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
837 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
838 | printk(KERN_INFO "Using 1TB segments\n"); | |
839 | } | |
840 | ||
1da177e4 LT |
841 | /* |
842 | * Calculate the required size of the htab. We want the number of | |
843 | * PTEGs to equal one half the number of real pages. | |
844 | */ | |
3c726f8d | 845 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
846 | pteg_count = htab_size_bytes >> 7; |
847 | ||
1da177e4 LT |
848 | htab_hash_mask = pteg_count - 1; |
849 | ||
5556ecf5 BH |
850 | if (firmware_has_feature(FW_FEATURE_LPAR) || |
851 | firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
1da177e4 LT |
852 | /* Using a hypervisor which owns the htab */ |
853 | htab_address = NULL; | |
854 | _SDR1 = 0; | |
dbfcf3cb PM |
855 | /* |
856 | * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall | |
857 | * to inform the hypervisor that we wish to use the HPT. | |
858 | */ | |
859 | if (cpu_has_feature(CPU_FTR_ARCH_300)) | |
860 | register_process_table(0, 0, 0); | |
3ccc00a7 MS |
861 | #ifdef CONFIG_FA_DUMP |
862 | /* | |
863 | * If firmware assisted dump is active firmware preserves | |
864 | * the contents of htab along with entire partition memory. | |
865 | * Clear the htab if firmware assisted dump is active so | |
866 | * that we dont end up using old mappings. | |
867 | */ | |
7025776e BH |
868 | if (is_fadump_active() && mmu_hash_ops.hpte_clear_all) |
869 | mmu_hash_ops.hpte_clear_all(); | |
3ccc00a7 | 870 | #endif |
1da177e4 | 871 | } else { |
5556ecf5 BH |
872 | unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE; |
873 | ||
874 | #ifdef CONFIG_PPC_CELL | |
875 | /* | |
876 | * Cell may require the hash table down low when using the | |
877 | * Axon IOMMU in order to fit the dynamic region over it, see | |
878 | * comments in cell/iommu.c | |
1da177e4 | 879 | */ |
5556ecf5 | 880 | if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) { |
31bf1119 | 881 | limit = 0x80000000; |
5556ecf5 BH |
882 | pr_info("Hash table forced below 2G for Axon IOMMU\n"); |
883 | } | |
884 | #endif /* CONFIG_PPC_CELL */ | |
41d824bf | 885 | |
5556ecf5 BH |
886 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, |
887 | limit); | |
1da177e4 LT |
888 | |
889 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
890 | htab_size_bytes); | |
891 | ||
70267a7f | 892 | htab_address = __va(table); |
1da177e4 LT |
893 | |
894 | /* htab absolute addr + encoded htabsize */ | |
4b7a3504 | 895 | _SDR1 = table + __ilog2(htab_size_bytes) - 18; |
1da177e4 LT |
896 | |
897 | /* Initialize the HPT with no entries */ | |
898 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 | 899 | |
50de596d AK |
900 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
901 | /* Set SDR1 */ | |
902 | mtspr(SPRN_SDR1, _SDR1); | |
903 | else | |
4b7a3504 | 904 | hash_init_partition_table(table, htab_size_bytes); |
1da177e4 LT |
905 | } |
906 | ||
f5ea64dc | 907 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 908 | |
370a908d | 909 | #ifdef CONFIG_DEBUG_PAGEALLOC |
e7df0d88 JK |
910 | if (debug_pagealloc_enabled()) { |
911 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; | |
912 | linear_map_hash_slots = __va(memblock_alloc_base( | |
913 | linear_map_hash_count, 1, ppc64_rma_size)); | |
914 | memset(linear_map_hash_slots, 0, linear_map_hash_count); | |
915 | } | |
370a908d BH |
916 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
917 | ||
1da177e4 | 918 | /* create bolted the linear mapping in the hash table */ |
28be7072 BH |
919 | for_each_memblock(memory, reg) { |
920 | base = (unsigned long)__va(reg->base); | |
921 | size = reg->size; | |
1da177e4 | 922 | |
5c339919 | 923 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 924 | base, size, prot); |
1da177e4 | 925 | |
caf80e57 | 926 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 927 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
928 | } |
929 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
930 | |
931 | /* | |
932 | * If we have a memory_limit and we've allocated TCEs then we need to | |
933 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
934 | * case that the TCEs start below memory_limit. | |
935 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
936 | * for either 4K or 16MB pages. | |
937 | */ | |
938 | if (tce_alloc_start) { | |
b5666f70 ME |
939 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
940 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
941 | |
942 | if (base + size >= tce_alloc_start) | |
943 | tce_alloc_start = base + size + 1; | |
944 | ||
caf80e57 | 945 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 946 | __pa(tce_alloc_start), prot, |
1189be65 | 947 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
948 | } |
949 | ||
7d0daae4 | 950 | |
1da177e4 LT |
951 | DBG(" <- htab_initialize()\n"); |
952 | } | |
953 | #undef KB | |
954 | #undef MB | |
1da177e4 | 955 | |
bacf9cf8 ME |
956 | void __init hash__early_init_devtree(void) |
957 | { | |
958 | /* Initialize segment sizes */ | |
959 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
960 | ||
961 | /* Initialize page sizes */ | |
962 | htab_scan_page_sizes(); | |
963 | } | |
964 | ||
756d08d1 | 965 | void __init hash__early_init_mmu(void) |
799d6046 | 966 | { |
9d2edb18 | 967 | #ifndef CONFIG_PPC_64K_PAGES |
6aa59f51 | 968 | /* |
9d2edb18 | 969 | * We have code in __hash_page_4K() and elsewhere, which assumes it can |
6aa59f51 AK |
970 | * do the following: |
971 | * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX); | |
972 | * | |
973 | * Where the slot number is between 0-15, and values of 8-15 indicate | |
974 | * the secondary bucket. For that code to work H_PAGE_F_SECOND and | |
975 | * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and | |
976 | * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here | |
977 | * with a BUILD_BUG_ON(). | |
978 | */ | |
979 | BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); | |
9d2edb18 | 980 | #endif /* CONFIG_PPC_64K_PAGES */ |
6aa59f51 | 981 | |
bacf9cf8 ME |
982 | htab_init_page_sizes(); |
983 | ||
dd1842a2 AK |
984 | /* |
985 | * initialize page table size | |
986 | */ | |
5ed7ecd0 AK |
987 | __pte_frag_nr = H_PTE_FRAG_NR; |
988 | __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; | |
8a6c697b AK |
989 | __pmd_frag_nr = H_PMD_FRAG_NR; |
990 | __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT; | |
5ed7ecd0 | 991 | |
dd1842a2 AK |
992 | __pte_index_size = H_PTE_INDEX_SIZE; |
993 | __pmd_index_size = H_PMD_INDEX_SIZE; | |
994 | __pud_index_size = H_PUD_INDEX_SIZE; | |
995 | __pgd_index_size = H_PGD_INDEX_SIZE; | |
fae22116 | 996 | __pud_cache_index = H_PUD_CACHE_INDEX; |
dd1842a2 AK |
997 | __pte_table_size = H_PTE_TABLE_SIZE; |
998 | __pmd_table_size = H_PMD_TABLE_SIZE; | |
999 | __pud_table_size = H_PUD_TABLE_SIZE; | |
1000 | __pgd_table_size = H_PGD_TABLE_SIZE; | |
a2f41eb9 AK |
1001 | /* |
1002 | * 4k use hugepd format, so for hash set then to | |
1003 | * zero | |
1004 | */ | |
1005 | __pmd_val_bits = 0; | |
1006 | __pud_val_bits = 0; | |
1007 | __pgd_val_bits = 0; | |
d6a9996e AK |
1008 | |
1009 | __kernel_virt_start = H_KERN_VIRT_START; | |
1010 | __kernel_virt_size = H_KERN_VIRT_SIZE; | |
1011 | __vmalloc_start = H_VMALLOC_START; | |
1012 | __vmalloc_end = H_VMALLOC_END; | |
63ee9b2f | 1013 | __kernel_io_start = H_KERN_IO_START; |
d6a9996e AK |
1014 | vmemmap = (struct page *)H_VMEMMAP_BASE; |
1015 | ioremap_bot = IOREMAP_BASE; | |
1016 | ||
bfa37087 DS |
1017 | #ifdef CONFIG_PCI |
1018 | pci_io_base = ISA_IO_BASE; | |
1019 | #endif | |
1020 | ||
166dd7d3 BH |
1021 | /* Select appropriate backend */ |
1022 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
1023 | ps3_early_mm_init(); | |
1024 | else if (firmware_has_feature(FW_FEATURE_LPAR)) | |
6364e84e | 1025 | hpte_init_pseries(); |
fbef66f0 | 1026 | else if (IS_ENABLED(CONFIG_PPC_NATIVE)) |
166dd7d3 BH |
1027 | hpte_init_native(); |
1028 | ||
7353644f ME |
1029 | if (!mmu_hash_ops.hpte_insert) |
1030 | panic("hash__early_init_mmu: No MMU hash ops defined!\n"); | |
1031 | ||
757c74d2 | 1032 | /* Initialize the MMU Hash table and create the linear mapping |
376af594 ME |
1033 | * of memory. Has to be done before SLB initialization as this is |
1034 | * currently where the page size encoding is obtained. | |
757c74d2 BH |
1035 | */ |
1036 | htab_initialize(); | |
1037 | ||
56547411 | 1038 | pr_info("Initializing hash mmu with SLB\n"); |
376af594 | 1039 | /* Initialize SLB management */ |
13b3d13b | 1040 | slb_initialize(); |
d4748276 NP |
1041 | |
1042 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1043 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1044 | tlbiel_all(); | |
757c74d2 BH |
1045 | } |
1046 | ||
1047 | #ifdef CONFIG_SMP | |
756d08d1 | 1048 | void hash__early_init_mmu_secondary(void) |
757c74d2 BH |
1049 | { |
1050 | /* Initialize hash table for that CPU */ | |
b5dcc609 | 1051 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
cac4a185 | 1052 | |
b5dcc609 AK |
1053 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
1054 | mtspr(SPRN_SDR1, _SDR1); | |
1055 | else | |
1056 | mtspr(SPRN_PTCR, | |
1057 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
1058 | } | |
376af594 | 1059 | /* Initialize SLB */ |
13b3d13b | 1060 | slb_initialize(); |
d4748276 NP |
1061 | |
1062 | if (cpu_has_feature(CPU_FTR_ARCH_206) | |
1063 | && cpu_has_feature(CPU_FTR_HVMODE)) | |
1064 | tlbiel_all(); | |
799d6046 | 1065 | } |
757c74d2 | 1066 | #endif /* CONFIG_SMP */ |
799d6046 | 1067 | |
1da177e4 LT |
1068 | /* |
1069 | * Called by asm hashtable.S for doing lazy icache flush | |
1070 | */ | |
1071 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
1072 | { | |
1073 | struct page *page; | |
1074 | ||
76c8e25b BH |
1075 | if (!pfn_valid(pte_pfn(pte))) |
1076 | return pp; | |
1077 | ||
1da177e4 LT |
1078 | page = pte_page(pte); |
1079 | ||
1080 | /* page is dirty */ | |
1081 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
1082 | if (trap == 0x400) { | |
0895ecda | 1083 | flush_dcache_icache_page(page); |
1da177e4 LT |
1084 | set_bit(PG_arch_1, &page->flags); |
1085 | } else | |
3c726f8d | 1086 | pp |= HPTE_R_N; |
1da177e4 LT |
1087 | } |
1088 | return pp; | |
1089 | } | |
1090 | ||
3a8247cc | 1091 | #ifdef CONFIG_PPC_MM_SLICES |
e51df2c1 | 1092 | static unsigned int get_paca_psize(unsigned long addr) |
3a8247cc | 1093 | { |
15472423 | 1094 | unsigned char *psizes; |
7aa0727f | 1095 | unsigned long index, mask_index; |
3a8247cc PM |
1096 | |
1097 | if (addr < SLICE_LOW_TOP) { | |
15472423 | 1098 | psizes = get_paca()->mm_ctx_low_slices_psize; |
3a8247cc | 1099 | index = GET_LOW_SLICE_INDEX(addr); |
15472423 CL |
1100 | } else { |
1101 | psizes = get_paca()->mm_ctx_high_slices_psize; | |
1102 | index = GET_HIGH_SLICE_INDEX(addr); | |
3a8247cc | 1103 | } |
7aa0727f | 1104 | mask_index = index & 0x1; |
15472423 | 1105 | return (psizes[index >> 1] >> (mask_index * 4)) & 0xF; |
3a8247cc PM |
1106 | } |
1107 | ||
1108 | #else | |
1109 | unsigned int get_paca_psize(unsigned long addr) | |
1110 | { | |
c33e54fa | 1111 | return get_paca()->mm_ctx_user_psize; |
3a8247cc PM |
1112 | } |
1113 | #endif | |
1114 | ||
721151d0 PM |
1115 | /* |
1116 | * Demote a segment to using 4k pages. | |
1117 | * For now this makes the whole process use 4k pages. | |
1118 | */ | |
721151d0 | 1119 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 1120 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 1121 | { |
3a8247cc | 1122 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 1123 | return; |
3a8247cc | 1124 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
be3ebfe8 | 1125 | copro_flush_all_slbs(mm); |
a1dca346 | 1126 | if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) { |
c395465d | 1127 | |
52b1e665 | 1128 | copy_mm_to_paca(mm); |
fa28237c PM |
1129 | slb_flush_and_rebolt(); |
1130 | } | |
721151d0 | 1131 | } |
16f1c746 | 1132 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 1133 | |
fa28237c PM |
1134 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1135 | /* | |
1136 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
1137 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
1138 | * | |
1139 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
73a1441a | 1140 | * _PAGE_RWX: no access. |
fa28237c | 1141 | */ |
d28513bc | 1142 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 1143 | { |
d28513bc | 1144 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
1145 | u32 spp = 0; |
1146 | u32 **sbpm, *sbpp; | |
1147 | ||
1148 | if (ea >= spt->maxaddr) | |
1149 | return 0; | |
b0d436c7 | 1150 | if (ea < 0x100000000UL) { |
fa28237c PM |
1151 | /* addresses below 4GB use spt->low_prot */ |
1152 | sbpm = spt->low_prot; | |
1153 | } else { | |
1154 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
1155 | if (!sbpm) | |
1156 | return 0; | |
1157 | } | |
1158 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
1159 | if (!sbpp) | |
1160 | return 0; | |
1161 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
1162 | ||
1163 | /* extract 2-bit bitfield for this 4k subpage */ | |
1164 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
1165 | ||
73a1441a AK |
1166 | /* |
1167 | * 0 -> full premission | |
1168 | * 1 -> Read only | |
1169 | * 2 -> no access. | |
1170 | * We return the flag that need to be cleared. | |
1171 | */ | |
1172 | spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0); | |
fa28237c PM |
1173 | return spp; |
1174 | } | |
1175 | ||
1176 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 1177 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
1178 | { |
1179 | return 0; | |
1180 | } | |
1181 | #endif | |
1182 | ||
4b8692c0 BH |
1183 | void hash_failure_debug(unsigned long ea, unsigned long access, |
1184 | unsigned long vsid, unsigned long trap, | |
d8139ebf | 1185 | int ssize, int psize, int lpsize, unsigned long pte) |
4b8692c0 BH |
1186 | { |
1187 | if (!printk_ratelimit()) | |
1188 | return; | |
1189 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
1190 | ea, access, current->comm); | |
d8139ebf AK |
1191 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n", |
1192 | trap, vsid, ssize, psize, lpsize, pte); | |
4b8692c0 BH |
1193 | } |
1194 | ||
09567e7f ME |
1195 | static void check_paca_psize(unsigned long ea, struct mm_struct *mm, |
1196 | int psize, bool user_region) | |
1197 | { | |
1198 | if (user_region) { | |
1199 | if (psize != get_paca_psize(ea)) { | |
52b1e665 | 1200 | copy_mm_to_paca(mm); |
09567e7f ME |
1201 | slb_flush_and_rebolt(); |
1202 | } | |
1203 | } else if (get_paca()->vmalloc_sllp != | |
1204 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1205 | get_paca()->vmalloc_sllp = | |
1206 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
1207 | slb_vmalloc_update(); | |
1208 | } | |
1209 | } | |
1210 | ||
1da177e4 LT |
1211 | /* Result code is: |
1212 | * 0 - handled | |
1213 | * 1 - normal page fault | |
1214 | * -1 - critical hash insertion error | |
fa28237c | 1215 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 | 1216 | */ |
aefa5688 AK |
1217 | int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
1218 | unsigned long access, unsigned long trap, | |
1219 | unsigned long flags) | |
1da177e4 | 1220 | { |
891121e6 | 1221 | bool is_thp; |
ba12eede | 1222 | enum ctx_state prev_state = exception_enter(); |
a1128f8f | 1223 | pgd_t *pgdir; |
1da177e4 | 1224 | unsigned long vsid; |
1da177e4 | 1225 | pte_t *ptep; |
a4fe3ce7 | 1226 | unsigned hugeshift; |
aefa5688 | 1227 | int rc, user_region = 0; |
1189be65 | 1228 | int psize, ssize; |
1da177e4 | 1229 | |
3c726f8d BH |
1230 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
1231 | ea, access, trap); | |
cfcb3d80 | 1232 | trace_hash_fault(ea, access, trap); |
1f8d419e | 1233 | |
3c726f8d | 1234 | /* Get region & vsid */ |
1da177e4 LT |
1235 | switch (REGION_ID(ea)) { |
1236 | case USER_REGION_ID: | |
1237 | user_region = 1; | |
3c726f8d BH |
1238 | if (! mm) { |
1239 | DBG_LOW(" user region with no mm !\n"); | |
ba12eede LZ |
1240 | rc = 1; |
1241 | goto bail; | |
3c726f8d | 1242 | } |
16c2d476 | 1243 | psize = get_slice_psize(mm, ea); |
1189be65 | 1244 | ssize = user_segment_size(ea); |
f384796c | 1245 | vsid = get_user_vsid(&mm->context, ea, ssize); |
1da177e4 | 1246 | break; |
1da177e4 | 1247 | case VMALLOC_REGION_ID: |
1189be65 | 1248 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
1249 | if (ea < VMALLOC_END) |
1250 | psize = mmu_vmalloc_psize; | |
1251 | else | |
1252 | psize = mmu_io_psize; | |
1189be65 | 1253 | ssize = mmu_kernel_ssize; |
1da177e4 | 1254 | break; |
1da177e4 LT |
1255 | default: |
1256 | /* Not a valid range | |
1257 | * Send the problem up to do_page_fault | |
1258 | */ | |
ba12eede LZ |
1259 | rc = 1; |
1260 | goto bail; | |
1da177e4 | 1261 | } |
3c726f8d | 1262 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 1263 | |
c60ac569 AK |
1264 | /* Bad address. */ |
1265 | if (!vsid) { | |
1266 | DBG_LOW("Bad address!\n"); | |
ba12eede LZ |
1267 | rc = 1; |
1268 | goto bail; | |
c60ac569 | 1269 | } |
3c726f8d | 1270 | /* Get pgdir */ |
1da177e4 | 1271 | pgdir = mm->pgd; |
ba12eede LZ |
1272 | if (pgdir == NULL) { |
1273 | rc = 1; | |
1274 | goto bail; | |
1275 | } | |
1da177e4 | 1276 | |
3c726f8d | 1277 | /* Check CPU locality */ |
b426e4bd | 1278 | if (user_region && mm_is_thread_local(mm)) |
aefa5688 | 1279 | flags |= HPTE_LOCAL_UPDATE; |
1da177e4 | 1280 | |
16c2d476 | 1281 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
1282 | /* If we use 4K pages and our psize is not 4K, then we might |
1283 | * be hitting a special driver mapping, and need to align the | |
1284 | * address before we fetch the PTE. | |
1285 | * | |
1286 | * It could also be a hugepage mapping, in which case this is | |
1287 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
1288 | */ |
1289 | if (psize != MMU_PAGE_4K) | |
1290 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
1291 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1292 | ||
3c726f8d | 1293 | /* Get PTE and page size from page tables */ |
94171b19 | 1294 | ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift); |
3c726f8d BH |
1295 | if (ptep == NULL || !pte_present(*ptep)) { |
1296 | DBG_LOW(" no PTE !\n"); | |
ba12eede LZ |
1297 | rc = 1; |
1298 | goto bail; | |
3c726f8d BH |
1299 | } |
1300 | ||
ca91e6c0 BH |
1301 | /* Add _PAGE_PRESENT to the required access perm */ |
1302 | access |= _PAGE_PRESENT; | |
1303 | ||
1304 | /* Pre-check access permissions (will be re-checked atomically | |
1305 | * in __hash_page_XX but this pre-check is a fast path | |
1306 | */ | |
ac29c640 | 1307 | if (!check_pte_access(access, pte_val(*ptep))) { |
ca91e6c0 | 1308 | DBG_LOW(" no access !\n"); |
ba12eede LZ |
1309 | rc = 1; |
1310 | goto bail; | |
ca91e6c0 BH |
1311 | } |
1312 | ||
ba12eede | 1313 | if (hugeshift) { |
891121e6 | 1314 | if (is_thp) |
6d492ecc | 1315 | rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep, |
aefa5688 | 1316 | trap, flags, ssize, psize); |
6d492ecc AK |
1317 | #ifdef CONFIG_HUGETLB_PAGE |
1318 | else | |
1319 | rc = __hash_page_huge(ea, access, vsid, ptep, trap, | |
aefa5688 | 1320 | flags, ssize, hugeshift, psize); |
6d492ecc AK |
1321 | #else |
1322 | else { | |
1323 | /* | |
1324 | * if we have hugeshift, and is not transhuge with | |
1325 | * hugetlb disabled, something is really wrong. | |
1326 | */ | |
1327 | rc = 1; | |
1328 | WARN_ON(1); | |
1329 | } | |
1330 | #endif | |
a1dca346 IM |
1331 | if (current->mm == mm) |
1332 | check_paca_psize(ea, mm, psize, user_region); | |
09567e7f | 1333 | |
ba12eede LZ |
1334 | goto bail; |
1335 | } | |
a4fe3ce7 | 1336 | |
3c726f8d BH |
1337 | #ifndef CONFIG_PPC_64K_PAGES |
1338 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1339 | #else | |
1340 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1341 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1342 | #endif | |
3c726f8d | 1343 | /* Do actual hashing */ |
16c2d476 | 1344 | #ifdef CONFIG_PPC_64K_PAGES |
945537df AK |
1345 | /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */ |
1346 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) { | |
721151d0 PM |
1347 | demote_segment_4k(mm, ea); |
1348 | psize = MMU_PAGE_4K; | |
1349 | } | |
1350 | ||
16f1c746 BH |
1351 | /* If this PTE is non-cacheable and we have restrictions on |
1352 | * using non cacheable large pages, then we switch to 4k | |
1353 | */ | |
30bda41a | 1354 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) { |
16f1c746 BH |
1355 | if (user_region) { |
1356 | demote_segment_4k(mm, ea); | |
1357 | psize = MMU_PAGE_4K; | |
1358 | } else if (ea < VMALLOC_END) { | |
1359 | /* | |
1360 | * some driver did a non-cacheable mapping | |
1361 | * in vmalloc space, so switch vmalloc | |
1362 | * to 4k pages | |
1363 | */ | |
1364 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1365 | "to 4kB pages because of " | |
1366 | "non-cacheable mapping\n"); | |
1367 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
be3ebfe8 | 1368 | copro_flush_all_slbs(mm); |
bf72aeba | 1369 | } |
16f1c746 | 1370 | } |
09567e7f | 1371 | |
0863d7f2 AK |
1372 | #endif /* CONFIG_PPC_64K_PAGES */ |
1373 | ||
a1dca346 IM |
1374 | if (current->mm == mm) |
1375 | check_paca_psize(ea, mm, psize, user_region); | |
16f1c746 | 1376 | |
73b341ef | 1377 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1378 | if (psize == MMU_PAGE_64K) |
aefa5688 AK |
1379 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1380 | flags, ssize); | |
3c726f8d | 1381 | else |
73b341ef | 1382 | #endif /* CONFIG_PPC_64K_PAGES */ |
fa28237c | 1383 | { |
a1128f8f | 1384 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1385 | if (access & spp) |
1386 | rc = -2; | |
1387 | else | |
1388 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
aefa5688 | 1389 | flags, ssize, spp); |
fa28237c | 1390 | } |
3c726f8d | 1391 | |
4b8692c0 BH |
1392 | /* Dump some info in case of hash insertion failure, they should |
1393 | * never happen so it is really useful to know if/when they do | |
1394 | */ | |
1395 | if (rc == -1) | |
1396 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
d8139ebf | 1397 | psize, pte_val(*ptep)); |
3c726f8d BH |
1398 | #ifndef CONFIG_PPC_64K_PAGES |
1399 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1400 | #else | |
1401 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1402 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1403 | #endif | |
1404 | DBG_LOW(" -> rc=%d\n", rc); | |
ba12eede LZ |
1405 | |
1406 | bail: | |
1407 | exception_exit(prev_state); | |
3c726f8d | 1408 | return rc; |
1da177e4 | 1409 | } |
a1dca346 IM |
1410 | EXPORT_SYMBOL_GPL(hash_page_mm); |
1411 | ||
aefa5688 AK |
1412 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
1413 | unsigned long dsisr) | |
a1dca346 | 1414 | { |
aefa5688 | 1415 | unsigned long flags = 0; |
a1dca346 IM |
1416 | struct mm_struct *mm = current->mm; |
1417 | ||
1418 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1419 | mm = &init_mm; | |
1420 | ||
aefa5688 AK |
1421 | if (dsisr & DSISR_NOHPTE) |
1422 | flags |= HPTE_NOHPTE_UPDATE; | |
1423 | ||
1424 | return hash_page_mm(mm, ea, access, trap, flags); | |
a1dca346 | 1425 | } |
67207b96 | 1426 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1427 | |
106713a1 AK |
1428 | int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap, |
1429 | unsigned long dsisr) | |
1430 | { | |
c7d54842 | 1431 | unsigned long access = _PAGE_PRESENT | _PAGE_READ; |
106713a1 AK |
1432 | unsigned long flags = 0; |
1433 | struct mm_struct *mm = current->mm; | |
1434 | ||
1435 | if (REGION_ID(ea) == VMALLOC_REGION_ID) | |
1436 | mm = &init_mm; | |
1437 | ||
1438 | if (dsisr & DSISR_NOHPTE) | |
1439 | flags |= HPTE_NOHPTE_UPDATE; | |
1440 | ||
1441 | if (dsisr & DSISR_ISSTORE) | |
c7d54842 | 1442 | access |= _PAGE_WRITE; |
106713a1 | 1443 | /* |
ac29c640 AK |
1444 | * We set _PAGE_PRIVILEGED only when |
1445 | * kernel mode access kernel space. | |
1446 | * | |
1447 | * _PAGE_PRIVILEGED is NOT set | |
1448 | * 1) when kernel mode access user space | |
1449 | * 2) user space access kernel space. | |
106713a1 | 1450 | */ |
ac29c640 | 1451 | access |= _PAGE_PRIVILEGED; |
106713a1 | 1452 | if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID)) |
ac29c640 | 1453 | access &= ~_PAGE_PRIVILEGED; |
106713a1 AK |
1454 | |
1455 | if (trap == 0x400) | |
1456 | access |= _PAGE_EXEC; | |
1457 | ||
1458 | return hash_page_mm(mm, ea, access, trap, flags); | |
1459 | } | |
1460 | ||
8bbc9b7b ME |
1461 | #ifdef CONFIG_PPC_MM_SLICES |
1462 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1463 | { | |
aac55d75 ME |
1464 | int psize = get_slice_psize(mm, ea); |
1465 | ||
8bbc9b7b | 1466 | /* We only prefault standard pages for now */ |
aac55d75 ME |
1467 | if (unlikely(psize != mm->context.user_psize)) |
1468 | return false; | |
1469 | ||
1470 | /* | |
1471 | * Don't prefault if subpage protection is enabled for the EA. | |
1472 | */ | |
1473 | if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea))) | |
8bbc9b7b ME |
1474 | return false; |
1475 | ||
1476 | return true; | |
1477 | } | |
1478 | #else | |
1479 | static bool should_hash_preload(struct mm_struct *mm, unsigned long ea) | |
1480 | { | |
1481 | return true; | |
1482 | } | |
1483 | #endif | |
1484 | ||
3c726f8d BH |
1485 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1486 | unsigned long access, unsigned long trap) | |
1da177e4 | 1487 | { |
12bc9f6f | 1488 | int hugepage_shift; |
3c726f8d | 1489 | unsigned long vsid; |
0b97fee0 | 1490 | pgd_t *pgdir; |
3c726f8d | 1491 | pte_t *ptep; |
3c726f8d | 1492 | unsigned long flags; |
aefa5688 | 1493 | int rc, ssize, update_flags = 0; |
3c726f8d | 1494 | |
d0f13e3c BH |
1495 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1496 | ||
8bbc9b7b | 1497 | if (!should_hash_preload(mm, ea)) |
3c726f8d BH |
1498 | return; |
1499 | ||
1500 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1501 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1502 | |
16f1c746 | 1503 | /* Get Linux PTE if available */ |
3c726f8d BH |
1504 | pgdir = mm->pgd; |
1505 | if (pgdir == NULL) | |
1506 | return; | |
0ac52dd7 AK |
1507 | |
1508 | /* Get VSID */ | |
1509 | ssize = user_segment_size(ea); | |
f384796c | 1510 | vsid = get_user_vsid(&mm->context, ea, ssize); |
0ac52dd7 AK |
1511 | if (!vsid) |
1512 | return; | |
1513 | /* | |
1514 | * Hash doesn't like irqs. Walking linux page table with irq disabled | |
1515 | * saves us from holding multiple locks. | |
1516 | */ | |
1517 | local_irq_save(flags); | |
1518 | ||
12bc9f6f AK |
1519 | /* |
1520 | * THP pages use update_mmu_cache_pmd. We don't do | |
1521 | * hash preload there. Hence can ignore THP here | |
1522 | */ | |
94171b19 | 1523 | ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift); |
3c726f8d | 1524 | if (!ptep) |
0ac52dd7 | 1525 | goto out_exit; |
16f1c746 | 1526 | |
12bc9f6f | 1527 | WARN_ON(hugepage_shift); |
16f1c746 | 1528 | #ifdef CONFIG_PPC_64K_PAGES |
945537df | 1529 | /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on |
16f1c746 BH |
1530 | * a 64K kernel), then we don't preload, hash_page() will take |
1531 | * care of it once we actually try to access the page. | |
1532 | * That way we don't have to duplicate all of the logic for segment | |
1533 | * page size demotion here | |
1534 | */ | |
945537df | 1535 | if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep)) |
0ac52dd7 | 1536 | goto out_exit; |
16f1c746 BH |
1537 | #endif /* CONFIG_PPC_64K_PAGES */ |
1538 | ||
16c2d476 | 1539 | /* Is that local to this CPU ? */ |
b426e4bd | 1540 | if (mm_is_thread_local(mm)) |
aefa5688 | 1541 | update_flags |= HPTE_LOCAL_UPDATE; |
16c2d476 BH |
1542 | |
1543 | /* Hash it in */ | |
73b341ef | 1544 | #ifdef CONFIG_PPC_64K_PAGES |
bf72aeba | 1545 | if (mm->context.user_psize == MMU_PAGE_64K) |
aefa5688 AK |
1546 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, |
1547 | update_flags, ssize); | |
1da177e4 | 1548 | else |
73b341ef | 1549 | #endif /* CONFIG_PPC_64K_PAGES */ |
aefa5688 AK |
1550 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags, |
1551 | ssize, subpage_protection(mm, ea)); | |
4b8692c0 BH |
1552 | |
1553 | /* Dump some info in case of hash insertion failure, they should | |
1554 | * never happen so it is really useful to know if/when they do | |
1555 | */ | |
1556 | if (rc == -1) | |
1557 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
d8139ebf AK |
1558 | mm->context.user_psize, |
1559 | mm->context.user_psize, | |
1560 | pte_val(*ptep)); | |
0ac52dd7 | 1561 | out_exit: |
3c726f8d BH |
1562 | local_irq_restore(flags); |
1563 | } | |
1564 | ||
087003e9 RP |
1565 | #ifdef CONFIG_PPC_MEM_KEYS |
1566 | /* | |
1567 | * Return the protection key associated with the given address and the | |
1568 | * mm_struct. | |
1569 | */ | |
1570 | u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address) | |
1571 | { | |
1572 | pte_t *ptep; | |
1573 | u16 pkey = 0; | |
1574 | unsigned long flags; | |
1575 | ||
1576 | if (!mm || !mm->pgd) | |
1577 | return 0; | |
1578 | ||
1579 | local_irq_save(flags); | |
1580 | ptep = find_linux_pte(mm->pgd, address, NULL, NULL); | |
1581 | if (ptep) | |
1582 | pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep))); | |
1583 | local_irq_restore(flags); | |
1584 | ||
1585 | return pkey; | |
1586 | } | |
1587 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
1588 | ||
f1a55ce0 RT |
1589 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1590 | static inline void tm_flush_hash_page(int local) | |
1591 | { | |
1592 | /* | |
1593 | * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a | |
1594 | * page back to a block device w/PIO could pick up transactional data | |
1595 | * (bad!) so we force an abort here. Before the sync the page will be | |
1596 | * made read-only, which will flush_hash_page. BIG ISSUE here: if the | |
1597 | * kernel uses a page from userspace without unmapping it first, it may | |
1598 | * see the speculated version. | |
1599 | */ | |
1600 | if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs && | |
1601 | MSR_TM_ACTIVE(current->thread.regs->msr)) { | |
1602 | tm_enable(); | |
1603 | tm_abort(TM_CAUSE_TLBI); | |
1604 | } | |
1605 | } | |
1606 | #else | |
1607 | static inline void tm_flush_hash_page(int local) | |
1608 | { | |
1609 | } | |
1610 | #endif | |
1611 | ||
318995b4 RP |
1612 | /* |
1613 | * Return the global hash slot, corresponding to the given PTE, which contains | |
1614 | * the HPTE. | |
1615 | */ | |
1616 | unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, | |
1617 | int ssize, real_pte_t rpte, unsigned int subpg_index) | |
1618 | { | |
1619 | unsigned long hash, gslot, hidx; | |
1620 | ||
1621 | hash = hpt_hash(vpn, shift, ssize); | |
1622 | hidx = __rpte_to_hidx(rpte, subpg_index); | |
1623 | if (hidx & _PTEIDX_SECONDARY) | |
1624 | hash = ~hash; | |
1625 | gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1626 | gslot += hidx & _PTEIDX_GROUP_IX; | |
1627 | return gslot; | |
1628 | } | |
1629 | ||
f6ab0b92 BH |
1630 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1631 | * do not forget to update the assembly call site ! | |
1632 | */ | |
5524a27d | 1633 | void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize, |
aefa5688 | 1634 | unsigned long flags) |
3c726f8d | 1635 | { |
a8548686 | 1636 | unsigned long index, shift, gslot; |
aefa5688 | 1637 | int local = flags & HPTE_LOCAL_UPDATE; |
3c726f8d | 1638 | |
5524a27d AK |
1639 | DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn); |
1640 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { | |
a8548686 RP |
1641 | gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index); |
1642 | DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot); | |
db3d8534 AK |
1643 | /* |
1644 | * We use same base page size and actual psize, because we don't | |
1645 | * use these functions for hugepage | |
1646 | */ | |
a8548686 | 1647 | mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize, |
7025776e | 1648 | ssize, local); |
3c726f8d | 1649 | } pte_iterate_hashed_end(); |
bc2a9408 | 1650 | |
f1a55ce0 | 1651 | tm_flush_hash_page(local); |
1da177e4 LT |
1652 | } |
1653 | ||
f1581bf1 AK |
1654 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1655 | void flush_hash_hugepage(unsigned long vsid, unsigned long addr, | |
aefa5688 AK |
1656 | pmd_t *pmdp, unsigned int psize, int ssize, |
1657 | unsigned long flags) | |
f1581bf1 AK |
1658 | { |
1659 | int i, max_hpte_count, valid; | |
1660 | unsigned long s_addr; | |
1661 | unsigned char *hpte_slot_array; | |
1662 | unsigned long hidx, shift, vpn, hash, slot; | |
aefa5688 | 1663 | int local = flags & HPTE_LOCAL_UPDATE; |
f1581bf1 AK |
1664 | |
1665 | s_addr = addr & HPAGE_PMD_MASK; | |
1666 | hpte_slot_array = get_hpte_slot_array(pmdp); | |
1667 | /* | |
1668 | * IF we try to do a HUGE PTE update after a withdraw is done. | |
1669 | * we will find the below NULL. This happens when we do | |
1670 | * split_huge_page_pmd | |
1671 | */ | |
1672 | if (!hpte_slot_array) | |
1673 | return; | |
1674 | ||
7025776e BH |
1675 | if (mmu_hash_ops.hugepage_invalidate) { |
1676 | mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array, | |
1677 | psize, ssize, local); | |
d557b098 AK |
1678 | goto tm_abort; |
1679 | } | |
f1581bf1 AK |
1680 | /* |
1681 | * No bluk hpte removal support, invalidate each entry | |
1682 | */ | |
1683 | shift = mmu_psize_defs[psize].shift; | |
1684 | max_hpte_count = HPAGE_PMD_SIZE >> shift; | |
1685 | for (i = 0; i < max_hpte_count; i++) { | |
1686 | /* | |
1687 | * 8 bits per each hpte entries | |
1688 | * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit] | |
1689 | */ | |
1690 | valid = hpte_valid(hpte_slot_array, i); | |
1691 | if (!valid) | |
1692 | continue; | |
1693 | hidx = hpte_hash_index(hpte_slot_array, i); | |
1694 | ||
1695 | /* get the vpn */ | |
1696 | addr = s_addr + (i * (1ul << shift)); | |
1697 | vpn = hpt_vpn(addr, vsid, ssize); | |
1698 | hash = hpt_hash(vpn, shift, ssize); | |
1699 | if (hidx & _PTEIDX_SECONDARY) | |
1700 | hash = ~hash; | |
1701 | ||
1702 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1703 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1704 | mmu_hash_ops.hpte_invalidate(slot, vpn, psize, |
1705 | MMU_PAGE_16M, ssize, local); | |
d557b098 AK |
1706 | } |
1707 | tm_abort: | |
f1a55ce0 | 1708 | tm_flush_hash_page(local); |
f1581bf1 AK |
1709 | } |
1710 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1711 | ||
61b1a942 | 1712 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1713 | { |
7025776e BH |
1714 | if (mmu_hash_ops.flush_hash_range) |
1715 | mmu_hash_ops.flush_hash_range(number, local); | |
3c726f8d | 1716 | else { |
1da177e4 | 1717 | int i; |
61b1a942 | 1718 | struct ppc64_tlb_batch *batch = |
69111bac | 1719 | this_cpu_ptr(&ppc64_tlb_batch); |
1da177e4 LT |
1720 | |
1721 | for (i = 0; i < number; i++) | |
5524a27d | 1722 | flush_hash_page(batch->vpn[i], batch->pte[i], |
1189be65 | 1723 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1724 | } |
1725 | } | |
1726 | ||
1da177e4 LT |
1727 | /* |
1728 | * low_hash_fault is called when we the low level hash code failed | |
1729 | * to instert a PTE due to an hypervisor error | |
1730 | */ | |
fa28237c | 1731 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 | 1732 | { |
ba12eede LZ |
1733 | enum ctx_state prev_state = exception_enter(); |
1734 | ||
1da177e4 | 1735 | if (user_mode(regs)) { |
fa28237c PM |
1736 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1737 | if (rc == -2) | |
1738 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1739 | else | |
1740 | #endif | |
1741 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1742 | } else | |
1743 | bad_page_fault(regs, address, SIGBUS); | |
ba12eede LZ |
1744 | |
1745 | exception_exit(prev_state); | |
1da177e4 | 1746 | } |
370a908d | 1747 | |
b170bd3d LZ |
1748 | long hpte_insert_repeating(unsigned long hash, unsigned long vpn, |
1749 | unsigned long pa, unsigned long rflags, | |
1750 | unsigned long vflags, int psize, int ssize) | |
1751 | { | |
1752 | unsigned long hpte_group; | |
1753 | long slot; | |
1754 | ||
1755 | repeat: | |
1531cff4 | 1756 | hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP; |
b170bd3d LZ |
1757 | |
1758 | /* Insert into the hash table, primary slot */ | |
7025776e BH |
1759 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags, |
1760 | psize, psize, ssize); | |
b170bd3d LZ |
1761 | |
1762 | /* Primary is full, try the secondary */ | |
1763 | if (unlikely(slot == -1)) { | |
1531cff4 | 1764 | hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP; |
7025776e BH |
1765 | slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, |
1766 | vflags | HPTE_V_SECONDARY, | |
1767 | psize, psize, ssize); | |
b170bd3d LZ |
1768 | if (slot == -1) { |
1769 | if (mftb() & 0x1) | |
1531cff4 AK |
1770 | hpte_group = (hash & htab_hash_mask) * |
1771 | HPTES_PER_GROUP; | |
b170bd3d | 1772 | |
7025776e | 1773 | mmu_hash_ops.hpte_remove(hpte_group); |
b170bd3d LZ |
1774 | goto repeat; |
1775 | } | |
1776 | } | |
1777 | ||
1778 | return slot; | |
1779 | } | |
1780 | ||
370a908d BH |
1781 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1782 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1783 | { | |
016af59f | 1784 | unsigned long hash; |
1189be65 | 1785 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); |
5524a27d | 1786 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
09f3f326 | 1787 | unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL)); |
016af59f | 1788 | long ret; |
370a908d | 1789 | |
5524a27d | 1790 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d | 1791 | |
c60ac569 AK |
1792 | /* Don't create HPTE entries for bad address */ |
1793 | if (!vsid) | |
1794 | return; | |
016af59f LZ |
1795 | |
1796 | ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode, | |
1797 | HPTE_V_BOLTED, | |
1798 | mmu_linear_psize, mmu_kernel_ssize); | |
1799 | ||
370a908d BH |
1800 | BUG_ON (ret < 0); |
1801 | spin_lock(&linear_map_hash_lock); | |
1802 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1803 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1804 | spin_unlock(&linear_map_hash_lock); | |
1805 | } | |
1806 | ||
1807 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1808 | { | |
1189be65 PM |
1809 | unsigned long hash, hidx, slot; |
1810 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
5524a27d | 1811 | unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize); |
370a908d | 1812 | |
5524a27d | 1813 | hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1814 | spin_lock(&linear_map_hash_lock); |
1815 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1816 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1817 | linear_map_hash_slots[lmi] = 0; | |
1818 | spin_unlock(&linear_map_hash_lock); | |
1819 | if (hidx & _PTEIDX_SECONDARY) | |
1820 | hash = ~hash; | |
1821 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1822 | slot += hidx & _PTEIDX_GROUP_IX; | |
7025776e BH |
1823 | mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize, |
1824 | mmu_linear_psize, | |
1825 | mmu_kernel_ssize, 0); | |
370a908d BH |
1826 | } |
1827 | ||
031bc574 | 1828 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
370a908d BH |
1829 | { |
1830 | unsigned long flags, vaddr, lmi; | |
1831 | int i; | |
1832 | ||
1833 | local_irq_save(flags); | |
1834 | for (i = 0; i < numpages; i++, page++) { | |
1835 | vaddr = (unsigned long)page_address(page); | |
1836 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1837 | if (lmi >= linear_map_hash_count) | |
1838 | continue; | |
1839 | if (enable) | |
1840 | kernel_map_linear_page(vaddr, lmi); | |
1841 | else | |
1842 | kernel_unmap_linear_page(vaddr, lmi); | |
1843 | } | |
1844 | local_irq_restore(flags); | |
1845 | } | |
1846 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 | 1847 | |
756d08d1 | 1848 | void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
cd3db0c4 BH |
1849 | phys_addr_t first_memblock_size) |
1850 | { | |
1851 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1852 | * physical on those processors | |
1853 | */ | |
1854 | BUG_ON(first_memblock_base != 0); | |
1855 | ||
1513c33d NP |
1856 | /* |
1857 | * On virtualized systems the first entry is our RMA region aka VRMA, | |
1858 | * non-virtualized 64-bit hash MMU systems don't have a limitation | |
1859 | * on real mode access. | |
1860 | * | |
c610d65c NP |
1861 | * For guests on platforms before POWER9, we clamp the it limit to 1G |
1862 | * to avoid some funky things such as RTAS bugs etc... | |
cd3db0c4 | 1863 | */ |
1513c33d | 1864 | if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { |
c610d65c NP |
1865 | ppc64_rma_size = first_memblock_size; |
1866 | if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) | |
1867 | ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); | |
cd3db0c4 | 1868 | |
1513c33d NP |
1869 | /* Finally limit subsequent allocations */ |
1870 | memblock_set_current_limit(ppc64_rma_size); | |
1871 | } else { | |
1872 | ppc64_rma_size = ULONG_MAX; | |
1873 | } | |
cd3db0c4 | 1874 | } |
dbcf929c DG |
1875 | |
1876 | #ifdef CONFIG_DEBUG_FS | |
1877 | ||
1878 | static int hpt_order_get(void *data, u64 *val) | |
1879 | { | |
1880 | *val = ppc64_pft_size; | |
1881 | return 0; | |
1882 | } | |
1883 | ||
1884 | static int hpt_order_set(void *data, u64 val) | |
1885 | { | |
1886 | if (!mmu_hash_ops.resize_hpt) | |
1887 | return -ENODEV; | |
1888 | ||
1889 | return mmu_hash_ops.resize_hpt(val); | |
1890 | } | |
1891 | ||
1892 | DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n"); | |
1893 | ||
1894 | static int __init hash64_debugfs(void) | |
1895 | { | |
1896 | if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, | |
1897 | NULL, &fops_hpt_order)) { | |
1898 | pr_err("lpar: unable to create hpt_order debugsfs file\n"); | |
1899 | } | |
1900 | ||
1901 | return 0; | |
1902 | } | |
1903 | machine_device_initcall(pseries, hash64_debugfs); | |
dbcf929c | 1904 | #endif /* CONFIG_DEBUG_FS */ |