Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * native hashtable management. | |
3 | * | |
4 | * SMP scalability work: | |
5 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
3c726f8d BH |
12 | |
13 | #undef DEBUG_LOW | |
14 | ||
1da177e4 LT |
15 | #include <linux/spinlock.h> |
16 | #include <linux/bitops.h> | |
beacc6da | 17 | #include <linux/of.h> |
1da177e4 LT |
18 | #include <linux/threads.h> |
19 | #include <linux/smp.h> | |
20 | ||
1da177e4 LT |
21 | #include <asm/machdep.h> |
22 | #include <asm/mmu.h> | |
23 | #include <asm/mmu_context.h> | |
24 | #include <asm/pgtable.h> | |
25 | #include <asm/tlbflush.h> | |
26 | #include <asm/tlb.h> | |
27 | #include <asm/cputable.h> | |
3c726f8d | 28 | #include <asm/udbg.h> |
71bf08b6 | 29 | #include <asm/kexec.h> |
60dbf438 | 30 | #include <asm/ppc-opcode.h> |
3c726f8d BH |
31 | |
32 | #ifdef DEBUG_LOW | |
33 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
34 | #else | |
35 | #define DBG_LOW(fmt...) | |
36 | #endif | |
1da177e4 | 37 | |
12f04f2b | 38 | #ifdef __BIG_ENDIAN__ |
1da177e4 | 39 | #define HPTE_LOCK_BIT 3 |
12f04f2b AB |
40 | #else |
41 | #define HPTE_LOCK_BIT (56+3) | |
42 | #endif | |
1da177e4 | 43 | |
9e368f29 | 44 | DEFINE_RAW_SPINLOCK(native_tlbie_lock); |
1da177e4 | 45 | |
b1022fbd | 46 | static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) |
3c726f8d | 47 | { |
5524a27d | 48 | unsigned long va; |
3c726f8d | 49 | unsigned int penc; |
de640959 | 50 | unsigned long sllp; |
3c726f8d | 51 | |
5524a27d AK |
52 | /* |
53 | * We need 14 to 65 bits of va for a tlibe of 4K page | |
54 | * With vpn we ignore the lower VPN_SHIFT bits already. | |
55 | * And top two bits are already ignored because we can | |
56 | * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT | |
57 | * of 12. | |
58 | */ | |
59 | va = vpn << VPN_SHIFT; | |
60 | /* | |
61 | * clear top 16 bits of 64bit va, non SLS segment | |
62 | * Older versions of the architecture (2.02 and earler) require the | |
63 | * masking of the top 16 bits. | |
64 | */ | |
3c726f8d BH |
65 | va &= ~(0xffffULL << 48); |
66 | ||
67 | switch (psize) { | |
68 | case MMU_PAGE_4K: | |
1f6aaacc AK |
69 | /* clear out bits after (52) [0....52.....63] */ |
70 | va &= ~((1ul << (64 - 52)) - 1); | |
1189be65 | 71 | va |= ssize << 8; |
de640959 AK |
72 | sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | |
73 | ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); | |
74 | va |= sllp << 5; | |
a32e252f | 75 | asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) |
969391c5 | 76 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 77 | : "memory"); |
3c726f8d BH |
78 | break; |
79 | default: | |
5524a27d | 80 | /* We need 14 to 14 + i bits of va */ |
b1022fbd | 81 | penc = mmu_psize_defs[psize].penc[apsize]; |
1f6aaacc | 82 | va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
19242b24 | 83 | va |= penc << 12; |
1189be65 | 84 | va |= ssize << 8; |
1f6aaacc AK |
85 | /* Add AVAL part */ |
86 | if (psize != apsize) { | |
87 | /* | |
88 | * MPSS, 64K base page size and 16MB parge page size | |
89 | * We don't need all the bits, but rest of the bits | |
90 | * must be ignored by the processor. | |
91 | * vpn cover upto 65 bits of va. (0...65) and we need | |
92 | * 58..64 bits of va. | |
93 | */ | |
94 | va |= (vpn & 0xfe); | |
95 | } | |
60dbf438 | 96 | va |= 1; /* L */ |
a32e252f | 97 | asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) |
969391c5 | 98 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
60dbf438 | 99 | : "memory"); |
3c726f8d BH |
100 | break; |
101 | } | |
102 | } | |
103 | ||
b1022fbd | 104 | static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) |
3c726f8d | 105 | { |
5524a27d | 106 | unsigned long va; |
3c726f8d | 107 | unsigned int penc; |
de640959 | 108 | unsigned long sllp; |
3c726f8d | 109 | |
5524a27d AK |
110 | /* VPN_SHIFT can be atmost 12 */ |
111 | va = vpn << VPN_SHIFT; | |
112 | /* | |
113 | * clear top 16 bits of 64 bit va, non SLS segment | |
114 | * Older versions of the architecture (2.02 and earler) require the | |
115 | * masking of the top 16 bits. | |
116 | */ | |
3c726f8d BH |
117 | va &= ~(0xffffULL << 48); |
118 | ||
119 | switch (psize) { | |
120 | case MMU_PAGE_4K: | |
1f6aaacc AK |
121 | /* clear out bits after(52) [0....52.....63] */ |
122 | va &= ~((1ul << (64 - 52)) - 1); | |
1189be65 | 123 | va |= ssize << 8; |
de640959 AK |
124 | sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | |
125 | ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); | |
126 | va |= sllp << 5; | |
3c726f8d BH |
127 | asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)" |
128 | : : "r"(va) : "memory"); | |
129 | break; | |
130 | default: | |
5524a27d | 131 | /* We need 14 to 14 + i bits of va */ |
b1022fbd | 132 | penc = mmu_psize_defs[psize].penc[apsize]; |
1f6aaacc | 133 | va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); |
19242b24 | 134 | va |= penc << 12; |
1189be65 | 135 | va |= ssize << 8; |
1f6aaacc AK |
136 | /* Add AVAL part */ |
137 | if (psize != apsize) { | |
138 | /* | |
139 | * MPSS, 64K base page size and 16MB parge page size | |
140 | * We don't need all the bits, but rest of the bits | |
141 | * must be ignored by the processor. | |
142 | * vpn cover upto 65 bits of va. (0...65) and we need | |
143 | * 58..64 bits of va. | |
144 | */ | |
145 | va |= (vpn & 0xfe); | |
146 | } | |
60dbf438 | 147 | va |= 1; /* L */ |
3c726f8d BH |
148 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" |
149 | : : "r"(va) : "memory"); | |
150 | break; | |
151 | } | |
152 | ||
153 | } | |
154 | ||
b1022fbd AK |
155 | static inline void tlbie(unsigned long vpn, int psize, int apsize, |
156 | int ssize, int local) | |
3c726f8d | 157 | { |
44ae3ab3 ME |
158 | unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL); |
159 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
3c726f8d BH |
160 | |
161 | if (use_local) | |
162 | use_local = mmu_psize_defs[psize].tlbiel; | |
163 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 164 | raw_spin_lock(&native_tlbie_lock); |
3c726f8d BH |
165 | asm volatile("ptesync": : :"memory"); |
166 | if (use_local) { | |
b1022fbd | 167 | __tlbiel(vpn, psize, apsize, ssize); |
3c726f8d BH |
168 | asm volatile("ptesync": : :"memory"); |
169 | } else { | |
b1022fbd | 170 | __tlbie(vpn, psize, apsize, ssize); |
3c726f8d BH |
171 | asm volatile("eieio; tlbsync; ptesync": : :"memory"); |
172 | } | |
173 | if (lock_tlbie && !use_local) | |
6b9c9b8a | 174 | raw_spin_unlock(&native_tlbie_lock); |
3c726f8d BH |
175 | } |
176 | ||
8e561e7e | 177 | static inline void native_lock_hpte(struct hash_pte *hptep) |
1da177e4 | 178 | { |
12f04f2b | 179 | unsigned long *word = (unsigned long *)&hptep->v; |
1da177e4 LT |
180 | |
181 | while (1) { | |
66d99b88 | 182 | if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word)) |
1da177e4 LT |
183 | break; |
184 | while(test_bit(HPTE_LOCK_BIT, word)) | |
185 | cpu_relax(); | |
186 | } | |
187 | } | |
188 | ||
8e561e7e | 189 | static inline void native_unlock_hpte(struct hash_pte *hptep) |
1da177e4 | 190 | { |
12f04f2b | 191 | unsigned long *word = (unsigned long *)&hptep->v; |
1da177e4 | 192 | |
66d99b88 | 193 | clear_bit_unlock(HPTE_LOCK_BIT, word); |
1da177e4 LT |
194 | } |
195 | ||
5524a27d | 196 | static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn, |
3c726f8d | 197 | unsigned long pa, unsigned long rflags, |
b1022fbd | 198 | unsigned long vflags, int psize, int apsize, int ssize) |
1da177e4 | 199 | { |
8e561e7e | 200 | struct hash_pte *hptep = htab_address + hpte_group; |
96e28449 | 201 | unsigned long hpte_v, hpte_r; |
1da177e4 LT |
202 | int i; |
203 | ||
3c726f8d | 204 | if (!(vflags & HPTE_V_BOLTED)) { |
5524a27d | 205 | DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx," |
3c726f8d | 206 | " rflags=%lx, vflags=%lx, psize=%d)\n", |
5524a27d | 207 | hpte_group, vpn, pa, rflags, vflags, psize); |
3c726f8d BH |
208 | } |
209 | ||
1da177e4 | 210 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
12f04f2b | 211 | if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) { |
1da177e4 LT |
212 | /* retry with lock held */ |
213 | native_lock_hpte(hptep); | |
12f04f2b | 214 | if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) |
1da177e4 LT |
215 | break; |
216 | native_unlock_hpte(hptep); | |
217 | } | |
218 | ||
219 | hptep++; | |
220 | } | |
221 | ||
222 | if (i == HPTES_PER_GROUP) | |
223 | return -1; | |
224 | ||
b1022fbd AK |
225 | hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID; |
226 | hpte_r = hpte_encode_r(pa, psize, apsize) | rflags; | |
3c726f8d BH |
227 | |
228 | if (!(vflags & HPTE_V_BOLTED)) { | |
229 | DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n", | |
230 | i, hpte_v, hpte_r); | |
231 | } | |
1da177e4 | 232 | |
12f04f2b | 233 | hptep->r = cpu_to_be64(hpte_r); |
1da177e4 | 234 | /* Guarantee the second dword is visible before the valid bit */ |
74a0ba61 | 235 | eieio(); |
1da177e4 LT |
236 | /* |
237 | * Now set the first dword including the valid bit | |
238 | * NOTE: this also unlocks the hpte | |
239 | */ | |
12f04f2b | 240 | hptep->v = cpu_to_be64(hpte_v); |
1da177e4 LT |
241 | |
242 | __asm__ __volatile__ ("ptesync" : : : "memory"); | |
243 | ||
96e28449 | 244 | return i | (!!(vflags & HPTE_V_SECONDARY) << 3); |
1da177e4 LT |
245 | } |
246 | ||
247 | static long native_hpte_remove(unsigned long hpte_group) | |
248 | { | |
8e561e7e | 249 | struct hash_pte *hptep; |
1da177e4 LT |
250 | int i; |
251 | int slot_offset; | |
96e28449 | 252 | unsigned long hpte_v; |
1da177e4 | 253 | |
3c726f8d BH |
254 | DBG_LOW(" remove(group=%lx)\n", hpte_group); |
255 | ||
1da177e4 LT |
256 | /* pick a random entry to start at */ |
257 | slot_offset = mftb() & 0x7; | |
258 | ||
259 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
260 | hptep = htab_address + hpte_group + slot_offset; | |
12f04f2b | 261 | hpte_v = be64_to_cpu(hptep->v); |
1da177e4 | 262 | |
96e28449 | 263 | if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) { |
1da177e4 LT |
264 | /* retry with lock held */ |
265 | native_lock_hpte(hptep); | |
12f04f2b | 266 | hpte_v = be64_to_cpu(hptep->v); |
96e28449 DG |
267 | if ((hpte_v & HPTE_V_VALID) |
268 | && !(hpte_v & HPTE_V_BOLTED)) | |
1da177e4 LT |
269 | break; |
270 | native_unlock_hpte(hptep); | |
271 | } | |
272 | ||
273 | slot_offset++; | |
274 | slot_offset &= 0x7; | |
275 | } | |
276 | ||
277 | if (i == HPTES_PER_GROUP) | |
278 | return -1; | |
279 | ||
280 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
96e28449 | 281 | hptep->v = 0; |
1da177e4 LT |
282 | |
283 | return i; | |
284 | } | |
285 | ||
3c726f8d | 286 | static long native_hpte_updatepp(unsigned long slot, unsigned long newpp, |
db3d8534 AK |
287 | unsigned long vpn, int bpsize, |
288 | int apsize, int ssize, int local) | |
1da177e4 | 289 | { |
8e561e7e | 290 | struct hash_pte *hptep = htab_address + slot; |
3c726f8d BH |
291 | unsigned long hpte_v, want_v; |
292 | int ret = 0; | |
293 | ||
db3d8534 | 294 | want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
3c726f8d | 295 | |
5524a27d AK |
296 | DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)", |
297 | vpn, want_v & HPTE_V_AVPN, slot, newpp); | |
3c726f8d BH |
298 | |
299 | native_lock_hpte(hptep); | |
300 | ||
12f04f2b | 301 | hpte_v = be64_to_cpu(hptep->v); |
0608d692 AK |
302 | /* |
303 | * We need to invalidate the TLB always because hpte_remove doesn't do | |
304 | * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less | |
305 | * random entry from it. When we do that we don't invalidate the TLB | |
306 | * (hpte_remove) because we assume the old translation is still | |
307 | * technically "valid". | |
308 | */ | |
db3d8534 | 309 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) { |
3c726f8d | 310 | DBG_LOW(" -> miss\n"); |
3c726f8d BH |
311 | ret = -1; |
312 | } else { | |
313 | DBG_LOW(" -> hit\n"); | |
314 | /* Update the HPTE */ | |
12f04f2b AB |
315 | hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) & ~(HPTE_R_PP | HPTE_R_N)) | |
316 | (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C))); | |
3c726f8d | 317 | } |
3f1df7a2 | 318 | native_unlock_hpte(hptep); |
3c726f8d BH |
319 | |
320 | /* Ensure it is out of the tlb too. */ | |
db3d8534 | 321 | tlbie(vpn, bpsize, apsize, ssize, local); |
3c726f8d BH |
322 | |
323 | return ret; | |
1da177e4 LT |
324 | } |
325 | ||
5524a27d | 326 | static long native_hpte_find(unsigned long vpn, int psize, int ssize) |
1da177e4 | 327 | { |
8e561e7e | 328 | struct hash_pte *hptep; |
1da177e4 | 329 | unsigned long hash; |
1189be65 | 330 | unsigned long i; |
1da177e4 | 331 | long slot; |
3c726f8d | 332 | unsigned long want_v, hpte_v; |
1da177e4 | 333 | |
5524a27d | 334 | hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize); |
74f227b2 | 335 | want_v = hpte_encode_avpn(vpn, psize, ssize); |
1da177e4 | 336 | |
1189be65 PM |
337 | /* Bolted mappings are only ever in the primary group */ |
338 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
339 | for (i = 0; i < HPTES_PER_GROUP; i++) { | |
340 | hptep = htab_address + slot; | |
12f04f2b | 341 | hpte_v = be64_to_cpu(hptep->v); |
1da177e4 | 342 | |
1189be65 PM |
343 | if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) |
344 | /* HPTE matches */ | |
345 | return slot; | |
346 | ++slot; | |
1da177e4 LT |
347 | } |
348 | ||
349 | return -1; | |
350 | } | |
351 | ||
1da177e4 LT |
352 | /* |
353 | * Update the page protection bits. Intended to be used to create | |
354 | * guard pages for kernel data structures on pages which are bolted | |
355 | * in the HPT. Assumes pages being operated on will not be stolen. | |
1da177e4 LT |
356 | * |
357 | * No need to lock here because we should be the only user. | |
358 | */ | |
3c726f8d | 359 | static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea, |
1189be65 | 360 | int psize, int ssize) |
1da177e4 | 361 | { |
5524a27d AK |
362 | unsigned long vpn; |
363 | unsigned long vsid; | |
1da177e4 | 364 | long slot; |
8e561e7e | 365 | struct hash_pte *hptep; |
1da177e4 | 366 | |
1189be65 | 367 | vsid = get_kernel_vsid(ea, ssize); |
5524a27d | 368 | vpn = hpt_vpn(ea, vsid, ssize); |
1da177e4 | 369 | |
5524a27d | 370 | slot = native_hpte_find(vpn, psize, ssize); |
1da177e4 LT |
371 | if (slot == -1) |
372 | panic("could not find page to bolt\n"); | |
373 | hptep = htab_address + slot; | |
374 | ||
3c726f8d | 375 | /* Update the HPTE */ |
12f04f2b AB |
376 | hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) & |
377 | ~(HPTE_R_PP | HPTE_R_N)) | | |
378 | (newpp & (HPTE_R_PP | HPTE_R_N))); | |
db3d8534 AK |
379 | /* |
380 | * Ensure it is out of the tlb too. Bolted entries base and | |
381 | * actual page size will be same. | |
382 | */ | |
383 | tlbie(vpn, psize, psize, ssize, 0); | |
1da177e4 LT |
384 | } |
385 | ||
5524a27d | 386 | static void native_hpte_invalidate(unsigned long slot, unsigned long vpn, |
db3d8534 | 387 | int bpsize, int apsize, int ssize, int local) |
1da177e4 | 388 | { |
8e561e7e | 389 | struct hash_pte *hptep = htab_address + slot; |
96e28449 | 390 | unsigned long hpte_v; |
3c726f8d | 391 | unsigned long want_v; |
1da177e4 | 392 | unsigned long flags; |
1da177e4 LT |
393 | |
394 | local_irq_save(flags); | |
1da177e4 | 395 | |
5524a27d | 396 | DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot); |
3c726f8d | 397 | |
db3d8534 | 398 | want_v = hpte_encode_avpn(vpn, bpsize, ssize); |
3c726f8d | 399 | native_lock_hpte(hptep); |
12f04f2b | 400 | hpte_v = be64_to_cpu(hptep->v); |
1da177e4 | 401 | |
0608d692 AK |
402 | /* |
403 | * We need to invalidate the TLB always because hpte_remove doesn't do | |
404 | * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less | |
405 | * random entry from it. When we do that we don't invalidate the TLB | |
406 | * (hpte_remove) because we assume the old translation is still | |
407 | * technically "valid". | |
408 | */ | |
db3d8534 | 409 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) |
1da177e4 | 410 | native_unlock_hpte(hptep); |
3c726f8d | 411 | else |
1da177e4 | 412 | /* Invalidate the hpte. NOTE: this also unlocks it */ |
96e28449 | 413 | hptep->v = 0; |
1da177e4 | 414 | |
3c726f8d | 415 | /* Invalidate the TLB */ |
db3d8534 AK |
416 | tlbie(vpn, bpsize, apsize, ssize, local); |
417 | ||
1da177e4 LT |
418 | local_irq_restore(flags); |
419 | } | |
420 | ||
1a527286 AK |
421 | static void native_hugepage_invalidate(struct mm_struct *mm, |
422 | unsigned char *hpte_slot_array, | |
423 | unsigned long addr, int psize) | |
424 | { | |
425 | int ssize = 0, i; | |
426 | int lock_tlbie; | |
427 | struct hash_pte *hptep; | |
428 | int actual_psize = MMU_PAGE_16M; | |
429 | unsigned int max_hpte_count, valid; | |
430 | unsigned long flags, s_addr = addr; | |
431 | unsigned long hpte_v, want_v, shift; | |
432 | unsigned long hidx, vpn = 0, vsid, hash, slot; | |
433 | ||
434 | shift = mmu_psize_defs[psize].shift; | |
435 | max_hpte_count = 1U << (PMD_SHIFT - shift); | |
436 | ||
437 | local_irq_save(flags); | |
438 | for (i = 0; i < max_hpte_count; i++) { | |
439 | valid = hpte_valid(hpte_slot_array, i); | |
440 | if (!valid) | |
441 | continue; | |
442 | hidx = hpte_hash_index(hpte_slot_array, i); | |
443 | ||
444 | /* get the vpn */ | |
445 | addr = s_addr + (i * (1ul << shift)); | |
446 | if (!is_kernel_addr(addr)) { | |
447 | ssize = user_segment_size(addr); | |
448 | vsid = get_vsid(mm->context.id, addr, ssize); | |
449 | WARN_ON(vsid == 0); | |
450 | } else { | |
451 | vsid = get_kernel_vsid(addr, mmu_kernel_ssize); | |
452 | ssize = mmu_kernel_ssize; | |
453 | } | |
454 | ||
455 | vpn = hpt_vpn(addr, vsid, ssize); | |
456 | hash = hpt_hash(vpn, shift, ssize); | |
457 | if (hidx & _PTEIDX_SECONDARY) | |
458 | hash = ~hash; | |
459 | ||
460 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
461 | slot += hidx & _PTEIDX_GROUP_IX; | |
462 | ||
463 | hptep = htab_address + slot; | |
464 | want_v = hpte_encode_avpn(vpn, psize, ssize); | |
465 | native_lock_hpte(hptep); | |
12f04f2b | 466 | hpte_v = be64_to_cpu(hptep->v); |
1a527286 AK |
467 | |
468 | /* Even if we miss, we need to invalidate the TLB */ | |
469 | if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) | |
470 | native_unlock_hpte(hptep); | |
471 | else | |
472 | /* Invalidate the hpte. NOTE: this also unlocks it */ | |
473 | hptep->v = 0; | |
474 | } | |
475 | /* | |
476 | * Since this is a hugepage, we just need a single tlbie. | |
477 | * use the last vpn. | |
478 | */ | |
479 | lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); | |
480 | if (lock_tlbie) | |
481 | raw_spin_lock(&native_tlbie_lock); | |
482 | ||
483 | asm volatile("ptesync":::"memory"); | |
484 | __tlbie(vpn, psize, actual_psize, ssize); | |
485 | asm volatile("eieio; tlbsync; ptesync":::"memory"); | |
486 | ||
487 | if (lock_tlbie) | |
488 | raw_spin_unlock(&native_tlbie_lock); | |
489 | ||
490 | local_irq_restore(flags); | |
491 | } | |
492 | ||
db3d8534 AK |
493 | static inline int __hpte_actual_psize(unsigned int lp, int psize) |
494 | { | |
495 | int i, shift; | |
496 | unsigned int mask; | |
497 | ||
498 | /* start from 1 ignoring MMU_PAGE_4K */ | |
499 | for (i = 1; i < MMU_PAGE_COUNT; i++) { | |
500 | ||
501 | /* invalid penc */ | |
502 | if (mmu_psize_defs[psize].penc[i] == -1) | |
503 | continue; | |
504 | /* | |
505 | * encoding bits per actual page size | |
506 | * PTE LP actual page size | |
507 | * rrrr rrrz >=8KB | |
508 | * rrrr rrzz >=16KB | |
509 | * rrrr rzzz >=32KB | |
510 | * rrrr zzzz >=64KB | |
511 | * ....... | |
512 | */ | |
513 | shift = mmu_psize_defs[i].shift - LP_SHIFT; | |
514 | if (shift > LP_BITS) | |
515 | shift = LP_BITS; | |
516 | mask = (1 << shift) - 1; | |
517 | if ((lp & mask) == mmu_psize_defs[psize].penc[i]) | |
518 | return i; | |
519 | } | |
520 | return -1; | |
521 | } | |
522 | ||
8e561e7e | 523 | static void hpte_decode(struct hash_pte *hpte, unsigned long slot, |
b1022fbd | 524 | int *psize, int *apsize, int *ssize, unsigned long *vpn) |
71bf08b6 | 525 | { |
dcda287a | 526 | unsigned long avpn, pteg, vpi; |
12f04f2b AB |
527 | unsigned long hpte_v = be64_to_cpu(hpte->v); |
528 | unsigned long hpte_r = be64_to_cpu(hpte->r); | |
dcda287a | 529 | unsigned long vsid, seg_off; |
7e74c392 AK |
530 | int size, a_size, shift; |
531 | /* Look at the 8 bit LP value */ | |
12f04f2b | 532 | unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1); |
71bf08b6 | 533 | |
b1022fbd AK |
534 | if (!(hpte_v & HPTE_V_LARGE)) { |
535 | size = MMU_PAGE_4K; | |
536 | a_size = MMU_PAGE_4K; | |
537 | } else { | |
71bf08b6 | 538 | for (size = 0; size < MMU_PAGE_COUNT; size++) { |
3c726f8d | 539 | |
71bf08b6 LB |
540 | /* valid entries have a shift value */ |
541 | if (!mmu_psize_defs[size].shift) | |
542 | continue; | |
b1022fbd | 543 | |
7e74c392 AK |
544 | a_size = __hpte_actual_psize(lp, size); |
545 | if (a_size != -1) | |
546 | break; | |
71bf08b6 LB |
547 | } |
548 | } | |
2454c7e9 | 549 | /* This works for all page sizes, and for 256M and 1T segments */ |
dcda287a | 550 | *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT; |
71bf08b6 | 551 | shift = mmu_psize_defs[size].shift; |
71bf08b6 | 552 | |
dcda287a AK |
553 | avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm); |
554 | pteg = slot / HPTES_PER_GROUP; | |
555 | if (hpte_v & HPTE_V_SECONDARY) | |
556 | pteg = ~pteg; | |
557 | ||
558 | switch (*ssize) { | |
559 | case MMU_SEGSIZE_256M: | |
560 | /* We only have 28 - 23 bits of seg_off in avpn */ | |
561 | seg_off = (avpn & 0x1f) << 23; | |
562 | vsid = avpn >> 5; | |
563 | /* We can find more bits from the pteg value */ | |
564 | if (shift < 23) { | |
565 | vpi = (vsid ^ pteg) & htab_hash_mask; | |
566 | seg_off |= vpi << shift; | |
567 | } | |
5524a27d | 568 | *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
83383b73 | 569 | break; |
dcda287a AK |
570 | case MMU_SEGSIZE_1T: |
571 | /* We only have 40 - 23 bits of seg_off in avpn */ | |
572 | seg_off = (avpn & 0x1ffff) << 23; | |
573 | vsid = avpn >> 17; | |
574 | if (shift < 23) { | |
2454c7e9 | 575 | vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask; |
dcda287a | 576 | seg_off |= vpi << shift; |
71bf08b6 | 577 | } |
5524a27d | 578 | *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT; |
83383b73 | 579 | break; |
dcda287a | 580 | default: |
5524a27d | 581 | *vpn = size = 0; |
3c726f8d | 582 | } |
b1022fbd AK |
583 | *psize = size; |
584 | *apsize = a_size; | |
3c726f8d BH |
585 | } |
586 | ||
f4c82d51 S |
587 | /* |
588 | * clear all mappings on kexec. All cpus are in real mode (or they will | |
589 | * be when they isi), and we are the only one left. We rely on our kernel | |
590 | * mapping being 0xC0's and the hardware ignoring those two real bits. | |
591 | * | |
592 | * TODO: add batching support when enabled. remember, no dynamic memory here, | |
593 | * athough there is the control page available... | |
594 | */ | |
595 | static void native_hpte_clear(void) | |
596 | { | |
5524a27d | 597 | unsigned long vpn = 0; |
f4c82d51 | 598 | unsigned long slot, slots, flags; |
8e561e7e | 599 | struct hash_pte *hptep = htab_address; |
5524a27d | 600 | unsigned long hpte_v; |
f4c82d51 | 601 | unsigned long pteg_count; |
b1022fbd | 602 | int psize, apsize, ssize; |
f4c82d51 S |
603 | |
604 | pteg_count = htab_hash_mask + 1; | |
605 | ||
606 | local_irq_save(flags); | |
607 | ||
608 | /* we take the tlbie lock and hold it. Some hardware will | |
609 | * deadlock if we try to tlbie from two processors at once. | |
610 | */ | |
6b9c9b8a | 611 | raw_spin_lock(&native_tlbie_lock); |
f4c82d51 S |
612 | |
613 | slots = pteg_count * HPTES_PER_GROUP; | |
614 | ||
615 | for (slot = 0; slot < slots; slot++, hptep++) { | |
616 | /* | |
617 | * we could lock the pte here, but we are the only cpu | |
618 | * running, right? and for crash dump, we probably | |
619 | * don't want to wait for a maybe bad cpu. | |
620 | */ | |
12f04f2b | 621 | hpte_v = be64_to_cpu(hptep->v); |
f4c82d51 | 622 | |
47f78a49 S |
623 | /* |
624 | * Call __tlbie() here rather than tlbie() since we | |
625 | * already hold the native_tlbie_lock. | |
626 | */ | |
96e28449 | 627 | if (hpte_v & HPTE_V_VALID) { |
b1022fbd | 628 | hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn); |
96e28449 | 629 | hptep->v = 0; |
b1022fbd | 630 | __tlbie(vpn, psize, apsize, ssize); |
f4c82d51 S |
631 | } |
632 | } | |
633 | ||
47f78a49 | 634 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
6b9c9b8a | 635 | raw_spin_unlock(&native_tlbie_lock); |
f4c82d51 S |
636 | local_irq_restore(flags); |
637 | } | |
638 | ||
3c726f8d BH |
639 | /* |
640 | * Batched hash table flush, we batch the tlbie's to avoid taking/releasing | |
641 | * the lock all the time | |
642 | */ | |
61b1a942 | 643 | static void native_flush_hash_range(unsigned long number, int local) |
1da177e4 | 644 | { |
5524a27d AK |
645 | unsigned long vpn; |
646 | unsigned long hash, index, hidx, shift, slot; | |
8e561e7e | 647 | struct hash_pte *hptep; |
96e28449 | 648 | unsigned long hpte_v; |
3c726f8d BH |
649 | unsigned long want_v; |
650 | unsigned long flags; | |
651 | real_pte_t pte; | |
1da177e4 | 652 | struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); |
3c726f8d | 653 | unsigned long psize = batch->psize; |
1189be65 | 654 | int ssize = batch->ssize; |
3c726f8d | 655 | int i; |
1da177e4 LT |
656 | |
657 | local_irq_save(flags); | |
658 | ||
1da177e4 | 659 | for (i = 0; i < number; i++) { |
5524a27d | 660 | vpn = batch->vpn[i]; |
3c726f8d BH |
661 | pte = batch->pte[i]; |
662 | ||
5524a27d AK |
663 | pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) { |
664 | hash = hpt_hash(vpn, shift, ssize); | |
3c726f8d BH |
665 | hidx = __rpte_to_hidx(pte, index); |
666 | if (hidx & _PTEIDX_SECONDARY) | |
667 | hash = ~hash; | |
668 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
669 | slot += hidx & _PTEIDX_GROUP_IX; | |
670 | hptep = htab_address + slot; | |
74f227b2 | 671 | want_v = hpte_encode_avpn(vpn, psize, ssize); |
3c726f8d | 672 | native_lock_hpte(hptep); |
12f04f2b | 673 | hpte_v = be64_to_cpu(hptep->v); |
3c726f8d BH |
674 | if (!HPTE_V_COMPARE(hpte_v, want_v) || |
675 | !(hpte_v & HPTE_V_VALID)) | |
676 | native_unlock_hpte(hptep); | |
677 | else | |
678 | hptep->v = 0; | |
679 | } pte_iterate_hashed_end(); | |
1da177e4 LT |
680 | } |
681 | ||
44ae3ab3 | 682 | if (mmu_has_feature(MMU_FTR_TLBIEL) && |
3c726f8d | 683 | mmu_psize_defs[psize].tlbiel && local) { |
1da177e4 | 684 | asm volatile("ptesync":::"memory"); |
3c726f8d | 685 | for (i = 0; i < number; i++) { |
5524a27d | 686 | vpn = batch->vpn[i]; |
3c726f8d BH |
687 | pte = batch->pte[i]; |
688 | ||
5524a27d AK |
689 | pte_iterate_hashed_subpages(pte, psize, |
690 | vpn, index, shift) { | |
b1022fbd | 691 | __tlbiel(vpn, psize, psize, ssize); |
3c726f8d BH |
692 | } pte_iterate_hashed_end(); |
693 | } | |
1da177e4 LT |
694 | asm volatile("ptesync":::"memory"); |
695 | } else { | |
44ae3ab3 | 696 | int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); |
1da177e4 LT |
697 | |
698 | if (lock_tlbie) | |
6b9c9b8a | 699 | raw_spin_lock(&native_tlbie_lock); |
1da177e4 LT |
700 | |
701 | asm volatile("ptesync":::"memory"); | |
3c726f8d | 702 | for (i = 0; i < number; i++) { |
5524a27d | 703 | vpn = batch->vpn[i]; |
3c726f8d BH |
704 | pte = batch->pte[i]; |
705 | ||
5524a27d AK |
706 | pte_iterate_hashed_subpages(pte, psize, |
707 | vpn, index, shift) { | |
b1022fbd | 708 | __tlbie(vpn, psize, psize, ssize); |
3c726f8d BH |
709 | } pte_iterate_hashed_end(); |
710 | } | |
1da177e4 LT |
711 | asm volatile("eieio; tlbsync; ptesync":::"memory"); |
712 | ||
713 | if (lock_tlbie) | |
6b9c9b8a | 714 | raw_spin_unlock(&native_tlbie_lock); |
1da177e4 LT |
715 | } |
716 | ||
717 | local_irq_restore(flags); | |
718 | } | |
719 | ||
7d0daae4 | 720 | void __init hpte_init_native(void) |
1da177e4 LT |
721 | { |
722 | ppc_md.hpte_invalidate = native_hpte_invalidate; | |
723 | ppc_md.hpte_updatepp = native_hpte_updatepp; | |
724 | ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp; | |
725 | ppc_md.hpte_insert = native_hpte_insert; | |
f4c82d51 S |
726 | ppc_md.hpte_remove = native_hpte_remove; |
727 | ppc_md.hpte_clear_all = native_hpte_clear; | |
8e166991 | 728 | ppc_md.flush_hash_range = native_flush_hash_range; |
1a527286 | 729 | ppc_md.hugepage_invalidate = native_hugepage_invalidate; |
1da177e4 | 730 | } |