Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2bfd65e4 AK |
2 | /* |
3 | * Page table handling routines for radix page table. | |
4 | * | |
5 | * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation. | |
2bfd65e4 | 6 | */ |
bd350f71 ME |
7 | |
8 | #define pr_fmt(fmt) "radix-mmu: " fmt | |
9 | ||
d38153f9 | 10 | #include <linux/io.h> |
bd350f71 | 11 | #include <linux/kernel.h> |
589ee628 | 12 | #include <linux/sched/mm.h> |
2bfd65e4 AK |
13 | #include <linux/memblock.h> |
14 | #include <linux/of_fdt.h> | |
7614ff32 | 15 | #include <linux/mm.h> |
6deb6b47 | 16 | #include <linux/string_helpers.h> |
4dd5f8a9 | 17 | #include <linux/stop_machine.h> |
2bfd65e4 AK |
18 | |
19 | #include <asm/pgtable.h> | |
20 | #include <asm/pgalloc.h> | |
eeb715c3 | 21 | #include <asm/mmu_context.h> |
2bfd65e4 AK |
22 | #include <asm/dma.h> |
23 | #include <asm/machdep.h> | |
24 | #include <asm/mmu.h> | |
25 | #include <asm/firmware.h> | |
1d0761d2 | 26 | #include <asm/powernv.h> |
9abcc981 | 27 | #include <asm/sections.h> |
0428491c | 28 | #include <asm/trace.h> |
890274c2 | 29 | #include <asm/uaccess.h> |
2bfd65e4 | 30 | |
bde3eb62 AK |
31 | #include <trace/events/thp.h> |
32 | ||
a25bd72b BH |
33 | unsigned int mmu_pid_bits; |
34 | unsigned int mmu_base_pid; | |
35 | ||
83209bc8 AK |
36 | static int native_register_process_table(unsigned long base, unsigned long pg_sz, |
37 | unsigned long table_size) | |
2bfd65e4 | 38 | { |
7cd2a869 SJS |
39 | unsigned long patb0, patb1; |
40 | ||
41 | patb0 = be64_to_cpu(partition_tb[0].patb0); | |
42 | patb1 = base | table_size | PATB_GR; | |
43 | ||
44 | mmu_partition_table_set_entry(0, patb0, patb1); | |
83209bc8 | 45 | |
2bfd65e4 AK |
46 | return 0; |
47 | } | |
48 | ||
2ad452ff NP |
49 | static __ref void *early_alloc_pgtable(unsigned long size, int nid, |
50 | unsigned long region_start, unsigned long region_end) | |
2bfd65e4 | 51 | { |
f806714f MR |
52 | phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT; |
53 | phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE; | |
8a7f97b9 | 54 | void *ptr; |
2bfd65e4 | 55 | |
f806714f MR |
56 | if (region_start) |
57 | min_addr = region_start; | |
58 | if (region_end) | |
59 | max_addr = region_end; | |
2ad452ff | 60 | |
8a7f97b9 MR |
61 | ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid); |
62 | ||
63 | if (!ptr) | |
64 | panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n", | |
65 | __func__, size, size, nid, &min_addr, &max_addr); | |
66 | ||
67 | return ptr; | |
2bfd65e4 AK |
68 | } |
69 | ||
0633dafc | 70 | static int early_map_kernel_page(unsigned long ea, unsigned long pa, |
2bfd65e4 | 71 | pgprot_t flags, |
2ad452ff NP |
72 | unsigned int map_page_size, |
73 | int nid, | |
74 | unsigned long region_start, unsigned long region_end) | |
2bfd65e4 | 75 | { |
2ad452ff | 76 | unsigned long pfn = pa >> PAGE_SHIFT; |
0633dafc NP |
77 | pgd_t *pgdp; |
78 | pud_t *pudp; | |
79 | pmd_t *pmdp; | |
80 | pte_t *ptep; | |
81 | ||
82 | pgdp = pgd_offset_k(ea); | |
83 | if (pgd_none(*pgdp)) { | |
2ad452ff NP |
84 | pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid, |
85 | region_start, region_end); | |
0633dafc NP |
86 | pgd_populate(&init_mm, pgdp, pudp); |
87 | } | |
88 | pudp = pud_offset(pgdp, ea); | |
89 | if (map_page_size == PUD_SIZE) { | |
90 | ptep = (pte_t *)pudp; | |
91 | goto set_the_pte; | |
92 | } | |
93 | if (pud_none(*pudp)) { | |
2ad452ff NP |
94 | pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid, |
95 | region_start, region_end); | |
0633dafc NP |
96 | pud_populate(&init_mm, pudp, pmdp); |
97 | } | |
98 | pmdp = pmd_offset(pudp, ea); | |
99 | if (map_page_size == PMD_SIZE) { | |
100 | ptep = pmdp_ptep(pmdp); | |
101 | goto set_the_pte; | |
102 | } | |
103 | if (!pmd_present(*pmdp)) { | |
2ad452ff NP |
104 | ptep = early_alloc_pgtable(PAGE_SIZE, nid, |
105 | region_start, region_end); | |
0633dafc NP |
106 | pmd_populate_kernel(&init_mm, pmdp, ptep); |
107 | } | |
108 | ptep = pte_offset_kernel(pmdp, ea); | |
109 | ||
110 | set_the_pte: | |
2ad452ff | 111 | set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags)); |
0633dafc NP |
112 | smp_wmb(); |
113 | return 0; | |
114 | } | |
115 | ||
2ad452ff NP |
116 | /* |
117 | * nid, region_start, and region_end are hints to try to place the page | |
118 | * table memory in the same node or region. | |
119 | */ | |
120 | static int __map_kernel_page(unsigned long ea, unsigned long pa, | |
2bfd65e4 | 121 | pgprot_t flags, |
2ad452ff NP |
122 | unsigned int map_page_size, |
123 | int nid, | |
124 | unsigned long region_start, unsigned long region_end) | |
2bfd65e4 | 125 | { |
2ad452ff | 126 | unsigned long pfn = pa >> PAGE_SHIFT; |
2bfd65e4 AK |
127 | pgd_t *pgdp; |
128 | pud_t *pudp; | |
129 | pmd_t *pmdp; | |
130 | pte_t *ptep; | |
131 | /* | |
132 | * Make sure task size is correct as per the max adddr | |
133 | */ | |
134 | BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE); | |
0633dafc | 135 | |
0034d395 AK |
136 | #ifdef CONFIG_PPC_64K_PAGES |
137 | BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT)); | |
138 | #endif | |
139 | ||
2ad452ff NP |
140 | if (unlikely(!slab_is_available())) |
141 | return early_map_kernel_page(ea, pa, flags, map_page_size, | |
142 | nid, region_start, region_end); | |
0633dafc | 143 | |
2ad452ff NP |
144 | /* |
145 | * Should make page table allocation functions be able to take a | |
146 | * node, so we can place kernel page tables on the right nodes after | |
147 | * boot. | |
148 | */ | |
0633dafc NP |
149 | pgdp = pgd_offset_k(ea); |
150 | pudp = pud_alloc(&init_mm, pgdp, ea); | |
151 | if (!pudp) | |
152 | return -ENOMEM; | |
153 | if (map_page_size == PUD_SIZE) { | |
154 | ptep = (pte_t *)pudp; | |
155 | goto set_the_pte; | |
2bfd65e4 | 156 | } |
0633dafc NP |
157 | pmdp = pmd_alloc(&init_mm, pudp, ea); |
158 | if (!pmdp) | |
159 | return -ENOMEM; | |
160 | if (map_page_size == PMD_SIZE) { | |
161 | ptep = pmdp_ptep(pmdp); | |
162 | goto set_the_pte; | |
2bfd65e4 | 163 | } |
0633dafc NP |
164 | ptep = pte_alloc_kernel(pmdp, ea); |
165 | if (!ptep) | |
166 | return -ENOMEM; | |
2bfd65e4 AK |
167 | |
168 | set_the_pte: | |
2ad452ff | 169 | set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags)); |
2bfd65e4 AK |
170 | smp_wmb(); |
171 | return 0; | |
172 | } | |
173 | ||
2ad452ff NP |
174 | int radix__map_kernel_page(unsigned long ea, unsigned long pa, |
175 | pgprot_t flags, | |
176 | unsigned int map_page_size) | |
177 | { | |
178 | return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0); | |
179 | } | |
180 | ||
7614ff32 | 181 | #ifdef CONFIG_STRICT_KERNEL_RWX |
b134bd90 ME |
182 | void radix__change_memory_range(unsigned long start, unsigned long end, |
183 | unsigned long clear) | |
7614ff32 | 184 | { |
7614ff32 BS |
185 | unsigned long idx; |
186 | pgd_t *pgdp; | |
187 | pud_t *pudp; | |
188 | pmd_t *pmdp; | |
189 | pte_t *ptep; | |
190 | ||
191 | start = ALIGN_DOWN(start, PAGE_SIZE); | |
192 | end = PAGE_ALIGN(end); // aligns up | |
193 | ||
b134bd90 ME |
194 | pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n", |
195 | start, end, clear); | |
7614ff32 BS |
196 | |
197 | for (idx = start; idx < end; idx += PAGE_SIZE) { | |
198 | pgdp = pgd_offset_k(idx); | |
199 | pudp = pud_alloc(&init_mm, pgdp, idx); | |
200 | if (!pudp) | |
201 | continue; | |
d6eacedd | 202 | if (pud_is_leaf(*pudp)) { |
7614ff32 BS |
203 | ptep = (pte_t *)pudp; |
204 | goto update_the_pte; | |
205 | } | |
206 | pmdp = pmd_alloc(&init_mm, pudp, idx); | |
207 | if (!pmdp) | |
208 | continue; | |
d6eacedd | 209 | if (pmd_is_leaf(*pmdp)) { |
7614ff32 BS |
210 | ptep = pmdp_ptep(pmdp); |
211 | goto update_the_pte; | |
212 | } | |
213 | ptep = pte_alloc_kernel(pmdp, idx); | |
214 | if (!ptep) | |
215 | continue; | |
216 | update_the_pte: | |
b134bd90 | 217 | radix__pte_update(&init_mm, idx, ptep, clear, 0, 0); |
7614ff32 BS |
218 | } |
219 | ||
220 | radix__flush_tlb_kernel_range(start, end); | |
221 | } | |
b134bd90 ME |
222 | |
223 | void radix__mark_rodata_ro(void) | |
224 | { | |
225 | unsigned long start, end; | |
226 | ||
227 | start = (unsigned long)_stext; | |
228 | end = (unsigned long)__init_begin; | |
229 | ||
230 | radix__change_memory_range(start, end, _PAGE_WRITE); | |
231 | } | |
029d9252 ME |
232 | |
233 | void radix__mark_initmem_nx(void) | |
234 | { | |
235 | unsigned long start = (unsigned long)__init_begin; | |
236 | unsigned long end = (unsigned long)__init_end; | |
237 | ||
238 | radix__change_memory_range(start, end, _PAGE_EXEC); | |
239 | } | |
7614ff32 BS |
240 | #endif /* CONFIG_STRICT_KERNEL_RWX */ |
241 | ||
afb6d064 ME |
242 | static inline void __meminit |
243 | print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec) | |
b5200ec9 | 244 | { |
6deb6b47 ME |
245 | char buf[10]; |
246 | ||
b5200ec9 RA |
247 | if (end <= start) |
248 | return; | |
249 | ||
6deb6b47 ME |
250 | string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf)); |
251 | ||
afb6d064 ME |
252 | pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf, |
253 | exec ? " (exec)" : ""); | |
b5200ec9 RA |
254 | } |
255 | ||
232aa407 ME |
256 | static unsigned long next_boundary(unsigned long addr, unsigned long end) |
257 | { | |
258 | #ifdef CONFIG_STRICT_KERNEL_RWX | |
259 | if (addr < __pa_symbol(__init_begin)) | |
260 | return __pa_symbol(__init_begin); | |
261 | #endif | |
262 | return end; | |
263 | } | |
264 | ||
b5200ec9 | 265 | static int __meminit create_physical_mapping(unsigned long start, |
2ad452ff NP |
266 | unsigned long end, |
267 | int nid) | |
b5200ec9 | 268 | { |
9abcc981 | 269 | unsigned long vaddr, addr, mapping_size = 0; |
afb6d064 | 270 | bool prev_exec, exec = false; |
9abcc981 | 271 | pgprot_t prot; |
a2dc009a | 272 | int psize; |
b5200ec9 RA |
273 | |
274 | start = _ALIGN_UP(start, PAGE_SIZE); | |
275 | for (addr = start; addr < end; addr += mapping_size) { | |
276 | unsigned long gap, previous_size; | |
277 | int rc; | |
278 | ||
232aa407 | 279 | gap = next_boundary(addr, end) - addr; |
b5200ec9 | 280 | previous_size = mapping_size; |
afb6d064 | 281 | prev_exec = exec; |
b5200ec9 RA |
282 | |
283 | if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE && | |
57306c66 | 284 | mmu_psize_defs[MMU_PAGE_1G].shift) { |
b5200ec9 | 285 | mapping_size = PUD_SIZE; |
a2dc009a AK |
286 | psize = MMU_PAGE_1G; |
287 | } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE && | |
288 | mmu_psize_defs[MMU_PAGE_2M].shift) { | |
b5200ec9 | 289 | mapping_size = PMD_SIZE; |
a2dc009a AK |
290 | psize = MMU_PAGE_2M; |
291 | } else { | |
b5200ec9 | 292 | mapping_size = PAGE_SIZE; |
a2dc009a AK |
293 | psize = mmu_virtual_psize; |
294 | } | |
7614ff32 | 295 | |
9abcc981 ME |
296 | vaddr = (unsigned long)__va(addr); |
297 | ||
7f6d498e | 298 | if (overlaps_kernel_text(vaddr, vaddr + mapping_size) || |
afb6d064 | 299 | overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) { |
9abcc981 | 300 | prot = PAGE_KERNEL_X; |
afb6d064 ME |
301 | exec = true; |
302 | } else { | |
9abcc981 | 303 | prot = PAGE_KERNEL; |
afb6d064 ME |
304 | exec = false; |
305 | } | |
306 | ||
307 | if (mapping_size != previous_size || exec != prev_exec) { | |
308 | print_mapping(start, addr, previous_size, prev_exec); | |
309 | start = addr; | |
310 | } | |
9abcc981 | 311 | |
2ad452ff | 312 | rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end); |
b5200ec9 RA |
313 | if (rc) |
314 | return rc; | |
a2dc009a AK |
315 | |
316 | update_page_count(psize, 1); | |
b5200ec9 RA |
317 | } |
318 | ||
afb6d064 | 319 | print_mapping(start, addr, mapping_size, exec); |
b5200ec9 RA |
320 | return 0; |
321 | } | |
322 | ||
d667edc0 | 323 | static void __init radix_init_pgtable(void) |
2bfd65e4 | 324 | { |
2bfd65e4 AK |
325 | unsigned long rts_field; |
326 | struct memblock_region *reg; | |
2bfd65e4 AK |
327 | |
328 | /* We don't support slb for radix */ | |
329 | mmu_slb_size = 0; | |
330 | /* | |
331 | * Create the linear mapping, using standard page size for now | |
332 | */ | |
2ad452ff NP |
333 | for_each_memblock(memory, reg) { |
334 | /* | |
335 | * The memblock allocator is up at this point, so the | |
336 | * page tables will be allocated within the range. No | |
337 | * need or a node (which we don't have yet). | |
338 | */ | |
e0909392 AK |
339 | |
340 | if ((reg->base + reg->size) >= RADIX_VMALLOC_START) { | |
f341d897 | 341 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
342 | continue; |
343 | } | |
344 | ||
b5200ec9 | 345 | WARN_ON(create_physical_mapping(reg->base, |
2ad452ff NP |
346 | reg->base + reg->size, |
347 | -1)); | |
348 | } | |
a25bd72b BH |
349 | |
350 | /* Find out how many PID bits are supported */ | |
351 | if (cpu_has_feature(CPU_FTR_HVMODE)) { | |
352 | if (!mmu_pid_bits) | |
353 | mmu_pid_bits = 20; | |
354 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE | |
355 | /* | |
356 | * When KVM is possible, we only use the top half of the | |
357 | * PID space to avoid collisions between host and guest PIDs | |
358 | * which can cause problems due to prefetch when exiting the | |
359 | * guest with AIL=3 | |
360 | */ | |
361 | mmu_base_pid = 1 << (mmu_pid_bits - 1); | |
362 | #else | |
363 | mmu_base_pid = 1; | |
364 | #endif | |
365 | } else { | |
366 | /* The guest uses the bottom half of the PID space */ | |
367 | if (!mmu_pid_bits) | |
368 | mmu_pid_bits = 19; | |
369 | mmu_base_pid = 1; | |
370 | } | |
371 | ||
2bfd65e4 AK |
372 | /* |
373 | * Allocate Partition table and process table for the | |
374 | * host. | |
375 | */ | |
a25bd72b | 376 | BUG_ON(PRTB_SIZE_SHIFT > 36); |
2ad452ff | 377 | process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0); |
2bfd65e4 AK |
378 | /* |
379 | * Fill in the process table. | |
2bfd65e4 | 380 | */ |
b23d9c5b | 381 | rts_field = radix__get_tree_size(); |
2bfd65e4 AK |
382 | process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE); |
383 | /* | |
384 | * Fill in the partition table. We are suppose to use effective address | |
385 | * of process table here. But our linear mapping also enable us to use | |
386 | * physical address here. | |
387 | */ | |
eea8148c | 388 | register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12); |
2bfd65e4 | 389 | pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd); |
7a70d728 PM |
390 | asm volatile("ptesync" : : : "memory"); |
391 | asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : : | |
392 | "r" (TLBIEL_INVAL_SET_LPID), "r" (0)); | |
393 | asm volatile("eieio; tlbsync; ptesync" : : : "memory"); | |
0428491c | 394 | trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1); |
eeb715c3 NP |
395 | |
396 | /* | |
397 | * The init_mm context is given the first available (non-zero) PID, | |
398 | * which is the "guard PID" and contains no page table. PIDR should | |
399 | * never be set to zero because that duplicates the kernel address | |
400 | * space at the 0x0... offset (quadrant 0)! | |
401 | * | |
402 | * An arbitrary PID that may later be allocated by the PID allocator | |
403 | * for userspace processes must not be used either, because that | |
404 | * would cause stale user mappings for that PID on CPUs outside of | |
405 | * the TLB invalidation scheme (because it won't be in mm_cpumask). | |
406 | * | |
407 | * So permanently carve out one PID for the purpose of a guard PID. | |
408 | */ | |
409 | init_mm.context.id = mmu_base_pid; | |
410 | mmu_base_pid++; | |
2bfd65e4 AK |
411 | } |
412 | ||
413 | static void __init radix_init_partition_table(void) | |
414 | { | |
9d661958 | 415 | unsigned long rts_field, dw0; |
b23d9c5b | 416 | |
9d661958 | 417 | mmu_partition_table_init(); |
b23d9c5b | 418 | rts_field = radix__get_tree_size(); |
9d661958 PM |
419 | dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR; |
420 | mmu_partition_table_set_entry(0, dw0, 0); | |
2bfd65e4 | 421 | |
56547411 AK |
422 | pr_info("Initializing Radix MMU\n"); |
423 | pr_info("Partition table %p\n", partition_tb); | |
2bfd65e4 AK |
424 | } |
425 | ||
426 | void __init radix_init_native(void) | |
427 | { | |
eea8148c | 428 | register_process_table = native_register_process_table; |
2bfd65e4 AK |
429 | } |
430 | ||
431 | static int __init get_idx_from_shift(unsigned int shift) | |
432 | { | |
433 | int idx = -1; | |
434 | ||
435 | switch (shift) { | |
436 | case 0xc: | |
437 | idx = MMU_PAGE_4K; | |
438 | break; | |
439 | case 0x10: | |
440 | idx = MMU_PAGE_64K; | |
441 | break; | |
442 | case 0x15: | |
443 | idx = MMU_PAGE_2M; | |
444 | break; | |
445 | case 0x1e: | |
446 | idx = MMU_PAGE_1G; | |
447 | break; | |
448 | } | |
449 | return idx; | |
450 | } | |
451 | ||
452 | static int __init radix_dt_scan_page_sizes(unsigned long node, | |
453 | const char *uname, int depth, | |
454 | void *data) | |
455 | { | |
456 | int size = 0; | |
457 | int shift, idx; | |
458 | unsigned int ap; | |
459 | const __be32 *prop; | |
460 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
461 | ||
462 | /* We are scanning "cpu" nodes only */ | |
463 | if (type == NULL || strcmp(type, "cpu") != 0) | |
464 | return 0; | |
465 | ||
a25bd72b BH |
466 | /* Find MMU PID size */ |
467 | prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size); | |
468 | if (prop && size == 4) | |
469 | mmu_pid_bits = be32_to_cpup(prop); | |
470 | ||
471 | /* Grab page size encodings */ | |
2bfd65e4 AK |
472 | prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size); |
473 | if (!prop) | |
474 | return 0; | |
475 | ||
476 | pr_info("Page sizes from device-tree:\n"); | |
477 | for (; size >= 4; size -= 4, ++prop) { | |
478 | ||
479 | struct mmu_psize_def *def; | |
480 | ||
481 | /* top 3 bit is AP encoding */ | |
482 | shift = be32_to_cpu(prop[0]) & ~(0xe << 28); | |
483 | ap = be32_to_cpu(prop[0]) >> 29; | |
ac8d3818 | 484 | pr_info("Page size shift = %d AP=0x%x\n", shift, ap); |
2bfd65e4 AK |
485 | |
486 | idx = get_idx_from_shift(shift); | |
487 | if (idx < 0) | |
488 | continue; | |
489 | ||
490 | def = &mmu_psize_defs[idx]; | |
491 | def->shift = shift; | |
492 | def->ap = ap; | |
493 | } | |
494 | ||
495 | /* needed ? */ | |
496 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; | |
497 | return 1; | |
498 | } | |
499 | ||
2537b09c | 500 | void __init radix__early_init_devtree(void) |
2bfd65e4 AK |
501 | { |
502 | int rc; | |
503 | ||
504 | /* | |
505 | * Try to find the available page sizes in the device-tree | |
506 | */ | |
507 | rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL); | |
508 | if (rc != 0) /* Found */ | |
509 | goto found; | |
510 | /* | |
511 | * let's assume we have page 4k and 64k support | |
512 | */ | |
513 | mmu_psize_defs[MMU_PAGE_4K].shift = 12; | |
514 | mmu_psize_defs[MMU_PAGE_4K].ap = 0x0; | |
515 | ||
516 | mmu_psize_defs[MMU_PAGE_64K].shift = 16; | |
517 | mmu_psize_defs[MMU_PAGE_64K].ap = 0x5; | |
518 | found: | |
2bfd65e4 AK |
519 | return; |
520 | } | |
521 | ||
ee97b6b9 BS |
522 | static void radix_init_amor(void) |
523 | { | |
524 | /* | |
525 | * In HV mode, we init AMOR (Authority Mask Override Register) so that | |
526 | * the hypervisor and guest can setup IAMR (Instruction Authority Mask | |
527 | * Register), enable key 0 and set it to 1. | |
528 | * | |
529 | * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11) | |
530 | */ | |
531 | mtspr(SPRN_AMOR, (3ul << 62)); | |
532 | } | |
533 | ||
1bb2bae2 RC |
534 | #ifdef CONFIG_PPC_KUEP |
535 | void setup_kuep(bool disabled) | |
3b10d009 | 536 | { |
1bb2bae2 RC |
537 | if (disabled || !early_radix_enabled()) |
538 | return; | |
539 | ||
540 | if (smp_processor_id() == boot_cpuid) | |
541 | pr_info("Activating Kernel Userspace Execution Prevention\n"); | |
542 | ||
3b10d009 BS |
543 | /* |
544 | * Radix always uses key0 of the IAMR to determine if an access is | |
545 | * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction | |
546 | * fetch. | |
547 | */ | |
2bf1071a | 548 | mtspr(SPRN_IAMR, (1ul << 62)); |
3b10d009 | 549 | } |
1bb2bae2 | 550 | #endif |
3b10d009 | 551 | |
890274c2 ME |
552 | #ifdef CONFIG_PPC_KUAP |
553 | void setup_kuap(bool disabled) | |
554 | { | |
555 | if (disabled || !early_radix_enabled()) | |
556 | return; | |
557 | ||
558 | if (smp_processor_id() == boot_cpuid) { | |
559 | pr_info("Activating Kernel Userspace Access Prevention\n"); | |
560 | cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_KUAP; | |
561 | } | |
562 | ||
563 | /* Make sure userspace can't change the AMR */ | |
564 | mtspr(SPRN_UAMOR, 0); | |
565 | mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); | |
566 | isync(); | |
567 | } | |
568 | #endif | |
569 | ||
2bfd65e4 AK |
570 | void __init radix__early_init_mmu(void) |
571 | { | |
572 | unsigned long lpcr; | |
2bfd65e4 AK |
573 | |
574 | #ifdef CONFIG_PPC_64K_PAGES | |
575 | /* PAGE_SIZE mappings */ | |
576 | mmu_virtual_psize = MMU_PAGE_64K; | |
577 | #else | |
578 | mmu_virtual_psize = MMU_PAGE_4K; | |
579 | #endif | |
580 | ||
581 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
582 | /* vmemmap mapping */ | |
89a3496e AK |
583 | if (mmu_psize_defs[MMU_PAGE_2M].shift) { |
584 | /* | |
585 | * map vmemmap using 2M if available | |
586 | */ | |
587 | mmu_vmemmap_psize = MMU_PAGE_2M; | |
588 | } else | |
589 | mmu_vmemmap_psize = mmu_virtual_psize; | |
2bfd65e4 AK |
590 | #endif |
591 | /* | |
592 | * initialize page table size | |
593 | */ | |
594 | __pte_index_size = RADIX_PTE_INDEX_SIZE; | |
595 | __pmd_index_size = RADIX_PMD_INDEX_SIZE; | |
596 | __pud_index_size = RADIX_PUD_INDEX_SIZE; | |
597 | __pgd_index_size = RADIX_PGD_INDEX_SIZE; | |
fae22116 | 598 | __pud_cache_index = RADIX_PUD_INDEX_SIZE; |
2bfd65e4 AK |
599 | __pte_table_size = RADIX_PTE_TABLE_SIZE; |
600 | __pmd_table_size = RADIX_PMD_TABLE_SIZE; | |
601 | __pud_table_size = RADIX_PUD_TABLE_SIZE; | |
602 | __pgd_table_size = RADIX_PGD_TABLE_SIZE; | |
603 | ||
a2f41eb9 AK |
604 | __pmd_val_bits = RADIX_PMD_VAL_BITS; |
605 | __pud_val_bits = RADIX_PUD_VAL_BITS; | |
606 | __pgd_val_bits = RADIX_PGD_VAL_BITS; | |
2bfd65e4 | 607 | |
d6a9996e | 608 | __kernel_virt_start = RADIX_KERN_VIRT_START; |
d6a9996e AK |
609 | __vmalloc_start = RADIX_VMALLOC_START; |
610 | __vmalloc_end = RADIX_VMALLOC_END; | |
63ee9b2f | 611 | __kernel_io_start = RADIX_KERN_IO_START; |
a35a3c6f | 612 | __kernel_io_end = RADIX_KERN_IO_END; |
0034d395 | 613 | vmemmap = (struct page *)RADIX_VMEMMAP_START; |
d6a9996e | 614 | ioremap_bot = IOREMAP_BASE; |
bfa37087 DS |
615 | |
616 | #ifdef CONFIG_PCI | |
617 | pci_io_base = ISA_IO_BASE; | |
618 | #endif | |
fb4e5dbd AK |
619 | __pte_frag_nr = RADIX_PTE_FRAG_NR; |
620 | __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT; | |
8a6c697b AK |
621 | __pmd_frag_nr = RADIX_PMD_FRAG_NR; |
622 | __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT; | |
d6a9996e | 623 | |
d6c88600 | 624 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
166dd7d3 | 625 | radix_init_native(); |
d6c88600 | 626 | lpcr = mfspr(SPRN_LPCR); |
bf16cdf4 | 627 | mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); |
2bfd65e4 | 628 | radix_init_partition_table(); |
ee97b6b9 | 629 | radix_init_amor(); |
cc3d2940 PM |
630 | } else { |
631 | radix_init_pseries(); | |
d6c88600 | 632 | } |
2bfd65e4 | 633 | |
9d661958 PM |
634 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); |
635 | ||
2bfd65e4 | 636 | radix_init_pgtable(); |
eeb715c3 NP |
637 | /* Switch to the guard PID before turning on MMU */ |
638 | radix__switch_mmu_context(NULL, &init_mm); | |
d4748276 NP |
639 | if (cpu_has_feature(CPU_FTR_HVMODE)) |
640 | tlbiel_all(); | |
2bfd65e4 AK |
641 | } |
642 | ||
643 | void radix__early_init_mmu_secondary(void) | |
644 | { | |
645 | unsigned long lpcr; | |
646 | /* | |
d6c88600 | 647 | * update partition table control register and UPRT |
2bfd65e4 | 648 | */ |
d6c88600 AK |
649 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
650 | lpcr = mfspr(SPRN_LPCR); | |
bf16cdf4 | 651 | mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); |
d6c88600 | 652 | |
2bfd65e4 AK |
653 | mtspr(SPRN_PTCR, |
654 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
ee97b6b9 | 655 | radix_init_amor(); |
d6c88600 | 656 | } |
d4748276 | 657 | |
eeb715c3 | 658 | radix__switch_mmu_context(NULL, &init_mm); |
d4748276 NP |
659 | if (cpu_has_feature(CPU_FTR_HVMODE)) |
660 | tlbiel_all(); | |
2bfd65e4 AK |
661 | } |
662 | ||
fe036a06 BH |
663 | void radix__mmu_cleanup_all(void) |
664 | { | |
665 | unsigned long lpcr; | |
666 | ||
667 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { | |
668 | lpcr = mfspr(SPRN_LPCR); | |
669 | mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); | |
670 | mtspr(SPRN_PTCR, 0); | |
1d0761d2 | 671 | powernv_set_nmmu_ptcr(0); |
fe036a06 BH |
672 | radix__flush_tlb_all(); |
673 | } | |
674 | } | |
675 | ||
2bfd65e4 AK |
676 | void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
677 | phys_addr_t first_memblock_size) | |
678 | { | |
47d99948 CL |
679 | /* |
680 | * We don't currently support the first MEMBLOCK not mapping 0 | |
177ba7c6 AK |
681 | * physical on those processors |
682 | */ | |
683 | BUG_ON(first_memblock_base != 0); | |
1513c33d | 684 | |
5eae82ca NP |
685 | /* |
686 | * Radix mode is not limited by RMA / VRMA addressing. | |
687 | */ | |
688 | ppc64_rma_size = ULONG_MAX; | |
2bfd65e4 | 689 | } |
d9225ad9 | 690 | |
6cc27341 | 691 | #ifdef CONFIG_MEMORY_HOTPLUG |
4b5d62ca RA |
692 | static void free_pte_table(pte_t *pte_start, pmd_t *pmd) |
693 | { | |
694 | pte_t *pte; | |
695 | int i; | |
696 | ||
697 | for (i = 0; i < PTRS_PER_PTE; i++) { | |
698 | pte = pte_start + i; | |
699 | if (!pte_none(*pte)) | |
700 | return; | |
701 | } | |
702 | ||
703 | pte_free_kernel(&init_mm, pte_start); | |
704 | pmd_clear(pmd); | |
705 | } | |
706 | ||
707 | static void free_pmd_table(pmd_t *pmd_start, pud_t *pud) | |
708 | { | |
709 | pmd_t *pmd; | |
710 | int i; | |
711 | ||
712 | for (i = 0; i < PTRS_PER_PMD; i++) { | |
713 | pmd = pmd_start + i; | |
714 | if (!pmd_none(*pmd)) | |
715 | return; | |
716 | } | |
717 | ||
718 | pmd_free(&init_mm, pmd_start); | |
719 | pud_clear(pud); | |
720 | } | |
721 | ||
4dd5f8a9 BS |
722 | struct change_mapping_params { |
723 | pte_t *pte; | |
724 | unsigned long start; | |
725 | unsigned long end; | |
726 | unsigned long aligned_start; | |
727 | unsigned long aligned_end; | |
728 | }; | |
729 | ||
bde709a7 | 730 | static int __meminit stop_machine_change_mapping(void *data) |
4dd5f8a9 BS |
731 | { |
732 | struct change_mapping_params *params = | |
733 | (struct change_mapping_params *)data; | |
734 | ||
735 | if (!data) | |
736 | return -1; | |
737 | ||
738 | spin_unlock(&init_mm.page_table_lock); | |
739 | pte_clear(&init_mm, params->aligned_start, params->pte); | |
f437c517 ME |
740 | create_physical_mapping(params->aligned_start, params->start, -1); |
741 | create_physical_mapping(params->end, params->aligned_end, -1); | |
4dd5f8a9 BS |
742 | spin_lock(&init_mm.page_table_lock); |
743 | return 0; | |
744 | } | |
745 | ||
4b5d62ca RA |
746 | static void remove_pte_table(pte_t *pte_start, unsigned long addr, |
747 | unsigned long end) | |
748 | { | |
749 | unsigned long next; | |
750 | pte_t *pte; | |
751 | ||
752 | pte = pte_start + pte_index(addr); | |
753 | for (; addr < end; addr = next, pte++) { | |
754 | next = (addr + PAGE_SIZE) & PAGE_MASK; | |
755 | if (next > end) | |
756 | next = end; | |
757 | ||
758 | if (!pte_present(*pte)) | |
759 | continue; | |
760 | ||
0d0a4bc2 RA |
761 | if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) { |
762 | /* | |
763 | * The vmemmap_free() and remove_section_mapping() | |
764 | * codepaths call us with aligned addresses. | |
765 | */ | |
766 | WARN_ONCE(1, "%s: unaligned range\n", __func__); | |
767 | continue; | |
768 | } | |
769 | ||
4b5d62ca RA |
770 | pte_clear(&init_mm, addr, pte); |
771 | } | |
772 | } | |
773 | ||
4dd5f8a9 BS |
774 | /* |
775 | * clear the pte and potentially split the mapping helper | |
776 | */ | |
bde709a7 | 777 | static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end, |
4dd5f8a9 BS |
778 | unsigned long size, pte_t *pte) |
779 | { | |
780 | unsigned long mask = ~(size - 1); | |
781 | unsigned long aligned_start = addr & mask; | |
782 | unsigned long aligned_end = addr + size; | |
783 | struct change_mapping_params params; | |
784 | bool split_region = false; | |
785 | ||
786 | if ((end - addr) < size) { | |
787 | /* | |
788 | * We're going to clear the PTE, but not flushed | |
789 | * the mapping, time to remap and flush. The | |
790 | * effects if visible outside the processor or | |
791 | * if we are running in code close to the | |
792 | * mapping we cleared, we are in trouble. | |
793 | */ | |
794 | if (overlaps_kernel_text(aligned_start, addr) || | |
795 | overlaps_kernel_text(end, aligned_end)) { | |
796 | /* | |
797 | * Hack, just return, don't pte_clear | |
798 | */ | |
799 | WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel " | |
800 | "text, not splitting\n", addr, end); | |
801 | return; | |
802 | } | |
803 | split_region = true; | |
804 | } | |
805 | ||
806 | if (split_region) { | |
807 | params.pte = pte; | |
808 | params.start = addr; | |
809 | params.end = end; | |
810 | params.aligned_start = addr & ~(size - 1); | |
811 | params.aligned_end = min_t(unsigned long, aligned_end, | |
812 | (unsigned long)__va(memblock_end_of_DRAM())); | |
813 | stop_machine(stop_machine_change_mapping, ¶ms, NULL); | |
814 | return; | |
815 | } | |
816 | ||
817 | pte_clear(&init_mm, addr, pte); | |
818 | } | |
819 | ||
4b5d62ca RA |
820 | static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr, |
821 | unsigned long end) | |
822 | { | |
823 | unsigned long next; | |
824 | pte_t *pte_base; | |
825 | pmd_t *pmd; | |
826 | ||
827 | pmd = pmd_start + pmd_index(addr); | |
828 | for (; addr < end; addr = next, pmd++) { | |
829 | next = pmd_addr_end(addr, end); | |
830 | ||
831 | if (!pmd_present(*pmd)) | |
832 | continue; | |
833 | ||
d6eacedd | 834 | if (pmd_is_leaf(*pmd)) { |
4dd5f8a9 | 835 | split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd); |
4b5d62ca RA |
836 | continue; |
837 | } | |
838 | ||
839 | pte_base = (pte_t *)pmd_page_vaddr(*pmd); | |
840 | remove_pte_table(pte_base, addr, next); | |
841 | free_pte_table(pte_base, pmd); | |
842 | } | |
843 | } | |
844 | ||
845 | static void remove_pud_table(pud_t *pud_start, unsigned long addr, | |
846 | unsigned long end) | |
847 | { | |
848 | unsigned long next; | |
849 | pmd_t *pmd_base; | |
850 | pud_t *pud; | |
851 | ||
852 | pud = pud_start + pud_index(addr); | |
853 | for (; addr < end; addr = next, pud++) { | |
854 | next = pud_addr_end(addr, end); | |
855 | ||
856 | if (!pud_present(*pud)) | |
857 | continue; | |
858 | ||
d6eacedd | 859 | if (pud_is_leaf(*pud)) { |
4dd5f8a9 | 860 | split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud); |
4b5d62ca RA |
861 | continue; |
862 | } | |
863 | ||
864 | pmd_base = (pmd_t *)pud_page_vaddr(*pud); | |
865 | remove_pmd_table(pmd_base, addr, next); | |
866 | free_pmd_table(pmd_base, pud); | |
867 | } | |
868 | } | |
869 | ||
bde709a7 | 870 | static void __meminit remove_pagetable(unsigned long start, unsigned long end) |
4b5d62ca RA |
871 | { |
872 | unsigned long addr, next; | |
873 | pud_t *pud_base; | |
874 | pgd_t *pgd; | |
875 | ||
876 | spin_lock(&init_mm.page_table_lock); | |
877 | ||
878 | for (addr = start; addr < end; addr = next) { | |
879 | next = pgd_addr_end(addr, end); | |
880 | ||
881 | pgd = pgd_offset_k(addr); | |
882 | if (!pgd_present(*pgd)) | |
883 | continue; | |
884 | ||
d6eacedd | 885 | if (pgd_is_leaf(*pgd)) { |
4dd5f8a9 | 886 | split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd); |
4b5d62ca RA |
887 | continue; |
888 | } | |
889 | ||
890 | pud_base = (pud_t *)pgd_page_vaddr(*pgd); | |
891 | remove_pud_table(pud_base, addr, next); | |
892 | } | |
893 | ||
894 | spin_unlock(&init_mm.page_table_lock); | |
895 | radix__flush_tlb_kernel_range(start, end); | |
896 | } | |
897 | ||
f437c517 | 898 | int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid) |
6cc27341 | 899 | { |
e0909392 | 900 | if (end >= RADIX_VMALLOC_START) { |
f341d897 | 901 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
902 | return -1; |
903 | } | |
904 | ||
29ab6c47 | 905 | return create_physical_mapping(start, end, nid); |
6cc27341 | 906 | } |
4b5d62ca | 907 | |
bde709a7 | 908 | int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end) |
4b5d62ca RA |
909 | { |
910 | remove_pagetable(start, end); | |
911 | return 0; | |
912 | } | |
6cc27341 RA |
913 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
914 | ||
d9225ad9 | 915 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
29ab6c47 NP |
916 | static int __map_kernel_page_nid(unsigned long ea, unsigned long pa, |
917 | pgprot_t flags, unsigned int map_page_size, | |
918 | int nid) | |
919 | { | |
920 | return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0); | |
921 | } | |
922 | ||
d9225ad9 AK |
923 | int __meminit radix__vmemmap_create_mapping(unsigned long start, |
924 | unsigned long page_size, | |
925 | unsigned long phys) | |
926 | { | |
927 | /* Create a PTE encoding */ | |
928 | unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW; | |
2ad452ff NP |
929 | int nid = early_pfn_to_nid(phys >> PAGE_SHIFT); |
930 | int ret; | |
931 | ||
e0909392 | 932 | if ((start + page_size) >= RADIX_VMEMMAP_END) { |
f341d897 | 933 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
934 | return -1; |
935 | } | |
936 | ||
2ad452ff NP |
937 | ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid); |
938 | BUG_ON(ret); | |
d9225ad9 | 939 | |
d9225ad9 AK |
940 | return 0; |
941 | } | |
942 | ||
943 | #ifdef CONFIG_MEMORY_HOTPLUG | |
bde709a7 | 944 | void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size) |
d9225ad9 | 945 | { |
0d0a4bc2 | 946 | remove_pagetable(start, start + page_size); |
d9225ad9 AK |
947 | } |
948 | #endif | |
949 | #endif | |
bde3eb62 AK |
950 | |
951 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
952 | ||
953 | unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, | |
954 | pmd_t *pmdp, unsigned long clr, | |
955 | unsigned long set) | |
956 | { | |
957 | unsigned long old; | |
958 | ||
959 | #ifdef CONFIG_DEBUG_VM | |
ebd31197 | 960 | WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp)); |
af60a4cf | 961 | assert_spin_locked(pmd_lockptr(mm, pmdp)); |
bde3eb62 AK |
962 | #endif |
963 | ||
964 | old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1); | |
965 | trace_hugepage_update(addr, old, clr, set); | |
966 | ||
967 | return old; | |
968 | } | |
969 | ||
970 | pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address, | |
971 | pmd_t *pmdp) | |
972 | ||
973 | { | |
974 | pmd_t pmd; | |
975 | ||
976 | VM_BUG_ON(address & ~HPAGE_PMD_MASK); | |
977 | VM_BUG_ON(radix__pmd_trans_huge(*pmdp)); | |
ebd31197 | 978 | VM_BUG_ON(pmd_devmap(*pmdp)); |
bde3eb62 AK |
979 | /* |
980 | * khugepaged calls this for normal pmd | |
981 | */ | |
982 | pmd = *pmdp; | |
983 | pmd_clear(pmdp); | |
424de9c6 | 984 | |
bde3eb62 | 985 | /*FIXME!! Verify whether we need this kick below */ |
fa4531f7 | 986 | serialize_against_pte_lookup(vma->vm_mm); |
424de9c6 BH |
987 | |
988 | radix__flush_tlb_collapsed_pmd(vma->vm_mm, address); | |
989 | ||
bde3eb62 AK |
990 | return pmd; |
991 | } | |
992 | ||
993 | /* | |
994 | * For us pgtable_t is pte_t *. Inorder to save the deposisted | |
995 | * page table, we consider the allocated page table as a list | |
996 | * head. On withdraw we need to make sure we zero out the used | |
997 | * list_head memory area. | |
998 | */ | |
999 | void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
1000 | pgtable_t pgtable) | |
1001 | { | |
47d99948 | 1002 | struct list_head *lh = (struct list_head *) pgtable; |
bde3eb62 | 1003 | |
47d99948 | 1004 | assert_spin_locked(pmd_lockptr(mm, pmdp)); |
bde3eb62 | 1005 | |
47d99948 CL |
1006 | /* FIFO */ |
1007 | if (!pmd_huge_pte(mm, pmdp)) | |
1008 | INIT_LIST_HEAD(lh); | |
1009 | else | |
1010 | list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp)); | |
1011 | pmd_huge_pte(mm, pmdp) = pgtable; | |
bde3eb62 AK |
1012 | } |
1013 | ||
1014 | pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp) | |
1015 | { | |
47d99948 CL |
1016 | pte_t *ptep; |
1017 | pgtable_t pgtable; | |
1018 | struct list_head *lh; | |
bde3eb62 | 1019 | |
47d99948 CL |
1020 | assert_spin_locked(pmd_lockptr(mm, pmdp)); |
1021 | ||
1022 | /* FIFO */ | |
1023 | pgtable = pmd_huge_pte(mm, pmdp); | |
1024 | lh = (struct list_head *) pgtable; | |
1025 | if (list_empty(lh)) | |
1026 | pmd_huge_pte(mm, pmdp) = NULL; | |
1027 | else { | |
1028 | pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next; | |
1029 | list_del(lh); | |
1030 | } | |
1031 | ptep = (pte_t *) pgtable; | |
1032 | *ptep = __pte(0); | |
1033 | ptep++; | |
1034 | *ptep = __pte(0); | |
1035 | return pgtable; | |
1036 | } | |
bde3eb62 AK |
1037 | |
1038 | pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm, | |
47d99948 | 1039 | unsigned long addr, pmd_t *pmdp) |
bde3eb62 AK |
1040 | { |
1041 | pmd_t old_pmd; | |
1042 | unsigned long old; | |
1043 | ||
1044 | old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0); | |
1045 | old_pmd = __pmd(old); | |
1046 | /* | |
fa4531f7 | 1047 | * Serialize against find_current_mm_pte which does lock-less |
bde3eb62 AK |
1048 | * lookup in page tables with local interrupts disabled. For huge pages |
1049 | * it casts pmd_t to pte_t. Since format of pte_t is different from | |
1050 | * pmd_t we want to prevent transit from pmd pointing to page table | |
1051 | * to pmd pointing to huge page (and back) while interrupts are disabled. | |
1052 | * We clear pmd to possibly replace it with page table pointer in | |
1053 | * different code paths. So make sure we wait for the parallel | |
fa4531f7 | 1054 | * find_current_mm_pte to finish. |
bde3eb62 | 1055 | */ |
fa4531f7 | 1056 | serialize_against_pte_lookup(mm); |
bde3eb62 AK |
1057 | return old_pmd; |
1058 | } | |
1059 | ||
bde3eb62 | 1060 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
044003b5 | 1061 | |
e4c1112c AK |
1062 | void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, |
1063 | pte_t entry, unsigned long address, int psize) | |
044003b5 | 1064 | { |
e4c1112c | 1065 | struct mm_struct *mm = vma->vm_mm; |
044003b5 AK |
1066 | unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | |
1067 | _PAGE_RW | _PAGE_EXEC); | |
f08d08f3 AK |
1068 | |
1069 | unsigned long change = pte_val(entry) ^ pte_val(*ptep); | |
bd5050e3 AK |
1070 | /* |
1071 | * To avoid NMMU hang while relaxing access, we need mark | |
1072 | * the pte invalid in between. | |
1073 | */ | |
f08d08f3 | 1074 | if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) { |
044003b5 AK |
1075 | unsigned long old_pte, new_pte; |
1076 | ||
f08d08f3 | 1077 | old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID); |
044003b5 AK |
1078 | /* |
1079 | * new value of pte | |
1080 | */ | |
1081 | new_pte = old_pte | set; | |
bd5050e3 | 1082 | radix__flush_tlb_page_psize(mm, address, psize); |
f08d08f3 | 1083 | __radix_pte_update(ptep, _PAGE_INVALID, new_pte); |
bd5050e3 | 1084 | } else { |
044003b5 | 1085 | __radix_pte_update(ptep, 0, set); |
e5f7cb58 NP |
1086 | /* |
1087 | * Book3S does not require a TLB flush when relaxing access | |
1088 | * restrictions when the address space is not attached to a | |
1089 | * NMMU, because the core MMU will reload the pte after taking | |
1090 | * an access fault, which is defined by the architectue. | |
1091 | */ | |
bd5050e3 | 1092 | } |
f1cb8f9b | 1093 | /* See ptesync comment in radix__set_pte_at */ |
044003b5 | 1094 | } |
5b323367 AK |
1095 | |
1096 | void radix__ptep_modify_prot_commit(struct vm_area_struct *vma, | |
1097 | unsigned long addr, pte_t *ptep, | |
1098 | pte_t old_pte, pte_t pte) | |
1099 | { | |
1100 | struct mm_struct *mm = vma->vm_mm; | |
1101 | ||
1102 | /* | |
1103 | * To avoid NMMU hang while relaxing access we need to flush the tlb before | |
1104 | * we set the new value. We need to do this only for radix, because hash | |
1105 | * translation does flush when updating the linux pte. | |
1106 | */ | |
1107 | if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) && | |
1108 | (atomic_read(&mm->context.copros) > 0)) | |
1109 | radix__flush_tlb_page(vma, addr); | |
1110 | ||
1111 | set_pte_at(mm, addr, ptep, pte); | |
1112 | } | |
d38153f9 | 1113 | |
d909f910 NP |
1114 | int __init arch_ioremap_pud_supported(void) |
1115 | { | |
1116 | /* HPT does not cope with large pages in the vmalloc area */ | |
1117 | return radix_enabled(); | |
1118 | } | |
1119 | ||
1120 | int __init arch_ioremap_pmd_supported(void) | |
1121 | { | |
1122 | return radix_enabled(); | |
1123 | } | |
1124 | ||
1125 | int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) | |
1126 | { | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) | |
1131 | { | |
1132 | pte_t *ptep = (pte_t *)pud; | |
1133 | pte_t new_pud = pfn_pte(__phys_to_pfn(addr), prot); | |
1134 | ||
1135 | if (!radix_enabled()) | |
1136 | return 0; | |
1137 | ||
1138 | set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pud); | |
1139 | ||
1140 | return 1; | |
1141 | } | |
1142 | ||
1143 | int pud_clear_huge(pud_t *pud) | |
1144 | { | |
1145 | if (pud_huge(*pud)) { | |
1146 | pud_clear(pud); | |
1147 | return 1; | |
1148 | } | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | int pud_free_pmd_page(pud_t *pud, unsigned long addr) | |
1154 | { | |
1155 | pmd_t *pmd; | |
1156 | int i; | |
1157 | ||
1158 | pmd = (pmd_t *)pud_page_vaddr(*pud); | |
1159 | pud_clear(pud); | |
1160 | ||
1161 | flush_tlb_kernel_range(addr, addr + PUD_SIZE); | |
1162 | ||
1163 | for (i = 0; i < PTRS_PER_PMD; i++) { | |
1164 | if (!pmd_none(pmd[i])) { | |
1165 | pte_t *pte; | |
1166 | pte = (pte_t *)pmd_page_vaddr(pmd[i]); | |
1167 | ||
1168 | pte_free_kernel(&init_mm, pte); | |
1169 | } | |
1170 | } | |
1171 | ||
1172 | pmd_free(&init_mm, pmd); | |
1173 | ||
1174 | return 1; | |
1175 | } | |
1176 | ||
1177 | int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) | |
1178 | { | |
1179 | pte_t *ptep = (pte_t *)pmd; | |
1180 | pte_t new_pmd = pfn_pte(__phys_to_pfn(addr), prot); | |
1181 | ||
1182 | if (!radix_enabled()) | |
1183 | return 0; | |
1184 | ||
1185 | set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pmd); | |
1186 | ||
1187 | return 1; | |
1188 | } | |
1189 | ||
1190 | int pmd_clear_huge(pmd_t *pmd) | |
1191 | { | |
1192 | if (pmd_huge(*pmd)) { | |
1193 | pmd_clear(pmd); | |
1194 | return 1; | |
1195 | } | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) | |
1201 | { | |
1202 | pte_t *pte; | |
1203 | ||
1204 | pte = (pte_t *)pmd_page_vaddr(*pmd); | |
1205 | pmd_clear(pmd); | |
1206 | ||
1207 | flush_tlb_kernel_range(addr, addr + PMD_SIZE); | |
1208 | ||
1209 | pte_free_kernel(&init_mm, pte); | |
1210 | ||
1211 | return 1; | |
1212 | } | |
1213 | ||
d38153f9 NP |
1214 | int radix__ioremap_range(unsigned long ea, phys_addr_t pa, unsigned long size, |
1215 | pgprot_t prot, int nid) | |
1216 | { | |
1217 | if (likely(slab_is_available())) { | |
1218 | int err = ioremap_page_range(ea, ea + size, pa, prot); | |
1219 | if (err) | |
1220 | unmap_kernel_range(ea, size); | |
1221 | return err; | |
1222 | } else { | |
1223 | unsigned long i; | |
1224 | ||
1225 | for (i = 0; i < size; i += PAGE_SIZE) { | |
1226 | int err = map_kernel_page(ea + i, pa + i, prot); | |
1227 | if (WARN_ON_ONCE(err)) /* Should clean up */ | |
1228 | return err; | |
1229 | } | |
1230 | return 0; | |
1231 | } | |
1232 | } | |
0f472d04 AK |
1233 | |
1234 | int __init arch_ioremap_p4d_supported(void) | |
1235 | { | |
1236 | return 0; | |
1237 | } |