Commit | Line | Data |
---|---|---|
2bfd65e4 AK |
1 | /* |
2 | * Page table handling routines for radix page table. | |
3 | * | |
4 | * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
bd350f71 ME |
11 | |
12 | #define pr_fmt(fmt) "radix-mmu: " fmt | |
13 | ||
d38153f9 | 14 | #include <linux/io.h> |
bd350f71 | 15 | #include <linux/kernel.h> |
589ee628 | 16 | #include <linux/sched/mm.h> |
2bfd65e4 AK |
17 | #include <linux/memblock.h> |
18 | #include <linux/of_fdt.h> | |
7614ff32 | 19 | #include <linux/mm.h> |
6deb6b47 | 20 | #include <linux/string_helpers.h> |
4dd5f8a9 | 21 | #include <linux/stop_machine.h> |
2bfd65e4 AK |
22 | |
23 | #include <asm/pgtable.h> | |
24 | #include <asm/pgalloc.h> | |
eeb715c3 | 25 | #include <asm/mmu_context.h> |
2bfd65e4 AK |
26 | #include <asm/dma.h> |
27 | #include <asm/machdep.h> | |
28 | #include <asm/mmu.h> | |
29 | #include <asm/firmware.h> | |
1d0761d2 | 30 | #include <asm/powernv.h> |
9abcc981 | 31 | #include <asm/sections.h> |
0428491c | 32 | #include <asm/trace.h> |
890274c2 | 33 | #include <asm/uaccess.h> |
2bfd65e4 | 34 | |
bde3eb62 AK |
35 | #include <trace/events/thp.h> |
36 | ||
a25bd72b BH |
37 | unsigned int mmu_pid_bits; |
38 | unsigned int mmu_base_pid; | |
39 | ||
83209bc8 AK |
40 | static int native_register_process_table(unsigned long base, unsigned long pg_sz, |
41 | unsigned long table_size) | |
2bfd65e4 | 42 | { |
7cd2a869 SJS |
43 | unsigned long patb0, patb1; |
44 | ||
45 | patb0 = be64_to_cpu(partition_tb[0].patb0); | |
46 | patb1 = base | table_size | PATB_GR; | |
47 | ||
48 | mmu_partition_table_set_entry(0, patb0, patb1); | |
83209bc8 | 49 | |
2bfd65e4 AK |
50 | return 0; |
51 | } | |
52 | ||
2ad452ff NP |
53 | static __ref void *early_alloc_pgtable(unsigned long size, int nid, |
54 | unsigned long region_start, unsigned long region_end) | |
2bfd65e4 | 55 | { |
f806714f MR |
56 | phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT; |
57 | phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE; | |
8a7f97b9 | 58 | void *ptr; |
2bfd65e4 | 59 | |
f806714f MR |
60 | if (region_start) |
61 | min_addr = region_start; | |
62 | if (region_end) | |
63 | max_addr = region_end; | |
2ad452ff | 64 | |
8a7f97b9 MR |
65 | ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid); |
66 | ||
67 | if (!ptr) | |
68 | panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n", | |
69 | __func__, size, size, nid, &min_addr, &max_addr); | |
70 | ||
71 | return ptr; | |
2bfd65e4 AK |
72 | } |
73 | ||
0633dafc | 74 | static int early_map_kernel_page(unsigned long ea, unsigned long pa, |
2bfd65e4 | 75 | pgprot_t flags, |
2ad452ff NP |
76 | unsigned int map_page_size, |
77 | int nid, | |
78 | unsigned long region_start, unsigned long region_end) | |
2bfd65e4 | 79 | { |
2ad452ff | 80 | unsigned long pfn = pa >> PAGE_SHIFT; |
0633dafc NP |
81 | pgd_t *pgdp; |
82 | pud_t *pudp; | |
83 | pmd_t *pmdp; | |
84 | pte_t *ptep; | |
85 | ||
86 | pgdp = pgd_offset_k(ea); | |
87 | if (pgd_none(*pgdp)) { | |
2ad452ff NP |
88 | pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid, |
89 | region_start, region_end); | |
0633dafc NP |
90 | pgd_populate(&init_mm, pgdp, pudp); |
91 | } | |
92 | pudp = pud_offset(pgdp, ea); | |
93 | if (map_page_size == PUD_SIZE) { | |
94 | ptep = (pte_t *)pudp; | |
95 | goto set_the_pte; | |
96 | } | |
97 | if (pud_none(*pudp)) { | |
2ad452ff NP |
98 | pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid, |
99 | region_start, region_end); | |
0633dafc NP |
100 | pud_populate(&init_mm, pudp, pmdp); |
101 | } | |
102 | pmdp = pmd_offset(pudp, ea); | |
103 | if (map_page_size == PMD_SIZE) { | |
104 | ptep = pmdp_ptep(pmdp); | |
105 | goto set_the_pte; | |
106 | } | |
107 | if (!pmd_present(*pmdp)) { | |
2ad452ff NP |
108 | ptep = early_alloc_pgtable(PAGE_SIZE, nid, |
109 | region_start, region_end); | |
0633dafc NP |
110 | pmd_populate_kernel(&init_mm, pmdp, ptep); |
111 | } | |
112 | ptep = pte_offset_kernel(pmdp, ea); | |
113 | ||
114 | set_the_pte: | |
2ad452ff | 115 | set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags)); |
0633dafc NP |
116 | smp_wmb(); |
117 | return 0; | |
118 | } | |
119 | ||
2ad452ff NP |
120 | /* |
121 | * nid, region_start, and region_end are hints to try to place the page | |
122 | * table memory in the same node or region. | |
123 | */ | |
124 | static int __map_kernel_page(unsigned long ea, unsigned long pa, | |
2bfd65e4 | 125 | pgprot_t flags, |
2ad452ff NP |
126 | unsigned int map_page_size, |
127 | int nid, | |
128 | unsigned long region_start, unsigned long region_end) | |
2bfd65e4 | 129 | { |
2ad452ff | 130 | unsigned long pfn = pa >> PAGE_SHIFT; |
2bfd65e4 AK |
131 | pgd_t *pgdp; |
132 | pud_t *pudp; | |
133 | pmd_t *pmdp; | |
134 | pte_t *ptep; | |
135 | /* | |
136 | * Make sure task size is correct as per the max adddr | |
137 | */ | |
138 | BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE); | |
0633dafc | 139 | |
0034d395 AK |
140 | #ifdef CONFIG_PPC_64K_PAGES |
141 | BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT)); | |
142 | #endif | |
143 | ||
2ad452ff NP |
144 | if (unlikely(!slab_is_available())) |
145 | return early_map_kernel_page(ea, pa, flags, map_page_size, | |
146 | nid, region_start, region_end); | |
0633dafc | 147 | |
2ad452ff NP |
148 | /* |
149 | * Should make page table allocation functions be able to take a | |
150 | * node, so we can place kernel page tables on the right nodes after | |
151 | * boot. | |
152 | */ | |
0633dafc NP |
153 | pgdp = pgd_offset_k(ea); |
154 | pudp = pud_alloc(&init_mm, pgdp, ea); | |
155 | if (!pudp) | |
156 | return -ENOMEM; | |
157 | if (map_page_size == PUD_SIZE) { | |
158 | ptep = (pte_t *)pudp; | |
159 | goto set_the_pte; | |
2bfd65e4 | 160 | } |
0633dafc NP |
161 | pmdp = pmd_alloc(&init_mm, pudp, ea); |
162 | if (!pmdp) | |
163 | return -ENOMEM; | |
164 | if (map_page_size == PMD_SIZE) { | |
165 | ptep = pmdp_ptep(pmdp); | |
166 | goto set_the_pte; | |
2bfd65e4 | 167 | } |
0633dafc NP |
168 | ptep = pte_alloc_kernel(pmdp, ea); |
169 | if (!ptep) | |
170 | return -ENOMEM; | |
2bfd65e4 AK |
171 | |
172 | set_the_pte: | |
2ad452ff | 173 | set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags)); |
2bfd65e4 AK |
174 | smp_wmb(); |
175 | return 0; | |
176 | } | |
177 | ||
2ad452ff NP |
178 | int radix__map_kernel_page(unsigned long ea, unsigned long pa, |
179 | pgprot_t flags, | |
180 | unsigned int map_page_size) | |
181 | { | |
182 | return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0); | |
183 | } | |
184 | ||
7614ff32 | 185 | #ifdef CONFIG_STRICT_KERNEL_RWX |
b134bd90 ME |
186 | void radix__change_memory_range(unsigned long start, unsigned long end, |
187 | unsigned long clear) | |
7614ff32 | 188 | { |
7614ff32 BS |
189 | unsigned long idx; |
190 | pgd_t *pgdp; | |
191 | pud_t *pudp; | |
192 | pmd_t *pmdp; | |
193 | pte_t *ptep; | |
194 | ||
195 | start = ALIGN_DOWN(start, PAGE_SIZE); | |
196 | end = PAGE_ALIGN(end); // aligns up | |
197 | ||
b134bd90 ME |
198 | pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n", |
199 | start, end, clear); | |
7614ff32 BS |
200 | |
201 | for (idx = start; idx < end; idx += PAGE_SIZE) { | |
202 | pgdp = pgd_offset_k(idx); | |
203 | pudp = pud_alloc(&init_mm, pgdp, idx); | |
204 | if (!pudp) | |
205 | continue; | |
206 | if (pud_huge(*pudp)) { | |
207 | ptep = (pte_t *)pudp; | |
208 | goto update_the_pte; | |
209 | } | |
210 | pmdp = pmd_alloc(&init_mm, pudp, idx); | |
211 | if (!pmdp) | |
212 | continue; | |
213 | if (pmd_huge(*pmdp)) { | |
214 | ptep = pmdp_ptep(pmdp); | |
215 | goto update_the_pte; | |
216 | } | |
217 | ptep = pte_alloc_kernel(pmdp, idx); | |
218 | if (!ptep) | |
219 | continue; | |
220 | update_the_pte: | |
b134bd90 | 221 | radix__pte_update(&init_mm, idx, ptep, clear, 0, 0); |
7614ff32 BS |
222 | } |
223 | ||
224 | radix__flush_tlb_kernel_range(start, end); | |
225 | } | |
b134bd90 ME |
226 | |
227 | void radix__mark_rodata_ro(void) | |
228 | { | |
229 | unsigned long start, end; | |
230 | ||
231 | start = (unsigned long)_stext; | |
232 | end = (unsigned long)__init_begin; | |
233 | ||
234 | radix__change_memory_range(start, end, _PAGE_WRITE); | |
235 | } | |
029d9252 ME |
236 | |
237 | void radix__mark_initmem_nx(void) | |
238 | { | |
239 | unsigned long start = (unsigned long)__init_begin; | |
240 | unsigned long end = (unsigned long)__init_end; | |
241 | ||
242 | radix__change_memory_range(start, end, _PAGE_EXEC); | |
243 | } | |
7614ff32 BS |
244 | #endif /* CONFIG_STRICT_KERNEL_RWX */ |
245 | ||
afb6d064 ME |
246 | static inline void __meminit |
247 | print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec) | |
b5200ec9 | 248 | { |
6deb6b47 ME |
249 | char buf[10]; |
250 | ||
b5200ec9 RA |
251 | if (end <= start) |
252 | return; | |
253 | ||
6deb6b47 ME |
254 | string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf)); |
255 | ||
afb6d064 ME |
256 | pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf, |
257 | exec ? " (exec)" : ""); | |
b5200ec9 RA |
258 | } |
259 | ||
232aa407 ME |
260 | static unsigned long next_boundary(unsigned long addr, unsigned long end) |
261 | { | |
262 | #ifdef CONFIG_STRICT_KERNEL_RWX | |
263 | if (addr < __pa_symbol(__init_begin)) | |
264 | return __pa_symbol(__init_begin); | |
265 | #endif | |
266 | return end; | |
267 | } | |
268 | ||
b5200ec9 | 269 | static int __meminit create_physical_mapping(unsigned long start, |
2ad452ff NP |
270 | unsigned long end, |
271 | int nid) | |
b5200ec9 | 272 | { |
9abcc981 | 273 | unsigned long vaddr, addr, mapping_size = 0; |
afb6d064 | 274 | bool prev_exec, exec = false; |
9abcc981 | 275 | pgprot_t prot; |
a2dc009a | 276 | int psize; |
b5200ec9 RA |
277 | |
278 | start = _ALIGN_UP(start, PAGE_SIZE); | |
279 | for (addr = start; addr < end; addr += mapping_size) { | |
280 | unsigned long gap, previous_size; | |
281 | int rc; | |
282 | ||
232aa407 | 283 | gap = next_boundary(addr, end) - addr; |
b5200ec9 | 284 | previous_size = mapping_size; |
afb6d064 | 285 | prev_exec = exec; |
b5200ec9 RA |
286 | |
287 | if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE && | |
57306c66 | 288 | mmu_psize_defs[MMU_PAGE_1G].shift) { |
b5200ec9 | 289 | mapping_size = PUD_SIZE; |
a2dc009a AK |
290 | psize = MMU_PAGE_1G; |
291 | } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE && | |
292 | mmu_psize_defs[MMU_PAGE_2M].shift) { | |
b5200ec9 | 293 | mapping_size = PMD_SIZE; |
a2dc009a AK |
294 | psize = MMU_PAGE_2M; |
295 | } else { | |
b5200ec9 | 296 | mapping_size = PAGE_SIZE; |
a2dc009a AK |
297 | psize = mmu_virtual_psize; |
298 | } | |
7614ff32 | 299 | |
9abcc981 ME |
300 | vaddr = (unsigned long)__va(addr); |
301 | ||
7f6d498e | 302 | if (overlaps_kernel_text(vaddr, vaddr + mapping_size) || |
afb6d064 | 303 | overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) { |
9abcc981 | 304 | prot = PAGE_KERNEL_X; |
afb6d064 ME |
305 | exec = true; |
306 | } else { | |
9abcc981 | 307 | prot = PAGE_KERNEL; |
afb6d064 ME |
308 | exec = false; |
309 | } | |
310 | ||
311 | if (mapping_size != previous_size || exec != prev_exec) { | |
312 | print_mapping(start, addr, previous_size, prev_exec); | |
313 | start = addr; | |
314 | } | |
9abcc981 | 315 | |
2ad452ff | 316 | rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end); |
b5200ec9 RA |
317 | if (rc) |
318 | return rc; | |
a2dc009a AK |
319 | |
320 | update_page_count(psize, 1); | |
b5200ec9 RA |
321 | } |
322 | ||
afb6d064 | 323 | print_mapping(start, addr, mapping_size, exec); |
b5200ec9 RA |
324 | return 0; |
325 | } | |
326 | ||
d667edc0 | 327 | static void __init radix_init_pgtable(void) |
2bfd65e4 | 328 | { |
2bfd65e4 AK |
329 | unsigned long rts_field; |
330 | struct memblock_region *reg; | |
2bfd65e4 AK |
331 | |
332 | /* We don't support slb for radix */ | |
333 | mmu_slb_size = 0; | |
334 | /* | |
335 | * Create the linear mapping, using standard page size for now | |
336 | */ | |
2ad452ff NP |
337 | for_each_memblock(memory, reg) { |
338 | /* | |
339 | * The memblock allocator is up at this point, so the | |
340 | * page tables will be allocated within the range. No | |
341 | * need or a node (which we don't have yet). | |
342 | */ | |
e0909392 AK |
343 | |
344 | if ((reg->base + reg->size) >= RADIX_VMALLOC_START) { | |
f341d897 | 345 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
346 | continue; |
347 | } | |
348 | ||
b5200ec9 | 349 | WARN_ON(create_physical_mapping(reg->base, |
2ad452ff NP |
350 | reg->base + reg->size, |
351 | -1)); | |
352 | } | |
a25bd72b BH |
353 | |
354 | /* Find out how many PID bits are supported */ | |
355 | if (cpu_has_feature(CPU_FTR_HVMODE)) { | |
356 | if (!mmu_pid_bits) | |
357 | mmu_pid_bits = 20; | |
358 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE | |
359 | /* | |
360 | * When KVM is possible, we only use the top half of the | |
361 | * PID space to avoid collisions between host and guest PIDs | |
362 | * which can cause problems due to prefetch when exiting the | |
363 | * guest with AIL=3 | |
364 | */ | |
365 | mmu_base_pid = 1 << (mmu_pid_bits - 1); | |
366 | #else | |
367 | mmu_base_pid = 1; | |
368 | #endif | |
369 | } else { | |
370 | /* The guest uses the bottom half of the PID space */ | |
371 | if (!mmu_pid_bits) | |
372 | mmu_pid_bits = 19; | |
373 | mmu_base_pid = 1; | |
374 | } | |
375 | ||
2bfd65e4 AK |
376 | /* |
377 | * Allocate Partition table and process table for the | |
378 | * host. | |
379 | */ | |
a25bd72b | 380 | BUG_ON(PRTB_SIZE_SHIFT > 36); |
2ad452ff | 381 | process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0); |
2bfd65e4 AK |
382 | /* |
383 | * Fill in the process table. | |
2bfd65e4 | 384 | */ |
b23d9c5b | 385 | rts_field = radix__get_tree_size(); |
2bfd65e4 AK |
386 | process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE); |
387 | /* | |
388 | * Fill in the partition table. We are suppose to use effective address | |
389 | * of process table here. But our linear mapping also enable us to use | |
390 | * physical address here. | |
391 | */ | |
eea8148c | 392 | register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12); |
2bfd65e4 | 393 | pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd); |
7a70d728 PM |
394 | asm volatile("ptesync" : : : "memory"); |
395 | asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : : | |
396 | "r" (TLBIEL_INVAL_SET_LPID), "r" (0)); | |
397 | asm volatile("eieio; tlbsync; ptesync" : : : "memory"); | |
0428491c | 398 | trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1); |
eeb715c3 NP |
399 | |
400 | /* | |
401 | * The init_mm context is given the first available (non-zero) PID, | |
402 | * which is the "guard PID" and contains no page table. PIDR should | |
403 | * never be set to zero because that duplicates the kernel address | |
404 | * space at the 0x0... offset (quadrant 0)! | |
405 | * | |
406 | * An arbitrary PID that may later be allocated by the PID allocator | |
407 | * for userspace processes must not be used either, because that | |
408 | * would cause stale user mappings for that PID on CPUs outside of | |
409 | * the TLB invalidation scheme (because it won't be in mm_cpumask). | |
410 | * | |
411 | * So permanently carve out one PID for the purpose of a guard PID. | |
412 | */ | |
413 | init_mm.context.id = mmu_base_pid; | |
414 | mmu_base_pid++; | |
2bfd65e4 AK |
415 | } |
416 | ||
417 | static void __init radix_init_partition_table(void) | |
418 | { | |
9d661958 | 419 | unsigned long rts_field, dw0; |
b23d9c5b | 420 | |
9d661958 | 421 | mmu_partition_table_init(); |
b23d9c5b | 422 | rts_field = radix__get_tree_size(); |
9d661958 PM |
423 | dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR; |
424 | mmu_partition_table_set_entry(0, dw0, 0); | |
2bfd65e4 | 425 | |
56547411 AK |
426 | pr_info("Initializing Radix MMU\n"); |
427 | pr_info("Partition table %p\n", partition_tb); | |
2bfd65e4 AK |
428 | } |
429 | ||
430 | void __init radix_init_native(void) | |
431 | { | |
eea8148c | 432 | register_process_table = native_register_process_table; |
2bfd65e4 AK |
433 | } |
434 | ||
435 | static int __init get_idx_from_shift(unsigned int shift) | |
436 | { | |
437 | int idx = -1; | |
438 | ||
439 | switch (shift) { | |
440 | case 0xc: | |
441 | idx = MMU_PAGE_4K; | |
442 | break; | |
443 | case 0x10: | |
444 | idx = MMU_PAGE_64K; | |
445 | break; | |
446 | case 0x15: | |
447 | idx = MMU_PAGE_2M; | |
448 | break; | |
449 | case 0x1e: | |
450 | idx = MMU_PAGE_1G; | |
451 | break; | |
452 | } | |
453 | return idx; | |
454 | } | |
455 | ||
456 | static int __init radix_dt_scan_page_sizes(unsigned long node, | |
457 | const char *uname, int depth, | |
458 | void *data) | |
459 | { | |
460 | int size = 0; | |
461 | int shift, idx; | |
462 | unsigned int ap; | |
463 | const __be32 *prop; | |
464 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
465 | ||
466 | /* We are scanning "cpu" nodes only */ | |
467 | if (type == NULL || strcmp(type, "cpu") != 0) | |
468 | return 0; | |
469 | ||
a25bd72b BH |
470 | /* Find MMU PID size */ |
471 | prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size); | |
472 | if (prop && size == 4) | |
473 | mmu_pid_bits = be32_to_cpup(prop); | |
474 | ||
475 | /* Grab page size encodings */ | |
2bfd65e4 AK |
476 | prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size); |
477 | if (!prop) | |
478 | return 0; | |
479 | ||
480 | pr_info("Page sizes from device-tree:\n"); | |
481 | for (; size >= 4; size -= 4, ++prop) { | |
482 | ||
483 | struct mmu_psize_def *def; | |
484 | ||
485 | /* top 3 bit is AP encoding */ | |
486 | shift = be32_to_cpu(prop[0]) & ~(0xe << 28); | |
487 | ap = be32_to_cpu(prop[0]) >> 29; | |
ac8d3818 | 488 | pr_info("Page size shift = %d AP=0x%x\n", shift, ap); |
2bfd65e4 AK |
489 | |
490 | idx = get_idx_from_shift(shift); | |
491 | if (idx < 0) | |
492 | continue; | |
493 | ||
494 | def = &mmu_psize_defs[idx]; | |
495 | def->shift = shift; | |
496 | def->ap = ap; | |
497 | } | |
498 | ||
499 | /* needed ? */ | |
500 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; | |
501 | return 1; | |
502 | } | |
503 | ||
2537b09c | 504 | void __init radix__early_init_devtree(void) |
2bfd65e4 AK |
505 | { |
506 | int rc; | |
507 | ||
508 | /* | |
509 | * Try to find the available page sizes in the device-tree | |
510 | */ | |
511 | rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL); | |
512 | if (rc != 0) /* Found */ | |
513 | goto found; | |
514 | /* | |
515 | * let's assume we have page 4k and 64k support | |
516 | */ | |
517 | mmu_psize_defs[MMU_PAGE_4K].shift = 12; | |
518 | mmu_psize_defs[MMU_PAGE_4K].ap = 0x0; | |
519 | ||
520 | mmu_psize_defs[MMU_PAGE_64K].shift = 16; | |
521 | mmu_psize_defs[MMU_PAGE_64K].ap = 0x5; | |
522 | found: | |
2bfd65e4 AK |
523 | return; |
524 | } | |
525 | ||
ee97b6b9 BS |
526 | static void radix_init_amor(void) |
527 | { | |
528 | /* | |
529 | * In HV mode, we init AMOR (Authority Mask Override Register) so that | |
530 | * the hypervisor and guest can setup IAMR (Instruction Authority Mask | |
531 | * Register), enable key 0 and set it to 1. | |
532 | * | |
533 | * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11) | |
534 | */ | |
535 | mtspr(SPRN_AMOR, (3ul << 62)); | |
536 | } | |
537 | ||
1bb2bae2 RC |
538 | #ifdef CONFIG_PPC_KUEP |
539 | void setup_kuep(bool disabled) | |
3b10d009 | 540 | { |
1bb2bae2 RC |
541 | if (disabled || !early_radix_enabled()) |
542 | return; | |
543 | ||
544 | if (smp_processor_id() == boot_cpuid) | |
545 | pr_info("Activating Kernel Userspace Execution Prevention\n"); | |
546 | ||
3b10d009 BS |
547 | /* |
548 | * Radix always uses key0 of the IAMR to determine if an access is | |
549 | * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction | |
550 | * fetch. | |
551 | */ | |
2bf1071a | 552 | mtspr(SPRN_IAMR, (1ul << 62)); |
3b10d009 | 553 | } |
1bb2bae2 | 554 | #endif |
3b10d009 | 555 | |
890274c2 ME |
556 | #ifdef CONFIG_PPC_KUAP |
557 | void setup_kuap(bool disabled) | |
558 | { | |
559 | if (disabled || !early_radix_enabled()) | |
560 | return; | |
561 | ||
562 | if (smp_processor_id() == boot_cpuid) { | |
563 | pr_info("Activating Kernel Userspace Access Prevention\n"); | |
564 | cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_KUAP; | |
565 | } | |
566 | ||
567 | /* Make sure userspace can't change the AMR */ | |
568 | mtspr(SPRN_UAMOR, 0); | |
569 | mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); | |
570 | isync(); | |
571 | } | |
572 | #endif | |
573 | ||
2bfd65e4 AK |
574 | void __init radix__early_init_mmu(void) |
575 | { | |
576 | unsigned long lpcr; | |
2bfd65e4 AK |
577 | |
578 | #ifdef CONFIG_PPC_64K_PAGES | |
579 | /* PAGE_SIZE mappings */ | |
580 | mmu_virtual_psize = MMU_PAGE_64K; | |
581 | #else | |
582 | mmu_virtual_psize = MMU_PAGE_4K; | |
583 | #endif | |
584 | ||
585 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
586 | /* vmemmap mapping */ | |
89a3496e AK |
587 | if (mmu_psize_defs[MMU_PAGE_2M].shift) { |
588 | /* | |
589 | * map vmemmap using 2M if available | |
590 | */ | |
591 | mmu_vmemmap_psize = MMU_PAGE_2M; | |
592 | } else | |
593 | mmu_vmemmap_psize = mmu_virtual_psize; | |
2bfd65e4 AK |
594 | #endif |
595 | /* | |
596 | * initialize page table size | |
597 | */ | |
598 | __pte_index_size = RADIX_PTE_INDEX_SIZE; | |
599 | __pmd_index_size = RADIX_PMD_INDEX_SIZE; | |
600 | __pud_index_size = RADIX_PUD_INDEX_SIZE; | |
601 | __pgd_index_size = RADIX_PGD_INDEX_SIZE; | |
fae22116 | 602 | __pud_cache_index = RADIX_PUD_INDEX_SIZE; |
2bfd65e4 AK |
603 | __pte_table_size = RADIX_PTE_TABLE_SIZE; |
604 | __pmd_table_size = RADIX_PMD_TABLE_SIZE; | |
605 | __pud_table_size = RADIX_PUD_TABLE_SIZE; | |
606 | __pgd_table_size = RADIX_PGD_TABLE_SIZE; | |
607 | ||
a2f41eb9 AK |
608 | __pmd_val_bits = RADIX_PMD_VAL_BITS; |
609 | __pud_val_bits = RADIX_PUD_VAL_BITS; | |
610 | __pgd_val_bits = RADIX_PGD_VAL_BITS; | |
2bfd65e4 | 611 | |
d6a9996e | 612 | __kernel_virt_start = RADIX_KERN_VIRT_START; |
d6a9996e AK |
613 | __vmalloc_start = RADIX_VMALLOC_START; |
614 | __vmalloc_end = RADIX_VMALLOC_END; | |
63ee9b2f | 615 | __kernel_io_start = RADIX_KERN_IO_START; |
a35a3c6f | 616 | __kernel_io_end = RADIX_KERN_IO_END; |
0034d395 | 617 | vmemmap = (struct page *)RADIX_VMEMMAP_START; |
d6a9996e | 618 | ioremap_bot = IOREMAP_BASE; |
bfa37087 DS |
619 | |
620 | #ifdef CONFIG_PCI | |
621 | pci_io_base = ISA_IO_BASE; | |
622 | #endif | |
fb4e5dbd AK |
623 | __pte_frag_nr = RADIX_PTE_FRAG_NR; |
624 | __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT; | |
8a6c697b AK |
625 | __pmd_frag_nr = RADIX_PMD_FRAG_NR; |
626 | __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT; | |
d6a9996e | 627 | |
d6c88600 | 628 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
166dd7d3 | 629 | radix_init_native(); |
d6c88600 | 630 | lpcr = mfspr(SPRN_LPCR); |
bf16cdf4 | 631 | mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); |
2bfd65e4 | 632 | radix_init_partition_table(); |
ee97b6b9 | 633 | radix_init_amor(); |
cc3d2940 PM |
634 | } else { |
635 | radix_init_pseries(); | |
d6c88600 | 636 | } |
2bfd65e4 | 637 | |
9d661958 PM |
638 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); |
639 | ||
2bfd65e4 | 640 | radix_init_pgtable(); |
eeb715c3 NP |
641 | /* Switch to the guard PID before turning on MMU */ |
642 | radix__switch_mmu_context(NULL, &init_mm); | |
d4748276 NP |
643 | if (cpu_has_feature(CPU_FTR_HVMODE)) |
644 | tlbiel_all(); | |
2bfd65e4 AK |
645 | } |
646 | ||
647 | void radix__early_init_mmu_secondary(void) | |
648 | { | |
649 | unsigned long lpcr; | |
650 | /* | |
d6c88600 | 651 | * update partition table control register and UPRT |
2bfd65e4 | 652 | */ |
d6c88600 AK |
653 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { |
654 | lpcr = mfspr(SPRN_LPCR); | |
bf16cdf4 | 655 | mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); |
d6c88600 | 656 | |
2bfd65e4 AK |
657 | mtspr(SPRN_PTCR, |
658 | __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); | |
ee97b6b9 | 659 | radix_init_amor(); |
d6c88600 | 660 | } |
d4748276 | 661 | |
eeb715c3 | 662 | radix__switch_mmu_context(NULL, &init_mm); |
d4748276 NP |
663 | if (cpu_has_feature(CPU_FTR_HVMODE)) |
664 | tlbiel_all(); | |
2bfd65e4 AK |
665 | } |
666 | ||
fe036a06 BH |
667 | void radix__mmu_cleanup_all(void) |
668 | { | |
669 | unsigned long lpcr; | |
670 | ||
671 | if (!firmware_has_feature(FW_FEATURE_LPAR)) { | |
672 | lpcr = mfspr(SPRN_LPCR); | |
673 | mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); | |
674 | mtspr(SPRN_PTCR, 0); | |
1d0761d2 | 675 | powernv_set_nmmu_ptcr(0); |
fe036a06 BH |
676 | radix__flush_tlb_all(); |
677 | } | |
678 | } | |
679 | ||
2bfd65e4 AK |
680 | void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base, |
681 | phys_addr_t first_memblock_size) | |
682 | { | |
47d99948 CL |
683 | /* |
684 | * We don't currently support the first MEMBLOCK not mapping 0 | |
177ba7c6 AK |
685 | * physical on those processors |
686 | */ | |
687 | BUG_ON(first_memblock_base != 0); | |
1513c33d | 688 | |
5eae82ca NP |
689 | /* |
690 | * Radix mode is not limited by RMA / VRMA addressing. | |
691 | */ | |
692 | ppc64_rma_size = ULONG_MAX; | |
2bfd65e4 | 693 | } |
d9225ad9 | 694 | |
6cc27341 | 695 | #ifdef CONFIG_MEMORY_HOTPLUG |
4b5d62ca RA |
696 | static void free_pte_table(pte_t *pte_start, pmd_t *pmd) |
697 | { | |
698 | pte_t *pte; | |
699 | int i; | |
700 | ||
701 | for (i = 0; i < PTRS_PER_PTE; i++) { | |
702 | pte = pte_start + i; | |
703 | if (!pte_none(*pte)) | |
704 | return; | |
705 | } | |
706 | ||
707 | pte_free_kernel(&init_mm, pte_start); | |
708 | pmd_clear(pmd); | |
709 | } | |
710 | ||
711 | static void free_pmd_table(pmd_t *pmd_start, pud_t *pud) | |
712 | { | |
713 | pmd_t *pmd; | |
714 | int i; | |
715 | ||
716 | for (i = 0; i < PTRS_PER_PMD; i++) { | |
717 | pmd = pmd_start + i; | |
718 | if (!pmd_none(*pmd)) | |
719 | return; | |
720 | } | |
721 | ||
722 | pmd_free(&init_mm, pmd_start); | |
723 | pud_clear(pud); | |
724 | } | |
725 | ||
4dd5f8a9 BS |
726 | struct change_mapping_params { |
727 | pte_t *pte; | |
728 | unsigned long start; | |
729 | unsigned long end; | |
730 | unsigned long aligned_start; | |
731 | unsigned long aligned_end; | |
732 | }; | |
733 | ||
bde709a7 | 734 | static int __meminit stop_machine_change_mapping(void *data) |
4dd5f8a9 BS |
735 | { |
736 | struct change_mapping_params *params = | |
737 | (struct change_mapping_params *)data; | |
738 | ||
739 | if (!data) | |
740 | return -1; | |
741 | ||
742 | spin_unlock(&init_mm.page_table_lock); | |
743 | pte_clear(&init_mm, params->aligned_start, params->pte); | |
f437c517 ME |
744 | create_physical_mapping(params->aligned_start, params->start, -1); |
745 | create_physical_mapping(params->end, params->aligned_end, -1); | |
4dd5f8a9 BS |
746 | spin_lock(&init_mm.page_table_lock); |
747 | return 0; | |
748 | } | |
749 | ||
4b5d62ca RA |
750 | static void remove_pte_table(pte_t *pte_start, unsigned long addr, |
751 | unsigned long end) | |
752 | { | |
753 | unsigned long next; | |
754 | pte_t *pte; | |
755 | ||
756 | pte = pte_start + pte_index(addr); | |
757 | for (; addr < end; addr = next, pte++) { | |
758 | next = (addr + PAGE_SIZE) & PAGE_MASK; | |
759 | if (next > end) | |
760 | next = end; | |
761 | ||
762 | if (!pte_present(*pte)) | |
763 | continue; | |
764 | ||
0d0a4bc2 RA |
765 | if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) { |
766 | /* | |
767 | * The vmemmap_free() and remove_section_mapping() | |
768 | * codepaths call us with aligned addresses. | |
769 | */ | |
770 | WARN_ONCE(1, "%s: unaligned range\n", __func__); | |
771 | continue; | |
772 | } | |
773 | ||
4b5d62ca RA |
774 | pte_clear(&init_mm, addr, pte); |
775 | } | |
776 | } | |
777 | ||
4dd5f8a9 BS |
778 | /* |
779 | * clear the pte and potentially split the mapping helper | |
780 | */ | |
bde709a7 | 781 | static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end, |
4dd5f8a9 BS |
782 | unsigned long size, pte_t *pte) |
783 | { | |
784 | unsigned long mask = ~(size - 1); | |
785 | unsigned long aligned_start = addr & mask; | |
786 | unsigned long aligned_end = addr + size; | |
787 | struct change_mapping_params params; | |
788 | bool split_region = false; | |
789 | ||
790 | if ((end - addr) < size) { | |
791 | /* | |
792 | * We're going to clear the PTE, but not flushed | |
793 | * the mapping, time to remap and flush. The | |
794 | * effects if visible outside the processor or | |
795 | * if we are running in code close to the | |
796 | * mapping we cleared, we are in trouble. | |
797 | */ | |
798 | if (overlaps_kernel_text(aligned_start, addr) || | |
799 | overlaps_kernel_text(end, aligned_end)) { | |
800 | /* | |
801 | * Hack, just return, don't pte_clear | |
802 | */ | |
803 | WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel " | |
804 | "text, not splitting\n", addr, end); | |
805 | return; | |
806 | } | |
807 | split_region = true; | |
808 | } | |
809 | ||
810 | if (split_region) { | |
811 | params.pte = pte; | |
812 | params.start = addr; | |
813 | params.end = end; | |
814 | params.aligned_start = addr & ~(size - 1); | |
815 | params.aligned_end = min_t(unsigned long, aligned_end, | |
816 | (unsigned long)__va(memblock_end_of_DRAM())); | |
817 | stop_machine(stop_machine_change_mapping, ¶ms, NULL); | |
818 | return; | |
819 | } | |
820 | ||
821 | pte_clear(&init_mm, addr, pte); | |
822 | } | |
823 | ||
4b5d62ca RA |
824 | static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr, |
825 | unsigned long end) | |
826 | { | |
827 | unsigned long next; | |
828 | pte_t *pte_base; | |
829 | pmd_t *pmd; | |
830 | ||
831 | pmd = pmd_start + pmd_index(addr); | |
832 | for (; addr < end; addr = next, pmd++) { | |
833 | next = pmd_addr_end(addr, end); | |
834 | ||
835 | if (!pmd_present(*pmd)) | |
836 | continue; | |
837 | ||
838 | if (pmd_huge(*pmd)) { | |
4dd5f8a9 | 839 | split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd); |
4b5d62ca RA |
840 | continue; |
841 | } | |
842 | ||
843 | pte_base = (pte_t *)pmd_page_vaddr(*pmd); | |
844 | remove_pte_table(pte_base, addr, next); | |
845 | free_pte_table(pte_base, pmd); | |
846 | } | |
847 | } | |
848 | ||
849 | static void remove_pud_table(pud_t *pud_start, unsigned long addr, | |
850 | unsigned long end) | |
851 | { | |
852 | unsigned long next; | |
853 | pmd_t *pmd_base; | |
854 | pud_t *pud; | |
855 | ||
856 | pud = pud_start + pud_index(addr); | |
857 | for (; addr < end; addr = next, pud++) { | |
858 | next = pud_addr_end(addr, end); | |
859 | ||
860 | if (!pud_present(*pud)) | |
861 | continue; | |
862 | ||
863 | if (pud_huge(*pud)) { | |
4dd5f8a9 | 864 | split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud); |
4b5d62ca RA |
865 | continue; |
866 | } | |
867 | ||
868 | pmd_base = (pmd_t *)pud_page_vaddr(*pud); | |
869 | remove_pmd_table(pmd_base, addr, next); | |
870 | free_pmd_table(pmd_base, pud); | |
871 | } | |
872 | } | |
873 | ||
bde709a7 | 874 | static void __meminit remove_pagetable(unsigned long start, unsigned long end) |
4b5d62ca RA |
875 | { |
876 | unsigned long addr, next; | |
877 | pud_t *pud_base; | |
878 | pgd_t *pgd; | |
879 | ||
880 | spin_lock(&init_mm.page_table_lock); | |
881 | ||
882 | for (addr = start; addr < end; addr = next) { | |
883 | next = pgd_addr_end(addr, end); | |
884 | ||
885 | pgd = pgd_offset_k(addr); | |
886 | if (!pgd_present(*pgd)) | |
887 | continue; | |
888 | ||
889 | if (pgd_huge(*pgd)) { | |
4dd5f8a9 | 890 | split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd); |
4b5d62ca RA |
891 | continue; |
892 | } | |
893 | ||
894 | pud_base = (pud_t *)pgd_page_vaddr(*pgd); | |
895 | remove_pud_table(pud_base, addr, next); | |
896 | } | |
897 | ||
898 | spin_unlock(&init_mm.page_table_lock); | |
899 | radix__flush_tlb_kernel_range(start, end); | |
900 | } | |
901 | ||
f437c517 | 902 | int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid) |
6cc27341 | 903 | { |
e0909392 | 904 | if (end >= RADIX_VMALLOC_START) { |
f341d897 | 905 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
906 | return -1; |
907 | } | |
908 | ||
29ab6c47 | 909 | return create_physical_mapping(start, end, nid); |
6cc27341 | 910 | } |
4b5d62ca | 911 | |
bde709a7 | 912 | int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end) |
4b5d62ca RA |
913 | { |
914 | remove_pagetable(start, end); | |
915 | return 0; | |
916 | } | |
6cc27341 RA |
917 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
918 | ||
d9225ad9 | 919 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
29ab6c47 NP |
920 | static int __map_kernel_page_nid(unsigned long ea, unsigned long pa, |
921 | pgprot_t flags, unsigned int map_page_size, | |
922 | int nid) | |
923 | { | |
924 | return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0); | |
925 | } | |
926 | ||
d9225ad9 AK |
927 | int __meminit radix__vmemmap_create_mapping(unsigned long start, |
928 | unsigned long page_size, | |
929 | unsigned long phys) | |
930 | { | |
931 | /* Create a PTE encoding */ | |
932 | unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW; | |
2ad452ff NP |
933 | int nid = early_pfn_to_nid(phys >> PAGE_SHIFT); |
934 | int ret; | |
935 | ||
e0909392 | 936 | if ((start + page_size) >= RADIX_VMEMMAP_END) { |
f341d897 | 937 | pr_warn("Outside the supported range\n"); |
e0909392 AK |
938 | return -1; |
939 | } | |
940 | ||
2ad452ff NP |
941 | ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid); |
942 | BUG_ON(ret); | |
d9225ad9 | 943 | |
d9225ad9 AK |
944 | return 0; |
945 | } | |
946 | ||
947 | #ifdef CONFIG_MEMORY_HOTPLUG | |
bde709a7 | 948 | void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size) |
d9225ad9 | 949 | { |
0d0a4bc2 | 950 | remove_pagetable(start, start + page_size); |
d9225ad9 AK |
951 | } |
952 | #endif | |
953 | #endif | |
bde3eb62 AK |
954 | |
955 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
956 | ||
957 | unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, | |
958 | pmd_t *pmdp, unsigned long clr, | |
959 | unsigned long set) | |
960 | { | |
961 | unsigned long old; | |
962 | ||
963 | #ifdef CONFIG_DEBUG_VM | |
ebd31197 | 964 | WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp)); |
af60a4cf | 965 | assert_spin_locked(pmd_lockptr(mm, pmdp)); |
bde3eb62 AK |
966 | #endif |
967 | ||
968 | old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1); | |
969 | trace_hugepage_update(addr, old, clr, set); | |
970 | ||
971 | return old; | |
972 | } | |
973 | ||
974 | pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address, | |
975 | pmd_t *pmdp) | |
976 | ||
977 | { | |
978 | pmd_t pmd; | |
979 | ||
980 | VM_BUG_ON(address & ~HPAGE_PMD_MASK); | |
981 | VM_BUG_ON(radix__pmd_trans_huge(*pmdp)); | |
ebd31197 | 982 | VM_BUG_ON(pmd_devmap(*pmdp)); |
bde3eb62 AK |
983 | /* |
984 | * khugepaged calls this for normal pmd | |
985 | */ | |
986 | pmd = *pmdp; | |
987 | pmd_clear(pmdp); | |
424de9c6 | 988 | |
bde3eb62 | 989 | /*FIXME!! Verify whether we need this kick below */ |
fa4531f7 | 990 | serialize_against_pte_lookup(vma->vm_mm); |
424de9c6 BH |
991 | |
992 | radix__flush_tlb_collapsed_pmd(vma->vm_mm, address); | |
993 | ||
bde3eb62 AK |
994 | return pmd; |
995 | } | |
996 | ||
997 | /* | |
998 | * For us pgtable_t is pte_t *. Inorder to save the deposisted | |
999 | * page table, we consider the allocated page table as a list | |
1000 | * head. On withdraw we need to make sure we zero out the used | |
1001 | * list_head memory area. | |
1002 | */ | |
1003 | void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
1004 | pgtable_t pgtable) | |
1005 | { | |
47d99948 | 1006 | struct list_head *lh = (struct list_head *) pgtable; |
bde3eb62 | 1007 | |
47d99948 | 1008 | assert_spin_locked(pmd_lockptr(mm, pmdp)); |
bde3eb62 | 1009 | |
47d99948 CL |
1010 | /* FIFO */ |
1011 | if (!pmd_huge_pte(mm, pmdp)) | |
1012 | INIT_LIST_HEAD(lh); | |
1013 | else | |
1014 | list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp)); | |
1015 | pmd_huge_pte(mm, pmdp) = pgtable; | |
bde3eb62 AK |
1016 | } |
1017 | ||
1018 | pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp) | |
1019 | { | |
47d99948 CL |
1020 | pte_t *ptep; |
1021 | pgtable_t pgtable; | |
1022 | struct list_head *lh; | |
bde3eb62 | 1023 | |
47d99948 CL |
1024 | assert_spin_locked(pmd_lockptr(mm, pmdp)); |
1025 | ||
1026 | /* FIFO */ | |
1027 | pgtable = pmd_huge_pte(mm, pmdp); | |
1028 | lh = (struct list_head *) pgtable; | |
1029 | if (list_empty(lh)) | |
1030 | pmd_huge_pte(mm, pmdp) = NULL; | |
1031 | else { | |
1032 | pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next; | |
1033 | list_del(lh); | |
1034 | } | |
1035 | ptep = (pte_t *) pgtable; | |
1036 | *ptep = __pte(0); | |
1037 | ptep++; | |
1038 | *ptep = __pte(0); | |
1039 | return pgtable; | |
1040 | } | |
bde3eb62 AK |
1041 | |
1042 | pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm, | |
47d99948 | 1043 | unsigned long addr, pmd_t *pmdp) |
bde3eb62 AK |
1044 | { |
1045 | pmd_t old_pmd; | |
1046 | unsigned long old; | |
1047 | ||
1048 | old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0); | |
1049 | old_pmd = __pmd(old); | |
1050 | /* | |
fa4531f7 | 1051 | * Serialize against find_current_mm_pte which does lock-less |
bde3eb62 AK |
1052 | * lookup in page tables with local interrupts disabled. For huge pages |
1053 | * it casts pmd_t to pte_t. Since format of pte_t is different from | |
1054 | * pmd_t we want to prevent transit from pmd pointing to page table | |
1055 | * to pmd pointing to huge page (and back) while interrupts are disabled. | |
1056 | * We clear pmd to possibly replace it with page table pointer in | |
1057 | * different code paths. So make sure we wait for the parallel | |
fa4531f7 | 1058 | * find_current_mm_pte to finish. |
bde3eb62 | 1059 | */ |
fa4531f7 | 1060 | serialize_against_pte_lookup(mm); |
bde3eb62 AK |
1061 | return old_pmd; |
1062 | } | |
1063 | ||
1064 | int radix__has_transparent_hugepage(void) | |
1065 | { | |
1066 | /* For radix 2M at PMD level means thp */ | |
1067 | if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT) | |
1068 | return 1; | |
1069 | return 0; | |
1070 | } | |
1071 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
044003b5 | 1072 | |
e4c1112c AK |
1073 | void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, |
1074 | pte_t entry, unsigned long address, int psize) | |
044003b5 | 1075 | { |
e4c1112c | 1076 | struct mm_struct *mm = vma->vm_mm; |
044003b5 AK |
1077 | unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | |
1078 | _PAGE_RW | _PAGE_EXEC); | |
f08d08f3 AK |
1079 | |
1080 | unsigned long change = pte_val(entry) ^ pte_val(*ptep); | |
bd5050e3 AK |
1081 | /* |
1082 | * To avoid NMMU hang while relaxing access, we need mark | |
1083 | * the pte invalid in between. | |
1084 | */ | |
f08d08f3 | 1085 | if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) { |
044003b5 AK |
1086 | unsigned long old_pte, new_pte; |
1087 | ||
f08d08f3 | 1088 | old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID); |
044003b5 AK |
1089 | /* |
1090 | * new value of pte | |
1091 | */ | |
1092 | new_pte = old_pte | set; | |
bd5050e3 | 1093 | radix__flush_tlb_page_psize(mm, address, psize); |
f08d08f3 | 1094 | __radix_pte_update(ptep, _PAGE_INVALID, new_pte); |
bd5050e3 | 1095 | } else { |
044003b5 | 1096 | __radix_pte_update(ptep, 0, set); |
e5f7cb58 NP |
1097 | /* |
1098 | * Book3S does not require a TLB flush when relaxing access | |
1099 | * restrictions when the address space is not attached to a | |
1100 | * NMMU, because the core MMU will reload the pte after taking | |
1101 | * an access fault, which is defined by the architectue. | |
1102 | */ | |
bd5050e3 | 1103 | } |
f1cb8f9b | 1104 | /* See ptesync comment in radix__set_pte_at */ |
044003b5 | 1105 | } |
5b323367 AK |
1106 | |
1107 | void radix__ptep_modify_prot_commit(struct vm_area_struct *vma, | |
1108 | unsigned long addr, pte_t *ptep, | |
1109 | pte_t old_pte, pte_t pte) | |
1110 | { | |
1111 | struct mm_struct *mm = vma->vm_mm; | |
1112 | ||
1113 | /* | |
1114 | * To avoid NMMU hang while relaxing access we need to flush the tlb before | |
1115 | * we set the new value. We need to do this only for radix, because hash | |
1116 | * translation does flush when updating the linux pte. | |
1117 | */ | |
1118 | if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) && | |
1119 | (atomic_read(&mm->context.copros) > 0)) | |
1120 | radix__flush_tlb_page(vma, addr); | |
1121 | ||
1122 | set_pte_at(mm, addr, ptep, pte); | |
1123 | } | |
d38153f9 | 1124 | |
d909f910 NP |
1125 | int __init arch_ioremap_pud_supported(void) |
1126 | { | |
1127 | /* HPT does not cope with large pages in the vmalloc area */ | |
1128 | return radix_enabled(); | |
1129 | } | |
1130 | ||
1131 | int __init arch_ioremap_pmd_supported(void) | |
1132 | { | |
1133 | return radix_enabled(); | |
1134 | } | |
1135 | ||
1136 | int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) | |
1137 | { | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) | |
1142 | { | |
1143 | pte_t *ptep = (pte_t *)pud; | |
1144 | pte_t new_pud = pfn_pte(__phys_to_pfn(addr), prot); | |
1145 | ||
1146 | if (!radix_enabled()) | |
1147 | return 0; | |
1148 | ||
1149 | set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pud); | |
1150 | ||
1151 | return 1; | |
1152 | } | |
1153 | ||
1154 | int pud_clear_huge(pud_t *pud) | |
1155 | { | |
1156 | if (pud_huge(*pud)) { | |
1157 | pud_clear(pud); | |
1158 | return 1; | |
1159 | } | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | int pud_free_pmd_page(pud_t *pud, unsigned long addr) | |
1165 | { | |
1166 | pmd_t *pmd; | |
1167 | int i; | |
1168 | ||
1169 | pmd = (pmd_t *)pud_page_vaddr(*pud); | |
1170 | pud_clear(pud); | |
1171 | ||
1172 | flush_tlb_kernel_range(addr, addr + PUD_SIZE); | |
1173 | ||
1174 | for (i = 0; i < PTRS_PER_PMD; i++) { | |
1175 | if (!pmd_none(pmd[i])) { | |
1176 | pte_t *pte; | |
1177 | pte = (pte_t *)pmd_page_vaddr(pmd[i]); | |
1178 | ||
1179 | pte_free_kernel(&init_mm, pte); | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | pmd_free(&init_mm, pmd); | |
1184 | ||
1185 | return 1; | |
1186 | } | |
1187 | ||
1188 | int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) | |
1189 | { | |
1190 | pte_t *ptep = (pte_t *)pmd; | |
1191 | pte_t new_pmd = pfn_pte(__phys_to_pfn(addr), prot); | |
1192 | ||
1193 | if (!radix_enabled()) | |
1194 | return 0; | |
1195 | ||
1196 | set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pmd); | |
1197 | ||
1198 | return 1; | |
1199 | } | |
1200 | ||
1201 | int pmd_clear_huge(pmd_t *pmd) | |
1202 | { | |
1203 | if (pmd_huge(*pmd)) { | |
1204 | pmd_clear(pmd); | |
1205 | return 1; | |
1206 | } | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) | |
1212 | { | |
1213 | pte_t *pte; | |
1214 | ||
1215 | pte = (pte_t *)pmd_page_vaddr(*pmd); | |
1216 | pmd_clear(pmd); | |
1217 | ||
1218 | flush_tlb_kernel_range(addr, addr + PMD_SIZE); | |
1219 | ||
1220 | pte_free_kernel(&init_mm, pte); | |
1221 | ||
1222 | return 1; | |
1223 | } | |
1224 | ||
d38153f9 NP |
1225 | int radix__ioremap_range(unsigned long ea, phys_addr_t pa, unsigned long size, |
1226 | pgprot_t prot, int nid) | |
1227 | { | |
1228 | if (likely(slab_is_available())) { | |
1229 | int err = ioremap_page_range(ea, ea + size, pa, prot); | |
1230 | if (err) | |
1231 | unmap_kernel_range(ea, size); | |
1232 | return err; | |
1233 | } else { | |
1234 | unsigned long i; | |
1235 | ||
1236 | for (i = 0; i < size; i += PAGE_SIZE) { | |
1237 | int err = map_kernel_page(ea + i, pa + i, prot); | |
1238 | if (WARN_ON_ONCE(err)) /* Should clean up */ | |
1239 | return err; | |
1240 | } | |
1241 | return 0; | |
1242 | } | |
1243 | } |