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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
48483760 AK |
2 | #include <linux/mm.h> |
3 | #include <linux/hugetlb.h> | |
5330367f | 4 | #include <linux/security.h> |
48483760 AK |
5 | #include <asm/cacheflush.h> |
6 | #include <asm/machdep.h> | |
7 | #include <asm/mman.h> | |
fbfa26d8 | 8 | #include <asm/tlb.h> |
48483760 AK |
9 | |
10 | void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr) | |
11 | { | |
fbfa26d8 | 12 | int psize; |
48483760 AK |
13 | struct hstate *hstate = hstate_file(vma->vm_file); |
14 | ||
fbfa26d8 AK |
15 | psize = hstate_get_psize(hstate); |
16 | radix__flush_tlb_page_psize(vma->vm_mm, vmaddr, psize); | |
48483760 AK |
17 | } |
18 | ||
19 | void radix__local_flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr) | |
20 | { | |
fbfa26d8 | 21 | int psize; |
48483760 AK |
22 | struct hstate *hstate = hstate_file(vma->vm_file); |
23 | ||
fbfa26d8 AK |
24 | psize = hstate_get_psize(hstate); |
25 | radix__local_flush_tlb_page_psize(vma->vm_mm, vmaddr, psize); | |
48483760 AK |
26 | } |
27 | ||
5491ae7b AK |
28 | void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma, unsigned long start, |
29 | unsigned long end) | |
30 | { | |
31 | int psize; | |
32 | struct hstate *hstate = hstate_file(vma->vm_file); | |
33 | ||
34 | psize = hstate_get_psize(hstate); | |
cec6515a AK |
35 | /* |
36 | * Flush PWC even if we get PUD_SIZE hugetlb invalidate to keep this simpler. | |
37 | */ | |
38 | if (end - start >= PUD_SIZE) | |
39 | radix__flush_tlb_pwc_range_psize(vma->vm_mm, start, end, psize); | |
40 | else | |
41 | radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize); | |
1af5a810 | 42 | mmu_notifier_arch_invalidate_secondary_tlbs(vma->vm_mm, start, end); |
5491ae7b AK |
43 | } |
44 | ||
8ef5cbde AK |
45 | void radix__huge_ptep_modify_prot_commit(struct vm_area_struct *vma, |
46 | unsigned long addr, pte_t *ptep, | |
47 | pte_t old_pte, pte_t pte) | |
48 | { | |
49 | struct mm_struct *mm = vma->vm_mm; | |
935d4f0c | 50 | unsigned long psize = huge_page_size(hstate_vma(vma)); |
8ef5cbde AK |
51 | |
52 | /* | |
2a8a0f42 NP |
53 | * POWER9 NMMU must flush the TLB after clearing the PTE before |
54 | * installing a PTE with more relaxed access permissions, see | |
55 | * radix__ptep_set_access_flags. | |
8ef5cbde | 56 | */ |
2a8a0f42 NP |
57 | if (!cpu_has_feature(CPU_FTR_ARCH_31) && |
58 | is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) && | |
59 | atomic_read(&mm->context.copros) > 0) | |
8ef5cbde AK |
60 | radix__flush_hugetlb_page(vma, addr); |
61 | ||
935d4f0c | 62 | set_huge_pte_at(vma->vm_mm, addr, ptep, pte, psize); |
8ef5cbde | 63 | } |