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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
14cf11af PM |
2 | /* |
3 | * This file contains the routines for handling the MMU on those | |
4 | * PowerPC implementations where the MMU substantially follows the | |
5 | * architecture specification. This includes the 6xx, 7xx, 7xxx, | |
0f369103 | 6 | * and 8260 implementations but excludes the 8xx and 4xx. |
14cf11af PM |
7 | * -- paulus |
8 | * | |
9 | * Derived from arch/ppc/mm/init.c: | |
10 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
11 | * | |
12 | * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) | |
13 | * and Cort Dougan (PReP) (cort@cs.nmt.edu) | |
14 | * Copyright (C) 1996 Paul Mackerras | |
14cf11af PM |
15 | * |
16 | * Derived from "arch/i386/mm/init.c" | |
17 | * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds | |
14cf11af PM |
18 | */ |
19 | ||
14cf11af PM |
20 | #include <linux/kernel.h> |
21 | #include <linux/mm.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/highmem.h> | |
95f72d1e | 24 | #include <linux/memblock.h> |
14cf11af | 25 | |
14cf11af PM |
26 | #include <asm/mmu.h> |
27 | #include <asm/machdep.h> | |
9efc74ff | 28 | #include <asm/code-patching.h> |
63b2bc61 | 29 | #include <asm/sections.h> |
14cf11af | 30 | |
9d9f2ccc | 31 | #include <mm/mmu_decl.h> |
14cf11af | 32 | |
69a1593a CL |
33 | u8 __initdata early_hash[SZ_256K] __aligned(SZ_256K) = {0}; |
34 | ||
6e980b5c CL |
35 | static struct hash_pte __initdata *Hash = (struct hash_pte *)early_hash; |
36 | static unsigned long __initdata Hash_size, Hash_mask; | |
37 | static unsigned int __initdata hash_mb, hash_mb2; | |
38 | unsigned long __initdata _SDR1; | |
14cf11af | 39 | |
316a4058 | 40 | struct ppc_bat BATS[8][2]; /* 8 pairs of IBAT, DBAT */ |
14cf11af | 41 | |
03d5b19c | 42 | static struct batrange { /* stores address ranges mapped by BATs */ |
14cf11af PM |
43 | unsigned long start; |
44 | unsigned long limit; | |
7c5c4325 | 45 | phys_addr_t phys; |
ee0339f2 | 46 | } bat_addrs[8]; |
14cf11af | 47 | |
f2655125 CL |
48 | #ifdef CONFIG_SMP |
49 | unsigned long mmu_hash_lock; | |
50 | #endif | |
51 | ||
14cf11af PM |
52 | /* |
53 | * Return PA for this VA if it is mapped by a BAT, or 0 | |
54 | */ | |
3084cdb7 | 55 | phys_addr_t v_block_mapped(unsigned long va) |
14cf11af PM |
56 | { |
57 | int b; | |
e93ba1b7 | 58 | for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b) |
14cf11af PM |
59 | if (va >= bat_addrs[b].start && va < bat_addrs[b].limit) |
60 | return bat_addrs[b].phys + (va - bat_addrs[b].start); | |
61 | return 0; | |
62 | } | |
63 | ||
64 | /* | |
65 | * Return VA for a given PA or 0 if not mapped | |
66 | */ | |
3084cdb7 | 67 | unsigned long p_block_mapped(phys_addr_t pa) |
14cf11af PM |
68 | { |
69 | int b; | |
e93ba1b7 | 70 | for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b) |
14cf11af PM |
71 | if (pa >= bat_addrs[b].phys |
72 | && pa < (bat_addrs[b].limit-bat_addrs[b].start) | |
73 | +bat_addrs[b].phys) | |
74 | return bat_addrs[b].start+(pa-bat_addrs[b].phys); | |
75 | return 0; | |
76 | } | |
77 | ||
d37823c3 | 78 | int __init find_free_bat(void) |
e4d6654e CL |
79 | { |
80 | int b; | |
2e38ea48 | 81 | int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4; |
e4d6654e | 82 | |
2e38ea48 CL |
83 | for (b = 0; b < n; b++) { |
84 | struct ppc_bat *bat = BATS[b]; | |
e4d6654e | 85 | |
2e38ea48 CL |
86 | if (!(bat[1].batu & 3)) |
87 | return b; | |
e4d6654e CL |
88 | } |
89 | return -1; | |
90 | } | |
91 | ||
12f36351 CL |
92 | /* |
93 | * This function calculates the size of the larger block usable to map the | |
94 | * beginning of an area based on the start address and size of that area: | |
8b14e1df | 95 | * - max block size is 256 on 6xx. |
12f36351 CL |
96 | * - base address must be aligned to the block size. So the maximum block size |
97 | * is identified by the lowest bit set to 1 in the base address (for instance | |
98 | * if base is 0x16000000, max size is 0x02000000). | |
99 | * - block size has to be a power of two. This is calculated by finding the | |
100 | * highest bit set to 1. | |
101 | */ | |
d37823c3 | 102 | unsigned int bat_block_size(unsigned long base, unsigned long top) |
e4d6654e | 103 | { |
8b14e1df | 104 | unsigned int max_size = SZ_256M; |
12f36351 | 105 | unsigned int base_shift = (ffs(base) - 1) & 31; |
e4d6654e CL |
106 | unsigned int block_shift = (fls(top - base) - 1) & 31; |
107 | ||
108 | return min3(max_size, 1U << base_shift, 1U << block_shift); | |
109 | } | |
110 | ||
5e04ae85 CL |
111 | /* |
112 | * Set up one of the IBAT (block address translation) register pairs. | |
113 | * The parameters are not checked; in particular size must be a power | |
114 | * of 2 between 128k and 256M. | |
5e04ae85 CL |
115 | */ |
116 | static void setibat(int index, unsigned long virt, phys_addr_t phys, | |
117 | unsigned int size, pgprot_t prot) | |
118 | { | |
119 | unsigned int bl = (size >> 17) - 1; | |
120 | int wimgxpp; | |
121 | struct ppc_bat *bat = BATS[index]; | |
122 | unsigned long flags = pgprot_val(prot); | |
123 | ||
124 | if (!cpu_has_feature(CPU_FTR_NEED_COHERENT)) | |
125 | flags &= ~_PAGE_COHERENT; | |
126 | ||
127 | wimgxpp = (flags & _PAGE_COHERENT) | (_PAGE_EXEC ? BPP_RX : BPP_XX); | |
128 | bat[0].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ | |
129 | bat[0].batl = BAT_PHYS_ADDR(phys) | wimgxpp; | |
a7858747 | 130 | if (!is_kernel_addr(virt)) |
5e04ae85 CL |
131 | bat[0].batu |= 1; /* Vp = 1 */ |
132 | } | |
133 | ||
134 | static void clearibat(int index) | |
135 | { | |
136 | struct ppc_bat *bat = BATS[index]; | |
137 | ||
138 | bat[0].batu = 0; | |
139 | bat[0].batl = 0; | |
140 | } | |
141 | ||
63b2bc61 | 142 | static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top) |
14cf11af | 143 | { |
e4d6654e | 144 | int idx; |
14cf11af | 145 | |
e4d6654e | 146 | while ((idx = find_free_bat()) != -1 && base != top) { |
d37823c3 | 147 | unsigned int size = bat_block_size(base, top); |
14cf11af | 148 | |
e4d6654e | 149 | if (size < 128 << 10) |
14cf11af | 150 | break; |
e4d6654e CL |
151 | setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X); |
152 | base += size; | |
14cf11af PM |
153 | } |
154 | ||
e4d6654e | 155 | return base; |
14cf11af PM |
156 | } |
157 | ||
63b2bc61 CL |
158 | unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) |
159 | { | |
12f36351 | 160 | unsigned long done; |
b150a4d1 | 161 | unsigned long border = (unsigned long)__srwx_boundary - PAGE_OFFSET; |
2a0fb3c1 | 162 | unsigned long size; |
63b2bc61 | 163 | |
2a0fb3c1 CL |
164 | size = roundup_pow_of_two((unsigned long)_einittext - PAGE_OFFSET); |
165 | setibat(0, PAGE_OFFSET, 0, size, PAGE_KERNEL_X); | |
035b19a1 | 166 | |
1ce84497 | 167 | if (debug_pagealloc_enabled_or_kfence()) { |
035b19a1 | 168 | pr_debug_once("Read-Write memory mapped without BATs\n"); |
2b279c03 CL |
169 | if (base >= border) |
170 | return base; | |
171 | if (top >= border) | |
172 | top = border; | |
173 | } | |
63b2bc61 CL |
174 | |
175 | if (!strict_kernel_rwx_enabled() || base >= border || top <= border) | |
176 | return __mmu_mapin_ram(base, top); | |
177 | ||
178 | done = __mmu_mapin_ram(base, border); | |
12f36351 | 179 | if (done != border) |
63b2bc61 CL |
180 | return done; |
181 | ||
12f36351 | 182 | return __mmu_mapin_ram(border, top); |
63b2bc61 CL |
183 | } |
184 | ||
c4964331 CL |
185 | static bool is_module_segment(unsigned long addr) |
186 | { | |
0a956d52 | 187 | if (!IS_ENABLED(CONFIG_EXECMEM)) |
c4964331 | 188 | return false; |
7bee31ad CL |
189 | if (addr < ALIGN_DOWN(MODULES_VADDR, SZ_256M)) |
190 | return false; | |
541cebb5 | 191 | if (addr > ALIGN(MODULES_END, SZ_256M) - 1) |
7bee31ad | 192 | return false; |
c4964331 CL |
193 | return true; |
194 | } | |
195 | ||
78cb0945 | 196 | int mmu_mark_initmem_nx(void) |
63b2bc61 CL |
197 | { |
198 | int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4; | |
199 | int i; | |
200 | unsigned long base = (unsigned long)_stext - PAGE_OFFSET; | |
37eb7ca9 | 201 | unsigned long top = ALIGN((unsigned long)_etext - PAGE_OFFSET, SZ_128K); |
4b19f96a | 202 | unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET; |
63b2bc61 CL |
203 | unsigned long size; |
204 | ||
37eb7ca9 | 205 | for (i = 0; i < nb - 1 && base < top;) { |
d37823c3 | 206 | size = bat_block_size(base, top); |
63b2bc61 CL |
207 | setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT); |
208 | base += size; | |
209 | } | |
210 | if (base < top) { | |
d37823c3 | 211 | size = bat_block_size(base, top); |
63b2bc61 | 212 | if ((top - base) > size) { |
63b2bc61 | 213 | size <<= 1; |
4b19f96a CL |
214 | if (strict_kernel_rwx_enabled() && base + size > border) |
215 | pr_warn("Some RW data is getting mapped X. " | |
216 | "Adjust CONFIG_DATA_SHIFT to avoid that.\n"); | |
63b2bc61 CL |
217 | } |
218 | setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT); | |
219 | base += size; | |
220 | } | |
221 | for (; i < nb; i++) | |
222 | clearibat(i); | |
223 | ||
224 | update_bats(); | |
225 | ||
226 | for (i = TASK_SIZE >> 28; i < 16; i++) { | |
227 | /* Do not set NX on VM space for modules */ | |
c4964331 CL |
228 | if (is_module_segment(i << 28)) |
229 | continue; | |
230 | ||
179ae57d | 231 | mtsr(mfsr(i << 28) | 0x10000000, i << 28); |
63b2bc61 | 232 | } |
78cb0945 | 233 | return 0; |
63b2bc61 CL |
234 | } |
235 | ||
78cb0945 | 236 | int mmu_mark_rodata_ro(void) |
63b2bc61 CL |
237 | { |
238 | int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4; | |
239 | int i; | |
240 | ||
63b2bc61 CL |
241 | for (i = 0; i < nb; i++) { |
242 | struct ppc_bat *bat = BATS[i]; | |
243 | ||
7082f8e7 | 244 | if (bat_addrs[i].start < (unsigned long)__end_rodata) |
63b2bc61 CL |
245 | bat[1].batl = (bat[1].batl & ~BPP_RW) | BPP_RX; |
246 | } | |
247 | ||
248 | update_bats(); | |
78cb0945 CL |
249 | |
250 | return 0; | |
63b2bc61 CL |
251 | } |
252 | ||
14cf11af | 253 | /* |
2a0fb3c1 | 254 | * Set up one of the D BAT (block address translation) register pairs. |
14cf11af PM |
255 | * The parameters are not checked; in particular size must be a power |
256 | * of 2 between 128k and 256M. | |
257 | */ | |
7c5c4325 | 258 | void __init setbat(int index, unsigned long virt, phys_addr_t phys, |
5dd4e4f6 | 259 | unsigned int size, pgprot_t prot) |
14cf11af PM |
260 | { |
261 | unsigned int bl; | |
262 | int wimgxpp; | |
cbcaff7d | 263 | struct ppc_bat *bat; |
5dd4e4f6 | 264 | unsigned long flags = pgprot_val(prot); |
14cf11af | 265 | |
cbcaff7d CL |
266 | if (index == -1) |
267 | index = find_free_bat(); | |
268 | if (index == -1) { | |
269 | pr_err("%s: no BAT available for mapping 0x%llx\n", __func__, | |
270 | (unsigned long long)phys); | |
271 | return; | |
272 | } | |
273 | bat = BATS[index]; | |
274 | ||
4c456a67 GP |
275 | if ((flags & _PAGE_NO_CACHE) || |
276 | (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0)) | |
277 | flags &= ~_PAGE_COHERENT; | |
14cf11af PM |
278 | |
279 | bl = (size >> 17) - 1; | |
2e38ea48 CL |
280 | /* Do DBAT first */ |
281 | wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE | |
282 | | _PAGE_COHERENT | _PAGE_GUARDED); | |
46ebef51 | 283 | wimgxpp |= (flags & _PAGE_WRITE) ? BPP_RW : BPP_RX; |
2e38ea48 CL |
284 | bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ |
285 | bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp; | |
a7858747 | 286 | if (!is_kernel_addr(virt)) |
2e38ea48 CL |
287 | bat[1].batu |= 1; /* Vp = 1 */ |
288 | if (flags & _PAGE_GUARDED) { | |
289 | /* G bit must be zero in IBATs */ | |
290 | flags &= ~_PAGE_EXEC; | |
14cf11af PM |
291 | } |
292 | ||
293 | bat_addrs[index].start = virt; | |
294 | bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1; | |
295 | bat_addrs[index].phys = phys; | |
296 | } | |
297 | ||
3c726f8d BH |
298 | /* |
299 | * Preload a translation in the hash table | |
300 | */ | |
79d1befe | 301 | static void hash_preload(struct mm_struct *mm, unsigned long ea) |
3c726f8d BH |
302 | { |
303 | pmd_t *pmd; | |
304 | ||
4cc445b4 | 305 | if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) |
3c726f8d | 306 | return; |
e05c7b1f | 307 | pmd = pmd_off(mm, ea); |
3c726f8d | 308 | if (!pmd_none(*pmd)) |
6218a761 | 309 | add_hash_page(mm->context.id, ea, pmd_val(*pmd)); |
3c726f8d BH |
310 | } |
311 | ||
e5a1edb9 CL |
312 | /* |
313 | * This is called at the end of handling a user page fault, when the | |
314 | * fault has been handled by updating a PTE in the linux page tables. | |
315 | * We use it to preload an HPTE into the hash table corresponding to | |
316 | * the updated linux PTE. | |
317 | * | |
318 | * This must always be called with the pte lock held. | |
319 | */ | |
73ea68ad | 320 | void __update_mmu_cache(struct vm_area_struct *vma, unsigned long address, |
e5a1edb9 CL |
321 | pte_t *ptep) |
322 | { | |
323 | /* | |
324 | * We don't need to worry about _PAGE_PRESENT here because we are | |
325 | * called with either mm->page_table_lock held or ptl lock held | |
326 | */ | |
e5a1edb9 CL |
327 | |
328 | /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ | |
329 | if (!pte_young(*ptep) || address >= TASK_SIZE) | |
330 | return; | |
331 | ||
f49f4e2b CL |
332 | /* We have to test for regs NULL since init will get here first thing at boot */ |
333 | if (!current->thread.regs) | |
334 | return; | |
e5a1edb9 | 335 | |
f49f4e2b CL |
336 | /* We also avoid filling the hash if not coming from a fault */ |
337 | if (TRAP(current->thread.regs) != 0x300 && TRAP(current->thread.regs) != 0x400) | |
e5a1edb9 | 338 | return; |
e5a1edb9 | 339 | |
f49f4e2b | 340 | hash_preload(vma->vm_mm, address); |
e5a1edb9 CL |
341 | } |
342 | ||
14cf11af PM |
343 | /* |
344 | * Initialize the hash table and patch the instructions in hashtable.S. | |
345 | */ | |
346 | void __init MMU_init_hw(void) | |
347 | { | |
14cf11af PM |
348 | unsigned int n_hpteg, lg_n_hpteg; |
349 | ||
4a3a224c | 350 | if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) |
14cf11af | 351 | return; |
14cf11af PM |
352 | |
353 | if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105); | |
354 | ||
14cf11af PM |
355 | #define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */ |
356 | #define SDR1_LOW_BITS ((n_hpteg - 1) >> 10) | |
357 | #define MIN_N_HPTEG 1024 /* min 64kB hash table */ | |
14cf11af | 358 | |
14cf11af PM |
359 | /* |
360 | * Allow 1 HPTE (1/8 HPTEG) for each page of memory. | |
361 | * This is less than the recommended amount, but then | |
362 | * Linux ain't AIX. | |
363 | */ | |
364 | n_hpteg = total_memory / (PAGE_SIZE * 8); | |
365 | if (n_hpteg < MIN_N_HPTEG) | |
366 | n_hpteg = MIN_N_HPTEG; | |
367 | lg_n_hpteg = __ilog2(n_hpteg); | |
368 | if (n_hpteg & (n_hpteg - 1)) { | |
369 | ++lg_n_hpteg; /* round up if not power of 2 */ | |
370 | n_hpteg = 1 << lg_n_hpteg; | |
371 | } | |
372 | Hash_size = n_hpteg << LG_HPTEG_SIZE; | |
373 | ||
374 | /* | |
375 | * Find some memory for the hash table. | |
376 | */ | |
377 | if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322); | |
b63a07d6 | 378 | Hash = memblock_alloc(Hash_size, Hash_size); |
8a7f97b9 MR |
379 | if (!Hash) |
380 | panic("%s: Failed to allocate %lu bytes align=0x%lx\n", | |
381 | __func__, Hash_size, Hash_size); | |
14cf11af | 382 | _SDR1 = __pa(Hash) | SDR1_LOW_BITS; |
14cf11af | 383 | |
8f156c23 CL |
384 | pr_info("Total memory = %lldMB; using %ldkB for hash table\n", |
385 | (unsigned long long)(total_memory >> 20), Hash_size >> 10); | |
14cf11af | 386 | |
14cf11af | 387 | |
14cf11af | 388 | Hash_mask = n_hpteg - 1; |
72f208c6 | 389 | hash_mb2 = hash_mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg; |
14cf11af | 390 | if (lg_n_hpteg > 16) |
72f208c6 CL |
391 | hash_mb2 = 16 - LG_HPTEG_SIZE; |
392 | } | |
393 | ||
394 | void __init MMU_init_hw_patch(void) | |
395 | { | |
396 | unsigned int hmask = Hash_mask >> (16 - LG_HPTEG_SIZE); | |
232ca1ee | 397 | unsigned int hash = (unsigned int)Hash - PAGE_OFFSET; |
14cf11af | 398 | |
69a1593a CL |
399 | if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) |
400 | return; | |
401 | ||
72f208c6 CL |
402 | if (ppc_md.progress) |
403 | ppc_md.progress("hash:patch", 0x345); | |
404 | if (ppc_md.progress) | |
405 | ppc_md.progress("hash:done", 0x205); | |
406 | ||
407 | /* WARNING: Make sure nothing can trigger a KASAN check past this point */ | |
14cf11af PM |
408 | |
409 | /* | |
410 | * Patch up the instructions in hashtable.S:create_hpte | |
411 | */ | |
cd08f109 | 412 | modify_instruction_site(&patch__hash_page_A0, 0xffff, hash >> 16); |
72f208c6 CL |
413 | modify_instruction_site(&patch__hash_page_A1, 0x7c0, hash_mb << 6); |
414 | modify_instruction_site(&patch__hash_page_A2, 0x7c0, hash_mb2 << 6); | |
9efc74ff CL |
415 | modify_instruction_site(&patch__hash_page_B, 0xffff, hmask); |
416 | modify_instruction_site(&patch__hash_page_C, 0xffff, hmask); | |
14cf11af PM |
417 | |
418 | /* | |
419 | * Patch up the instructions in hashtable.S:flush_hash_page | |
420 | */ | |
232ca1ee | 421 | modify_instruction_site(&patch__flush_hash_A0, 0xffff, hash >> 16); |
72f208c6 CL |
422 | modify_instruction_site(&patch__flush_hash_A1, 0x7c0, hash_mb << 6); |
423 | modify_instruction_site(&patch__flush_hash_A2, 0x7c0, hash_mb2 << 6); | |
9efc74ff | 424 | modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask); |
14cf11af | 425 | } |
cd3db0c4 BH |
426 | |
427 | void setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
428 | phys_addr_t first_memblock_size) | |
429 | { | |
430 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
431 | * physical on those processors | |
432 | */ | |
433 | BUG_ON(first_memblock_base != 0); | |
434 | ||
8b14e1df | 435 | memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_256M)); |
cd3db0c4 | 436 | } |
31ed2b13 | 437 | |
e4dccf90 CL |
438 | void __init print_system_hash_info(void) |
439 | { | |
440 | pr_info("Hash_size = 0x%lx\n", Hash_size); | |
441 | if (Hash_mask) | |
442 | pr_info("Hash_mask = 0x%lx\n", Hash_mask); | |
443 | } | |
444 | ||
068fdba1 CL |
445 | void __init early_init_mmu(void) |
446 | { | |
447 | } |