Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * Single-step support. | |
3 | * | |
4 | * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
0d69a052 | 12 | #include <linux/kprobes.h> |
14cf11af | 13 | #include <linux/ptrace.h> |
268bb0ce | 14 | #include <linux/prefetch.h> |
14cf11af PM |
15 | #include <asm/sstep.h> |
16 | #include <asm/processor.h> | |
7c0f6ba6 | 17 | #include <linux/uaccess.h> |
5e9d0e3d | 18 | #include <asm/cpu_has_feature.h> |
0016a4cf | 19 | #include <asm/cputable.h> |
14cf11af PM |
20 | |
21 | extern char system_call_common[]; | |
22 | ||
c032524f | 23 | #ifdef CONFIG_PPC64 |
14cf11af | 24 | /* Bits in SRR1 that are copied from MSR */ |
af308377 | 25 | #define MSR_MASK 0xffffffff87c0ffffUL |
c032524f PM |
26 | #else |
27 | #define MSR_MASK 0x87c0ffff | |
28 | #endif | |
14cf11af | 29 | |
0016a4cf PM |
30 | /* Bits in XER */ |
31 | #define XER_SO 0x80000000U | |
32 | #define XER_OV 0x40000000U | |
33 | #define XER_CA 0x20000000U | |
34 | ||
cd64d169 | 35 | #ifdef CONFIG_PPC_FPU |
0016a4cf PM |
36 | /* |
37 | * Functions in ldstfp.S | |
38 | */ | |
39 | extern int do_lfs(int rn, unsigned long ea); | |
40 | extern int do_lfd(int rn, unsigned long ea); | |
41 | extern int do_stfs(int rn, unsigned long ea); | |
42 | extern int do_stfd(int rn, unsigned long ea); | |
43 | extern int do_lvx(int rn, unsigned long ea); | |
44 | extern int do_stvx(int rn, unsigned long ea); | |
350779a2 PM |
45 | extern void load_vsrn(int vsr, const void *p); |
46 | extern void store_vsrn(int vsr, void *p); | |
47 | extern void conv_sp_to_dp(const float *sp, double *dp); | |
48 | extern void conv_dp_to_sp(const double *dp, float *sp); | |
49 | #endif | |
50 | ||
51 | #ifdef __powerpc64__ | |
52 | /* | |
53 | * Functions in quad.S | |
54 | */ | |
55 | extern int do_lq(unsigned long ea, unsigned long *regs); | |
56 | extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1); | |
57 | extern int do_lqarx(unsigned long ea, unsigned long *regs); | |
58 | extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1, | |
59 | unsigned int *crp); | |
60 | #endif | |
61 | ||
62 | #ifdef __LITTLE_ENDIAN__ | |
63 | #define IS_LE 1 | |
64 | #define IS_BE 0 | |
65 | #else | |
66 | #define IS_LE 0 | |
67 | #define IS_BE 1 | |
cd64d169 | 68 | #endif |
0016a4cf | 69 | |
b91e136c ME |
70 | /* |
71 | * Emulate the truncation of 64 bit values in 32-bit mode. | |
72 | */ | |
71f6e58e NR |
73 | static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr, |
74 | unsigned long val) | |
b91e136c ME |
75 | { |
76 | #ifdef __powerpc64__ | |
77 | if ((msr & MSR_64BIT) == 0) | |
78 | val &= 0xffffffffUL; | |
79 | #endif | |
80 | return val; | |
81 | } | |
82 | ||
14cf11af PM |
83 | /* |
84 | * Determine whether a conditional branch instruction would branch. | |
85 | */ | |
3cdfcbfd PM |
86 | static nokprobe_inline int branch_taken(unsigned int instr, |
87 | const struct pt_regs *regs, | |
88 | struct instruction_op *op) | |
14cf11af PM |
89 | { |
90 | unsigned int bo = (instr >> 21) & 0x1f; | |
91 | unsigned int bi; | |
92 | ||
93 | if ((bo & 4) == 0) { | |
94 | /* decrement counter */ | |
3cdfcbfd PM |
95 | op->type |= DECCTR; |
96 | if (((bo >> 1) & 1) ^ (regs->ctr == 1)) | |
14cf11af PM |
97 | return 0; |
98 | } | |
99 | if ((bo & 0x10) == 0) { | |
100 | /* check bit from CR */ | |
101 | bi = (instr >> 16) & 0x1f; | |
102 | if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) | |
103 | return 0; | |
104 | } | |
105 | return 1; | |
106 | } | |
107 | ||
71f6e58e | 108 | static nokprobe_inline long address_ok(struct pt_regs *regs, unsigned long ea, int nb) |
0016a4cf PM |
109 | { |
110 | if (!user_mode(regs)) | |
111 | return 1; | |
112 | return __access_ok(ea, nb, USER_DS); | |
113 | } | |
114 | ||
115 | /* | |
116 | * Calculate effective address for a D-form instruction | |
117 | */ | |
3cdfcbfd PM |
118 | static nokprobe_inline unsigned long dform_ea(unsigned int instr, |
119 | const struct pt_regs *regs) | |
0016a4cf PM |
120 | { |
121 | int ra; | |
122 | unsigned long ea; | |
123 | ||
124 | ra = (instr >> 16) & 0x1f; | |
125 | ea = (signed short) instr; /* sign-extend */ | |
be96f633 | 126 | if (ra) |
0016a4cf | 127 | ea += regs->gpr[ra]; |
b91e136c | 128 | |
d120cdbc | 129 | return ea; |
0016a4cf PM |
130 | } |
131 | ||
132 | #ifdef __powerpc64__ | |
133 | /* | |
134 | * Calculate effective address for a DS-form instruction | |
135 | */ | |
3cdfcbfd PM |
136 | static nokprobe_inline unsigned long dsform_ea(unsigned int instr, |
137 | const struct pt_regs *regs) | |
0016a4cf PM |
138 | { |
139 | int ra; | |
140 | unsigned long ea; | |
141 | ||
142 | ra = (instr >> 16) & 0x1f; | |
143 | ea = (signed short) (instr & ~3); /* sign-extend */ | |
be96f633 | 144 | if (ra) |
0016a4cf | 145 | ea += regs->gpr[ra]; |
b91e136c | 146 | |
d120cdbc | 147 | return ea; |
0016a4cf | 148 | } |
350779a2 PM |
149 | |
150 | /* | |
151 | * Calculate effective address for a DQ-form instruction | |
152 | */ | |
153 | static nokprobe_inline unsigned long dqform_ea(unsigned int instr, | |
154 | const struct pt_regs *regs) | |
155 | { | |
156 | int ra; | |
157 | unsigned long ea; | |
158 | ||
159 | ra = (instr >> 16) & 0x1f; | |
160 | ea = (signed short) (instr & ~0xf); /* sign-extend */ | |
161 | if (ra) | |
162 | ea += regs->gpr[ra]; | |
163 | ||
d120cdbc | 164 | return ea; |
350779a2 | 165 | } |
0016a4cf PM |
166 | #endif /* __powerpc64 */ |
167 | ||
168 | /* | |
169 | * Calculate effective address for an X-form instruction | |
170 | */ | |
71f6e58e | 171 | static nokprobe_inline unsigned long xform_ea(unsigned int instr, |
3cdfcbfd | 172 | const struct pt_regs *regs) |
0016a4cf PM |
173 | { |
174 | int ra, rb; | |
175 | unsigned long ea; | |
176 | ||
177 | ra = (instr >> 16) & 0x1f; | |
178 | rb = (instr >> 11) & 0x1f; | |
179 | ea = regs->gpr[rb]; | |
be96f633 | 180 | if (ra) |
0016a4cf | 181 | ea += regs->gpr[ra]; |
b91e136c | 182 | |
d120cdbc | 183 | return ea; |
0016a4cf PM |
184 | } |
185 | ||
186 | /* | |
187 | * Return the largest power of 2, not greater than sizeof(unsigned long), | |
188 | * such that x is a multiple of it. | |
189 | */ | |
71f6e58e | 190 | static nokprobe_inline unsigned long max_align(unsigned long x) |
0016a4cf PM |
191 | { |
192 | x |= sizeof(unsigned long); | |
193 | return x & -x; /* isolates rightmost bit */ | |
194 | } | |
195 | ||
71f6e58e | 196 | static nokprobe_inline unsigned long byterev_2(unsigned long x) |
0016a4cf PM |
197 | { |
198 | return ((x >> 8) & 0xff) | ((x & 0xff) << 8); | |
199 | } | |
200 | ||
71f6e58e | 201 | static nokprobe_inline unsigned long byterev_4(unsigned long x) |
0016a4cf PM |
202 | { |
203 | return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) | | |
204 | ((x & 0xff00) << 8) | ((x & 0xff) << 24); | |
205 | } | |
206 | ||
207 | #ifdef __powerpc64__ | |
71f6e58e | 208 | static nokprobe_inline unsigned long byterev_8(unsigned long x) |
0016a4cf PM |
209 | { |
210 | return (byterev_4(x) << 32) | byterev_4(x >> 32); | |
211 | } | |
212 | #endif | |
213 | ||
71f6e58e NR |
214 | static nokprobe_inline int read_mem_aligned(unsigned long *dest, |
215 | unsigned long ea, int nb) | |
0016a4cf PM |
216 | { |
217 | int err = 0; | |
218 | unsigned long x = 0; | |
219 | ||
220 | switch (nb) { | |
221 | case 1: | |
222 | err = __get_user(x, (unsigned char __user *) ea); | |
223 | break; | |
224 | case 2: | |
225 | err = __get_user(x, (unsigned short __user *) ea); | |
226 | break; | |
227 | case 4: | |
228 | err = __get_user(x, (unsigned int __user *) ea); | |
229 | break; | |
230 | #ifdef __powerpc64__ | |
231 | case 8: | |
232 | err = __get_user(x, (unsigned long __user *) ea); | |
233 | break; | |
234 | #endif | |
235 | } | |
236 | if (!err) | |
237 | *dest = x; | |
238 | return err; | |
239 | } | |
240 | ||
e0a0986b PM |
241 | /* |
242 | * Copy from userspace to a buffer, using the largest possible | |
243 | * aligned accesses, up to sizeof(long). | |
244 | */ | |
245 | static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb) | |
0016a4cf | 246 | { |
e0a0986b PM |
247 | int err = 0; |
248 | int c; | |
0016a4cf | 249 | |
0016a4cf PM |
250 | for (; nb > 0; nb -= c) { |
251 | c = max_align(ea); | |
252 | if (c > nb) | |
253 | c = max_align(nb); | |
e0a0986b PM |
254 | switch (c) { |
255 | case 1: | |
256 | err = __get_user(*dest, (unsigned char __user *) ea); | |
257 | break; | |
258 | case 2: | |
259 | err = __get_user(*(u16 *)dest, | |
260 | (unsigned short __user *) ea); | |
261 | break; | |
262 | case 4: | |
263 | err = __get_user(*(u32 *)dest, | |
264 | (unsigned int __user *) ea); | |
265 | break; | |
266 | #ifdef __powerpc64__ | |
267 | case 8: | |
268 | err = __get_user(*(unsigned long *)dest, | |
269 | (unsigned long __user *) ea); | |
270 | break; | |
271 | #endif | |
272 | } | |
0016a4cf PM |
273 | if (err) |
274 | return err; | |
e0a0986b | 275 | dest += c; |
0016a4cf PM |
276 | ea += c; |
277 | } | |
0016a4cf PM |
278 | return 0; |
279 | } | |
280 | ||
e0a0986b PM |
281 | static nokprobe_inline int read_mem_unaligned(unsigned long *dest, |
282 | unsigned long ea, int nb, | |
283 | struct pt_regs *regs) | |
284 | { | |
285 | union { | |
286 | unsigned long ul; | |
287 | u8 b[sizeof(unsigned long)]; | |
288 | } u; | |
289 | int i; | |
290 | int err; | |
291 | ||
292 | u.ul = 0; | |
293 | i = IS_BE ? sizeof(unsigned long) - nb : 0; | |
294 | err = copy_mem_in(&u.b[i], ea, nb); | |
295 | if (!err) | |
296 | *dest = u.ul; | |
297 | return err; | |
298 | } | |
299 | ||
0016a4cf PM |
300 | /* |
301 | * Read memory at address ea for nb bytes, return 0 for success | |
e0a0986b PM |
302 | * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. |
303 | * If nb < sizeof(long), the result is right-justified on BE systems. | |
0016a4cf | 304 | */ |
71f6e58e | 305 | static int read_mem(unsigned long *dest, unsigned long ea, int nb, |
0016a4cf PM |
306 | struct pt_regs *regs) |
307 | { | |
308 | if (!address_ok(regs, ea, nb)) | |
309 | return -EFAULT; | |
310 | if ((ea & (nb - 1)) == 0) | |
311 | return read_mem_aligned(dest, ea, nb); | |
312 | return read_mem_unaligned(dest, ea, nb, regs); | |
313 | } | |
71f6e58e | 314 | NOKPROBE_SYMBOL(read_mem); |
0016a4cf | 315 | |
71f6e58e NR |
316 | static nokprobe_inline int write_mem_aligned(unsigned long val, |
317 | unsigned long ea, int nb) | |
0016a4cf PM |
318 | { |
319 | int err = 0; | |
320 | ||
321 | switch (nb) { | |
322 | case 1: | |
323 | err = __put_user(val, (unsigned char __user *) ea); | |
324 | break; | |
325 | case 2: | |
326 | err = __put_user(val, (unsigned short __user *) ea); | |
327 | break; | |
328 | case 4: | |
329 | err = __put_user(val, (unsigned int __user *) ea); | |
330 | break; | |
331 | #ifdef __powerpc64__ | |
332 | case 8: | |
333 | err = __put_user(val, (unsigned long __user *) ea); | |
334 | break; | |
335 | #endif | |
336 | } | |
337 | return err; | |
338 | } | |
339 | ||
e0a0986b PM |
340 | /* |
341 | * Copy from a buffer to userspace, using the largest possible | |
342 | * aligned accesses, up to sizeof(long). | |
343 | */ | |
344 | static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb) | |
0016a4cf | 345 | { |
e0a0986b PM |
346 | int err = 0; |
347 | int c; | |
0016a4cf | 348 | |
0016a4cf PM |
349 | for (; nb > 0; nb -= c) { |
350 | c = max_align(ea); | |
351 | if (c > nb) | |
352 | c = max_align(nb); | |
e0a0986b PM |
353 | switch (c) { |
354 | case 1: | |
355 | err = __put_user(*dest, (unsigned char __user *) ea); | |
356 | break; | |
357 | case 2: | |
358 | err = __put_user(*(u16 *)dest, | |
359 | (unsigned short __user *) ea); | |
360 | break; | |
361 | case 4: | |
362 | err = __put_user(*(u32 *)dest, | |
363 | (unsigned int __user *) ea); | |
364 | break; | |
365 | #ifdef __powerpc64__ | |
366 | case 8: | |
367 | err = __put_user(*(unsigned long *)dest, | |
368 | (unsigned long __user *) ea); | |
369 | break; | |
370 | #endif | |
371 | } | |
0016a4cf PM |
372 | if (err) |
373 | return err; | |
e0a0986b | 374 | dest += c; |
17e8de7e | 375 | ea += c; |
0016a4cf PM |
376 | } |
377 | return 0; | |
378 | } | |
379 | ||
e0a0986b PM |
380 | static nokprobe_inline int write_mem_unaligned(unsigned long val, |
381 | unsigned long ea, int nb, | |
382 | struct pt_regs *regs) | |
383 | { | |
384 | union { | |
385 | unsigned long ul; | |
386 | u8 b[sizeof(unsigned long)]; | |
387 | } u; | |
388 | int i; | |
389 | ||
390 | u.ul = val; | |
391 | i = IS_BE ? sizeof(unsigned long) - nb : 0; | |
392 | return copy_mem_out(&u.b[i], ea, nb); | |
393 | } | |
394 | ||
0016a4cf PM |
395 | /* |
396 | * Write memory at address ea for nb bytes, return 0 for success | |
e0a0986b | 397 | * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8. |
0016a4cf | 398 | */ |
71f6e58e | 399 | static int write_mem(unsigned long val, unsigned long ea, int nb, |
0016a4cf PM |
400 | struct pt_regs *regs) |
401 | { | |
402 | if (!address_ok(regs, ea, nb)) | |
403 | return -EFAULT; | |
404 | if ((ea & (nb - 1)) == 0) | |
405 | return write_mem_aligned(val, ea, nb); | |
406 | return write_mem_unaligned(val, ea, nb, regs); | |
407 | } | |
71f6e58e | 408 | NOKPROBE_SYMBOL(write_mem); |
0016a4cf | 409 | |
cd64d169 | 410 | #ifdef CONFIG_PPC_FPU |
14cf11af | 411 | /* |
0016a4cf PM |
412 | * Check the address and alignment, and call func to do the actual |
413 | * load or store. | |
414 | */ | |
71f6e58e | 415 | static int do_fp_load(int rn, int (*func)(int, unsigned long), |
0016a4cf PM |
416 | unsigned long ea, int nb, |
417 | struct pt_regs *regs) | |
418 | { | |
419 | int err; | |
e0a0986b | 420 | u8 buf[sizeof(double)] __attribute__((aligned(sizeof(double)))); |
0016a4cf PM |
421 | |
422 | if (!address_ok(regs, ea, nb)) | |
423 | return -EFAULT; | |
e0a0986b PM |
424 | if (ea & 3) { |
425 | err = copy_mem_in(buf, ea, nb); | |
426 | if (err) | |
427 | return err; | |
428 | ea = (unsigned long) buf; | |
0016a4cf | 429 | } |
e0a0986b | 430 | return (*func)(rn, ea); |
0016a4cf | 431 | } |
71f6e58e | 432 | NOKPROBE_SYMBOL(do_fp_load); |
0016a4cf | 433 | |
71f6e58e | 434 | static int do_fp_store(int rn, int (*func)(int, unsigned long), |
0016a4cf PM |
435 | unsigned long ea, int nb, |
436 | struct pt_regs *regs) | |
437 | { | |
438 | int err; | |
e0a0986b | 439 | u8 buf[sizeof(double)] __attribute__((aligned(sizeof(double)))); |
0016a4cf PM |
440 | |
441 | if (!address_ok(regs, ea, nb)) | |
442 | return -EFAULT; | |
443 | if ((ea & 3) == 0) | |
444 | return (*func)(rn, ea); | |
e0a0986b PM |
445 | err = (*func)(rn, (unsigned long) buf); |
446 | if (!err) | |
447 | err = copy_mem_out(buf, ea, nb); | |
0016a4cf PM |
448 | return err; |
449 | } | |
71f6e58e | 450 | NOKPROBE_SYMBOL(do_fp_store); |
cd64d169 | 451 | #endif |
0016a4cf PM |
452 | |
453 | #ifdef CONFIG_ALTIVEC | |
454 | /* For Altivec/VMX, no need to worry about alignment */ | |
71f6e58e | 455 | static nokprobe_inline int do_vec_load(int rn, int (*func)(int, unsigned long), |
0016a4cf PM |
456 | unsigned long ea, struct pt_regs *regs) |
457 | { | |
458 | if (!address_ok(regs, ea & ~0xfUL, 16)) | |
459 | return -EFAULT; | |
460 | return (*func)(rn, ea); | |
461 | } | |
462 | ||
71f6e58e | 463 | static nokprobe_inline int do_vec_store(int rn, int (*func)(int, unsigned long), |
0016a4cf PM |
464 | unsigned long ea, struct pt_regs *regs) |
465 | { | |
466 | if (!address_ok(regs, ea & ~0xfUL, 16)) | |
467 | return -EFAULT; | |
468 | return (*func)(rn, ea); | |
469 | } | |
470 | #endif /* CONFIG_ALTIVEC */ | |
471 | ||
350779a2 PM |
472 | #ifdef __powerpc64__ |
473 | static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea, | |
474 | int reg) | |
0016a4cf PM |
475 | { |
476 | int err; | |
0016a4cf PM |
477 | |
478 | if (!address_ok(regs, ea, 16)) | |
479 | return -EFAULT; | |
350779a2 PM |
480 | /* if aligned, should be atomic */ |
481 | if ((ea & 0xf) == 0) | |
482 | return do_lq(ea, ®s->gpr[reg]); | |
483 | ||
484 | err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); | |
0016a4cf | 485 | if (!err) |
350779a2 | 486 | err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); |
0016a4cf PM |
487 | return err; |
488 | } | |
489 | ||
350779a2 PM |
490 | static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea, |
491 | int reg) | |
0016a4cf PM |
492 | { |
493 | int err; | |
0016a4cf PM |
494 | |
495 | if (!address_ok(regs, ea, 16)) | |
496 | return -EFAULT; | |
350779a2 PM |
497 | /* if aligned, should be atomic */ |
498 | if ((ea & 0xf) == 0) | |
499 | return do_stq(ea, regs->gpr[reg], regs->gpr[reg + 1]); | |
500 | ||
501 | err = write_mem(regs->gpr[reg + IS_LE], ea, 8, regs); | |
0016a4cf | 502 | if (!err) |
350779a2 | 503 | err = write_mem(regs->gpr[reg + IS_BE], ea + 8, 8, regs); |
0016a4cf PM |
504 | return err; |
505 | } | |
350779a2 PM |
506 | #endif /* __powerpc64 */ |
507 | ||
508 | #ifdef CONFIG_VSX | |
509 | void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, | |
510 | const void *mem) | |
511 | { | |
512 | int size, read_size; | |
513 | int i, j; | |
514 | const unsigned int *wp; | |
515 | const unsigned short *hp; | |
516 | const unsigned char *bp; | |
517 | ||
518 | size = GETSIZE(op->type); | |
519 | reg->d[0] = reg->d[1] = 0; | |
520 | ||
521 | switch (op->element_size) { | |
522 | case 16: | |
523 | /* whole vector; lxv[x] or lxvl[l] */ | |
524 | if (size == 0) | |
525 | break; | |
526 | memcpy(reg, mem, size); | |
527 | if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) { | |
528 | /* reverse 16 bytes */ | |
529 | unsigned long tmp; | |
530 | tmp = byterev_8(reg->d[0]); | |
531 | reg->d[0] = byterev_8(reg->d[1]); | |
532 | reg->d[1] = tmp; | |
533 | } | |
534 | break; | |
535 | case 8: | |
536 | /* scalar loads, lxvd2x, lxvdsx */ | |
537 | read_size = (size >= 8) ? 8 : size; | |
538 | i = IS_LE ? 8 : 8 - read_size; | |
539 | memcpy(®->b[i], mem, read_size); | |
540 | if (size < 8) { | |
541 | if (op->type & SIGNEXT) { | |
542 | /* size == 4 is the only case here */ | |
543 | reg->d[IS_LE] = (signed int) reg->d[IS_LE]; | |
544 | } else if (op->vsx_flags & VSX_FPCONV) { | |
545 | preempt_disable(); | |
546 | conv_sp_to_dp(®->fp[1 + IS_LE], | |
547 | ®->dp[IS_LE]); | |
548 | preempt_enable(); | |
549 | } | |
550 | } else { | |
551 | if (size == 16) | |
552 | reg->d[IS_BE] = *(unsigned long *)(mem + 8); | |
553 | else if (op->vsx_flags & VSX_SPLAT) | |
554 | reg->d[IS_BE] = reg->d[IS_LE]; | |
555 | } | |
556 | break; | |
557 | case 4: | |
558 | /* lxvw4x, lxvwsx */ | |
559 | wp = mem; | |
560 | for (j = 0; j < size / 4; ++j) { | |
561 | i = IS_LE ? 3 - j : j; | |
562 | reg->w[i] = *wp++; | |
563 | } | |
564 | if (op->vsx_flags & VSX_SPLAT) { | |
565 | u32 val = reg->w[IS_LE ? 3 : 0]; | |
566 | for (; j < 4; ++j) { | |
567 | i = IS_LE ? 3 - j : j; | |
568 | reg->w[i] = val; | |
569 | } | |
570 | } | |
571 | break; | |
572 | case 2: | |
573 | /* lxvh8x */ | |
574 | hp = mem; | |
575 | for (j = 0; j < size / 2; ++j) { | |
576 | i = IS_LE ? 7 - j : j; | |
577 | reg->h[i] = *hp++; | |
578 | } | |
579 | break; | |
580 | case 1: | |
581 | /* lxvb16x */ | |
582 | bp = mem; | |
583 | for (j = 0; j < size; ++j) { | |
584 | i = IS_LE ? 15 - j : j; | |
585 | reg->b[i] = *bp++; | |
586 | } | |
587 | break; | |
588 | } | |
589 | } | |
590 | EXPORT_SYMBOL_GPL(emulate_vsx_load); | |
591 | NOKPROBE_SYMBOL(emulate_vsx_load); | |
592 | ||
593 | void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, | |
594 | void *mem) | |
595 | { | |
596 | int size, write_size; | |
597 | int i, j; | |
598 | union vsx_reg buf; | |
599 | unsigned int *wp; | |
600 | unsigned short *hp; | |
601 | unsigned char *bp; | |
602 | ||
603 | size = GETSIZE(op->type); | |
604 | ||
605 | switch (op->element_size) { | |
606 | case 16: | |
607 | /* stxv, stxvx, stxvl, stxvll */ | |
608 | if (size == 0) | |
609 | break; | |
610 | if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) { | |
611 | /* reverse 16 bytes */ | |
612 | buf.d[0] = byterev_8(reg->d[1]); | |
613 | buf.d[1] = byterev_8(reg->d[0]); | |
614 | reg = &buf; | |
615 | } | |
616 | memcpy(mem, reg, size); | |
617 | break; | |
618 | case 8: | |
619 | /* scalar stores, stxvd2x */ | |
620 | write_size = (size >= 8) ? 8 : size; | |
621 | i = IS_LE ? 8 : 8 - write_size; | |
622 | if (size < 8 && op->vsx_flags & VSX_FPCONV) { | |
623 | buf.d[0] = buf.d[1] = 0; | |
624 | preempt_disable(); | |
625 | conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); | |
626 | preempt_enable(); | |
627 | reg = &buf; | |
628 | } | |
629 | memcpy(mem, ®->b[i], write_size); | |
630 | if (size == 16) | |
631 | memcpy(mem + 8, ®->d[IS_BE], 8); | |
632 | break; | |
633 | case 4: | |
634 | /* stxvw4x */ | |
635 | wp = mem; | |
636 | for (j = 0; j < size / 4; ++j) { | |
637 | i = IS_LE ? 3 - j : j; | |
638 | *wp++ = reg->w[i]; | |
639 | } | |
640 | break; | |
641 | case 2: | |
642 | /* stxvh8x */ | |
643 | hp = mem; | |
644 | for (j = 0; j < size / 2; ++j) { | |
645 | i = IS_LE ? 7 - j : j; | |
646 | *hp++ = reg->h[i]; | |
647 | } | |
648 | break; | |
649 | case 1: | |
650 | /* stvxb16x */ | |
651 | bp = mem; | |
652 | for (j = 0; j < size; ++j) { | |
653 | i = IS_LE ? 15 - j : j; | |
654 | *bp++ = reg->b[i]; | |
655 | } | |
656 | break; | |
657 | } | |
658 | } | |
659 | EXPORT_SYMBOL_GPL(emulate_vsx_store); | |
660 | NOKPROBE_SYMBOL(emulate_vsx_store); | |
0016a4cf PM |
661 | #endif /* CONFIG_VSX */ |
662 | ||
663 | #define __put_user_asmx(x, addr, err, op, cr) \ | |
664 | __asm__ __volatile__( \ | |
665 | "1: " op " %2,0,%3\n" \ | |
666 | " mfcr %1\n" \ | |
667 | "2:\n" \ | |
668 | ".section .fixup,\"ax\"\n" \ | |
669 | "3: li %0,%4\n" \ | |
670 | " b 2b\n" \ | |
671 | ".previous\n" \ | |
24bfa6a9 | 672 | EX_TABLE(1b, 3b) \ |
0016a4cf PM |
673 | : "=r" (err), "=r" (cr) \ |
674 | : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) | |
675 | ||
676 | #define __get_user_asmx(x, addr, err, op) \ | |
677 | __asm__ __volatile__( \ | |
678 | "1: "op" %1,0,%2\n" \ | |
679 | "2:\n" \ | |
680 | ".section .fixup,\"ax\"\n" \ | |
681 | "3: li %0,%3\n" \ | |
682 | " b 2b\n" \ | |
683 | ".previous\n" \ | |
24bfa6a9 | 684 | EX_TABLE(1b, 3b) \ |
0016a4cf PM |
685 | : "=r" (err), "=r" (x) \ |
686 | : "r" (addr), "i" (-EFAULT), "0" (err)) | |
687 | ||
688 | #define __cacheop_user_asmx(addr, err, op) \ | |
689 | __asm__ __volatile__( \ | |
690 | "1: "op" 0,%1\n" \ | |
691 | "2:\n" \ | |
692 | ".section .fixup,\"ax\"\n" \ | |
693 | "3: li %0,%3\n" \ | |
694 | " b 2b\n" \ | |
695 | ".previous\n" \ | |
24bfa6a9 | 696 | EX_TABLE(1b, 3b) \ |
0016a4cf PM |
697 | : "=r" (err) \ |
698 | : "r" (addr), "i" (-EFAULT), "0" (err)) | |
699 | ||
3cdfcbfd PM |
700 | static nokprobe_inline void set_cr0(const struct pt_regs *regs, |
701 | struct instruction_op *op, int rd) | |
0016a4cf PM |
702 | { |
703 | long val = regs->gpr[rd]; | |
704 | ||
3cdfcbfd PM |
705 | op->type |= SETCC; |
706 | op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); | |
0016a4cf | 707 | #ifdef __powerpc64__ |
b91e136c | 708 | if (!(regs->msr & MSR_64BIT)) |
0016a4cf PM |
709 | val = (int) val; |
710 | #endif | |
711 | if (val < 0) | |
3cdfcbfd | 712 | op->ccval |= 0x80000000; |
0016a4cf | 713 | else if (val > 0) |
3cdfcbfd | 714 | op->ccval |= 0x40000000; |
0016a4cf | 715 | else |
3cdfcbfd | 716 | op->ccval |= 0x20000000; |
0016a4cf PM |
717 | } |
718 | ||
3cdfcbfd PM |
719 | static nokprobe_inline void add_with_carry(const struct pt_regs *regs, |
720 | struct instruction_op *op, int rd, | |
0016a4cf PM |
721 | unsigned long val1, unsigned long val2, |
722 | unsigned long carry_in) | |
723 | { | |
724 | unsigned long val = val1 + val2; | |
725 | ||
726 | if (carry_in) | |
727 | ++val; | |
3cdfcbfd PM |
728 | op->type = COMPUTE + SETREG + SETXER; |
729 | op->reg = rd; | |
730 | op->val = val; | |
0016a4cf | 731 | #ifdef __powerpc64__ |
b91e136c | 732 | if (!(regs->msr & MSR_64BIT)) { |
0016a4cf PM |
733 | val = (unsigned int) val; |
734 | val1 = (unsigned int) val1; | |
735 | } | |
736 | #endif | |
3cdfcbfd | 737 | op->xerval = regs->xer; |
0016a4cf | 738 | if (val < val1 || (carry_in && val == val1)) |
3cdfcbfd | 739 | op->xerval |= XER_CA; |
0016a4cf | 740 | else |
3cdfcbfd | 741 | op->xerval &= ~XER_CA; |
0016a4cf PM |
742 | } |
743 | ||
3cdfcbfd PM |
744 | static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs, |
745 | struct instruction_op *op, | |
746 | long v1, long v2, int crfld) | |
0016a4cf PM |
747 | { |
748 | unsigned int crval, shift; | |
749 | ||
3cdfcbfd | 750 | op->type = COMPUTE + SETCC; |
0016a4cf PM |
751 | crval = (regs->xer >> 31) & 1; /* get SO bit */ |
752 | if (v1 < v2) | |
753 | crval |= 8; | |
754 | else if (v1 > v2) | |
755 | crval |= 4; | |
756 | else | |
757 | crval |= 2; | |
758 | shift = (7 - crfld) * 4; | |
3cdfcbfd | 759 | op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); |
0016a4cf PM |
760 | } |
761 | ||
3cdfcbfd PM |
762 | static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs, |
763 | struct instruction_op *op, | |
764 | unsigned long v1, | |
765 | unsigned long v2, int crfld) | |
0016a4cf PM |
766 | { |
767 | unsigned int crval, shift; | |
768 | ||
3cdfcbfd | 769 | op->type = COMPUTE + SETCC; |
0016a4cf PM |
770 | crval = (regs->xer >> 31) & 1; /* get SO bit */ |
771 | if (v1 < v2) | |
772 | crval |= 8; | |
773 | else if (v1 > v2) | |
774 | crval |= 4; | |
775 | else | |
776 | crval |= 2; | |
777 | shift = (7 - crfld) * 4; | |
3cdfcbfd | 778 | op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); |
0016a4cf PM |
779 | } |
780 | ||
3cdfcbfd PM |
781 | static nokprobe_inline void do_cmpb(const struct pt_regs *regs, |
782 | struct instruction_op *op, | |
783 | unsigned long v1, unsigned long v2) | |
02c0f62a MB |
784 | { |
785 | unsigned long long out_val, mask; | |
786 | int i; | |
787 | ||
788 | out_val = 0; | |
789 | for (i = 0; i < 8; i++) { | |
790 | mask = 0xffUL << (i * 8); | |
791 | if ((v1 & mask) == (v2 & mask)) | |
792 | out_val |= mask; | |
793 | } | |
3cdfcbfd | 794 | op->val = out_val; |
02c0f62a MB |
795 | } |
796 | ||
dcbd19b4 MB |
797 | /* |
798 | * The size parameter is used to adjust the equivalent popcnt instruction. | |
799 | * popcntb = 8, popcntw = 32, popcntd = 64 | |
800 | */ | |
3cdfcbfd PM |
801 | static nokprobe_inline void do_popcnt(const struct pt_regs *regs, |
802 | struct instruction_op *op, | |
803 | unsigned long v1, int size) | |
dcbd19b4 MB |
804 | { |
805 | unsigned long long out = v1; | |
806 | ||
807 | out -= (out >> 1) & 0x5555555555555555; | |
808 | out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2)); | |
809 | out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f; | |
810 | ||
811 | if (size == 8) { /* popcntb */ | |
3cdfcbfd | 812 | op->val = out; |
dcbd19b4 MB |
813 | return; |
814 | } | |
815 | out += out >> 8; | |
816 | out += out >> 16; | |
817 | if (size == 32) { /* popcntw */ | |
3cdfcbfd | 818 | op->val = out & 0x0000003f0000003f; |
dcbd19b4 MB |
819 | return; |
820 | } | |
821 | ||
822 | out = (out + (out >> 32)) & 0x7f; | |
3cdfcbfd | 823 | op->val = out; /* popcntd */ |
dcbd19b4 MB |
824 | } |
825 | ||
f312793d | 826 | #ifdef CONFIG_PPC64 |
3cdfcbfd PM |
827 | static nokprobe_inline void do_bpermd(const struct pt_regs *regs, |
828 | struct instruction_op *op, | |
829 | unsigned long v1, unsigned long v2) | |
f312793d MB |
830 | { |
831 | unsigned char perm, idx; | |
832 | unsigned int i; | |
833 | ||
834 | perm = 0; | |
835 | for (i = 0; i < 8; i++) { | |
836 | idx = (v1 >> (i * 8)) & 0xff; | |
837 | if (idx < 64) | |
838 | if (v2 & PPC_BIT(idx)) | |
839 | perm |= 1 << i; | |
840 | } | |
3cdfcbfd | 841 | op->val = perm; |
f312793d MB |
842 | } |
843 | #endif /* CONFIG_PPC64 */ | |
2c979c48 MB |
844 | /* |
845 | * The size parameter adjusts the equivalent prty instruction. | |
846 | * prtyw = 32, prtyd = 64 | |
847 | */ | |
3cdfcbfd PM |
848 | static nokprobe_inline void do_prty(const struct pt_regs *regs, |
849 | struct instruction_op *op, | |
850 | unsigned long v, int size) | |
2c979c48 MB |
851 | { |
852 | unsigned long long res = v ^ (v >> 8); | |
853 | ||
854 | res ^= res >> 16; | |
855 | if (size == 32) { /* prtyw */ | |
3cdfcbfd | 856 | op->val = res & 0x0000000100000001; |
2c979c48 MB |
857 | return; |
858 | } | |
859 | ||
860 | res ^= res >> 32; | |
3cdfcbfd | 861 | op->val = res & 1; /*prtyd */ |
2c979c48 | 862 | } |
f312793d | 863 | |
71f6e58e | 864 | static nokprobe_inline int trap_compare(long v1, long v2) |
cf87c3f6 PM |
865 | { |
866 | int ret = 0; | |
867 | ||
868 | if (v1 < v2) | |
869 | ret |= 0x10; | |
870 | else if (v1 > v2) | |
871 | ret |= 0x08; | |
872 | else | |
873 | ret |= 0x04; | |
874 | if ((unsigned long)v1 < (unsigned long)v2) | |
875 | ret |= 0x02; | |
876 | else if ((unsigned long)v1 > (unsigned long)v2) | |
877 | ret |= 0x01; | |
878 | return ret; | |
879 | } | |
880 | ||
0016a4cf PM |
881 | /* |
882 | * Elements of 32-bit rotate and mask instructions. | |
883 | */ | |
884 | #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \ | |
885 | ((signed long)-0x80000000L >> (me)) + ((me) >= (mb))) | |
886 | #ifdef __powerpc64__ | |
887 | #define MASK64_L(mb) (~0UL >> (mb)) | |
888 | #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me)) | |
889 | #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb))) | |
890 | #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32)) | |
891 | #else | |
892 | #define DATA32(x) (x) | |
893 | #endif | |
894 | #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x)) | |
895 | ||
896 | /* | |
3cdfcbfd PM |
897 | * Decode an instruction, and return information about it in *op |
898 | * without changing *regs. | |
899 | * Integer arithmetic and logical instructions, branches, and barrier | |
900 | * instructions can be emulated just using the information in *op. | |
901 | * | |
902 | * Return value is 1 if the instruction can be emulated just by | |
903 | * updating *regs with the information in *op, -1 if we need the | |
904 | * GPRs but *regs doesn't contain the full register set, or 0 | |
905 | * otherwise. | |
14cf11af | 906 | */ |
3cdfcbfd PM |
907 | int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, |
908 | unsigned int instr) | |
14cf11af | 909 | { |
0016a4cf | 910 | unsigned int opcode, ra, rb, rd, spr, u; |
14cf11af | 911 | unsigned long int imm; |
0016a4cf | 912 | unsigned long int val, val2; |
be96f633 | 913 | unsigned int mb, me, sh; |
0016a4cf | 914 | long ival; |
14cf11af | 915 | |
be96f633 PM |
916 | op->type = COMPUTE; |
917 | ||
14cf11af PM |
918 | opcode = instr >> 26; |
919 | switch (opcode) { | |
920 | case 16: /* bc */ | |
be96f633 | 921 | op->type = BRANCH; |
14cf11af PM |
922 | imm = (signed short)(instr & 0xfffc); |
923 | if ((instr & 2) == 0) | |
924 | imm += regs->nip; | |
3cdfcbfd | 925 | op->val = truncate_if_32bit(regs->msr, imm); |
14cf11af | 926 | if (instr & 1) |
3cdfcbfd PM |
927 | op->type |= SETLK; |
928 | if (branch_taken(instr, regs, op)) | |
929 | op->type |= BRTAKEN; | |
14cf11af | 930 | return 1; |
c032524f | 931 | #ifdef CONFIG_PPC64 |
14cf11af | 932 | case 17: /* sc */ |
be96f633 PM |
933 | if ((instr & 0xfe2) == 2) |
934 | op->type = SYSCALL; | |
935 | else | |
936 | op->type = UNKNOWN; | |
937 | return 0; | |
c032524f | 938 | #endif |
14cf11af | 939 | case 18: /* b */ |
3cdfcbfd | 940 | op->type = BRANCH | BRTAKEN; |
14cf11af PM |
941 | imm = instr & 0x03fffffc; |
942 | if (imm & 0x02000000) | |
943 | imm -= 0x04000000; | |
944 | if ((instr & 2) == 0) | |
945 | imm += regs->nip; | |
3cdfcbfd | 946 | op->val = truncate_if_32bit(regs->msr, imm); |
b91e136c | 947 | if (instr & 1) |
3cdfcbfd | 948 | op->type |= SETLK; |
14cf11af PM |
949 | return 1; |
950 | case 19: | |
0016a4cf | 951 | switch ((instr >> 1) & 0x3ff) { |
cf87c3f6 | 952 | case 0: /* mcrf */ |
3cdfcbfd | 953 | op->type = COMPUTE + SETCC; |
87c4b83e AB |
954 | rd = 7 - ((instr >> 23) & 0x7); |
955 | ra = 7 - ((instr >> 18) & 0x7); | |
956 | rd *= 4; | |
957 | ra *= 4; | |
cf87c3f6 | 958 | val = (regs->ccr >> ra) & 0xf; |
3cdfcbfd PM |
959 | op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); |
960 | return 1; | |
cf87c3f6 | 961 | |
0016a4cf PM |
962 | case 16: /* bclr */ |
963 | case 528: /* bcctr */ | |
be96f633 | 964 | op->type = BRANCH; |
14cf11af | 965 | imm = (instr & 0x400)? regs->ctr: regs->link; |
3cdfcbfd | 966 | op->val = truncate_if_32bit(regs->msr, imm); |
14cf11af | 967 | if (instr & 1) |
3cdfcbfd PM |
968 | op->type |= SETLK; |
969 | if (branch_taken(instr, regs, op)) | |
970 | op->type |= BRTAKEN; | |
14cf11af | 971 | return 1; |
0016a4cf PM |
972 | |
973 | case 18: /* rfid, scary */ | |
be96f633 PM |
974 | if (regs->msr & MSR_PR) |
975 | goto priv; | |
976 | op->type = RFI; | |
977 | return 0; | |
0016a4cf PM |
978 | |
979 | case 150: /* isync */ | |
3cdfcbfd PM |
980 | op->type = BARRIER | BARRIER_ISYNC; |
981 | return 1; | |
0016a4cf PM |
982 | |
983 | case 33: /* crnor */ | |
984 | case 129: /* crandc */ | |
985 | case 193: /* crxor */ | |
986 | case 225: /* crnand */ | |
987 | case 257: /* crand */ | |
988 | case 289: /* creqv */ | |
989 | case 417: /* crorc */ | |
990 | case 449: /* cror */ | |
3cdfcbfd | 991 | op->type = COMPUTE + SETCC; |
0016a4cf PM |
992 | ra = (instr >> 16) & 0x1f; |
993 | rb = (instr >> 11) & 0x1f; | |
994 | rd = (instr >> 21) & 0x1f; | |
995 | ra = (regs->ccr >> (31 - ra)) & 1; | |
996 | rb = (regs->ccr >> (31 - rb)) & 1; | |
997 | val = (instr >> (6 + ra * 2 + rb)) & 1; | |
3cdfcbfd | 998 | op->ccval = (regs->ccr & ~(1UL << (31 - rd))) | |
0016a4cf | 999 | (val << (31 - rd)); |
3cdfcbfd | 1000 | return 1; |
0016a4cf PM |
1001 | } |
1002 | break; | |
1003 | case 31: | |
1004 | switch ((instr >> 1) & 0x3ff) { | |
1005 | case 598: /* sync */ | |
3cdfcbfd | 1006 | op->type = BARRIER + BARRIER_SYNC; |
0016a4cf PM |
1007 | #ifdef __powerpc64__ |
1008 | switch ((instr >> 21) & 3) { | |
1009 | case 1: /* lwsync */ | |
3cdfcbfd PM |
1010 | op->type = BARRIER + BARRIER_LWSYNC; |
1011 | break; | |
0016a4cf | 1012 | case 2: /* ptesync */ |
3cdfcbfd PM |
1013 | op->type = BARRIER + BARRIER_PTESYNC; |
1014 | break; | |
0016a4cf PM |
1015 | } |
1016 | #endif | |
3cdfcbfd | 1017 | return 1; |
0016a4cf PM |
1018 | |
1019 | case 854: /* eieio */ | |
3cdfcbfd PM |
1020 | op->type = BARRIER + BARRIER_EIEIO; |
1021 | return 1; | |
0016a4cf PM |
1022 | } |
1023 | break; | |
1024 | } | |
1025 | ||
1026 | /* Following cases refer to regs->gpr[], so we need all regs */ | |
1027 | if (!FULL_REGS(regs)) | |
3cdfcbfd | 1028 | return -1; |
0016a4cf PM |
1029 | |
1030 | rd = (instr >> 21) & 0x1f; | |
1031 | ra = (instr >> 16) & 0x1f; | |
1032 | rb = (instr >> 11) & 0x1f; | |
1033 | ||
1034 | switch (opcode) { | |
cf87c3f6 PM |
1035 | #ifdef __powerpc64__ |
1036 | case 2: /* tdi */ | |
1037 | if (rd & trap_compare(regs->gpr[ra], (short) instr)) | |
1038 | goto trap; | |
3cdfcbfd | 1039 | return 1; |
cf87c3f6 PM |
1040 | #endif |
1041 | case 3: /* twi */ | |
1042 | if (rd & trap_compare((int)regs->gpr[ra], (short) instr)) | |
1043 | goto trap; | |
3cdfcbfd | 1044 | return 1; |
cf87c3f6 | 1045 | |
0016a4cf | 1046 | case 7: /* mulli */ |
3cdfcbfd PM |
1047 | op->val = regs->gpr[ra] * (short) instr; |
1048 | goto compute_done; | |
0016a4cf PM |
1049 | |
1050 | case 8: /* subfic */ | |
1051 | imm = (short) instr; | |
3cdfcbfd PM |
1052 | add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1); |
1053 | return 1; | |
0016a4cf PM |
1054 | |
1055 | case 10: /* cmpli */ | |
1056 | imm = (unsigned short) instr; | |
1057 | val = regs->gpr[ra]; | |
1058 | #ifdef __powerpc64__ | |
1059 | if ((rd & 1) == 0) | |
1060 | val = (unsigned int) val; | |
1061 | #endif | |
3cdfcbfd PM |
1062 | do_cmp_unsigned(regs, op, val, imm, rd >> 2); |
1063 | return 1; | |
0016a4cf PM |
1064 | |
1065 | case 11: /* cmpi */ | |
1066 | imm = (short) instr; | |
1067 | val = regs->gpr[ra]; | |
1068 | #ifdef __powerpc64__ | |
1069 | if ((rd & 1) == 0) | |
1070 | val = (int) val; | |
1071 | #endif | |
3cdfcbfd PM |
1072 | do_cmp_signed(regs, op, val, imm, rd >> 2); |
1073 | return 1; | |
0016a4cf PM |
1074 | |
1075 | case 12: /* addic */ | |
1076 | imm = (short) instr; | |
3cdfcbfd PM |
1077 | add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); |
1078 | return 1; | |
0016a4cf PM |
1079 | |
1080 | case 13: /* addic. */ | |
1081 | imm = (short) instr; | |
3cdfcbfd PM |
1082 | add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); |
1083 | set_cr0(regs, op, rd); | |
1084 | return 1; | |
0016a4cf PM |
1085 | |
1086 | case 14: /* addi */ | |
1087 | imm = (short) instr; | |
1088 | if (ra) | |
1089 | imm += regs->gpr[ra]; | |
3cdfcbfd PM |
1090 | op->val = imm; |
1091 | goto compute_done; | |
0016a4cf PM |
1092 | |
1093 | case 15: /* addis */ | |
1094 | imm = ((short) instr) << 16; | |
1095 | if (ra) | |
1096 | imm += regs->gpr[ra]; | |
3cdfcbfd PM |
1097 | op->val = imm; |
1098 | goto compute_done; | |
0016a4cf | 1099 | |
958465ee PM |
1100 | case 19: |
1101 | if (((instr >> 1) & 0x1f) == 2) { | |
1102 | /* addpcis */ | |
1103 | imm = (short) (instr & 0xffc1); /* d0 + d2 fields */ | |
1104 | imm |= (instr >> 15) & 0x3e; /* d1 field */ | |
1105 | op->val = regs->nip + (imm << 16) + 4; | |
1106 | goto compute_done; | |
1107 | } | |
1108 | op->type = UNKNOWN; | |
1109 | return 0; | |
1110 | ||
0016a4cf PM |
1111 | case 20: /* rlwimi */ |
1112 | mb = (instr >> 6) & 0x1f; | |
1113 | me = (instr >> 1) & 0x1f; | |
1114 | val = DATA32(regs->gpr[rd]); | |
1115 | imm = MASK32(mb, me); | |
3cdfcbfd | 1116 | op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); |
0016a4cf PM |
1117 | goto logical_done; |
1118 | ||
1119 | case 21: /* rlwinm */ | |
1120 | mb = (instr >> 6) & 0x1f; | |
1121 | me = (instr >> 1) & 0x1f; | |
1122 | val = DATA32(regs->gpr[rd]); | |
3cdfcbfd | 1123 | op->val = ROTATE(val, rb) & MASK32(mb, me); |
0016a4cf PM |
1124 | goto logical_done; |
1125 | ||
1126 | case 23: /* rlwnm */ | |
1127 | mb = (instr >> 6) & 0x1f; | |
1128 | me = (instr >> 1) & 0x1f; | |
1129 | rb = regs->gpr[rb] & 0x1f; | |
1130 | val = DATA32(regs->gpr[rd]); | |
3cdfcbfd | 1131 | op->val = ROTATE(val, rb) & MASK32(mb, me); |
0016a4cf PM |
1132 | goto logical_done; |
1133 | ||
1134 | case 24: /* ori */ | |
3cdfcbfd PM |
1135 | op->val = regs->gpr[rd] | (unsigned short) instr; |
1136 | goto logical_done_nocc; | |
0016a4cf PM |
1137 | |
1138 | case 25: /* oris */ | |
1139 | imm = (unsigned short) instr; | |
3cdfcbfd PM |
1140 | op->val = regs->gpr[rd] | (imm << 16); |
1141 | goto logical_done_nocc; | |
0016a4cf PM |
1142 | |
1143 | case 26: /* xori */ | |
3cdfcbfd PM |
1144 | op->val = regs->gpr[rd] ^ (unsigned short) instr; |
1145 | goto logical_done_nocc; | |
0016a4cf PM |
1146 | |
1147 | case 27: /* xoris */ | |
1148 | imm = (unsigned short) instr; | |
3cdfcbfd PM |
1149 | op->val = regs->gpr[rd] ^ (imm << 16); |
1150 | goto logical_done_nocc; | |
0016a4cf PM |
1151 | |
1152 | case 28: /* andi. */ | |
3cdfcbfd PM |
1153 | op->val = regs->gpr[rd] & (unsigned short) instr; |
1154 | set_cr0(regs, op, ra); | |
1155 | goto logical_done_nocc; | |
0016a4cf PM |
1156 | |
1157 | case 29: /* andis. */ | |
1158 | imm = (unsigned short) instr; | |
3cdfcbfd PM |
1159 | op->val = regs->gpr[rd] & (imm << 16); |
1160 | set_cr0(regs, op, ra); | |
1161 | goto logical_done_nocc; | |
0016a4cf PM |
1162 | |
1163 | #ifdef __powerpc64__ | |
1164 | case 30: /* rld* */ | |
1165 | mb = ((instr >> 6) & 0x1f) | (instr & 0x20); | |
1166 | val = regs->gpr[rd]; | |
1167 | if ((instr & 0x10) == 0) { | |
1168 | sh = rb | ((instr & 2) << 4); | |
1169 | val = ROTATE(val, sh); | |
1170 | switch ((instr >> 2) & 3) { | |
1171 | case 0: /* rldicl */ | |
3cdfcbfd PM |
1172 | val &= MASK64_L(mb); |
1173 | break; | |
0016a4cf | 1174 | case 1: /* rldicr */ |
3cdfcbfd PM |
1175 | val &= MASK64_R(mb); |
1176 | break; | |
0016a4cf | 1177 | case 2: /* rldic */ |
3cdfcbfd PM |
1178 | val &= MASK64(mb, 63 - sh); |
1179 | break; | |
0016a4cf PM |
1180 | case 3: /* rldimi */ |
1181 | imm = MASK64(mb, 63 - sh); | |
3cdfcbfd | 1182 | val = (regs->gpr[ra] & ~imm) | |
0016a4cf | 1183 | (val & imm); |
0016a4cf | 1184 | } |
3cdfcbfd PM |
1185 | op->val = val; |
1186 | goto logical_done; | |
0016a4cf PM |
1187 | } else { |
1188 | sh = regs->gpr[rb] & 0x3f; | |
1189 | val = ROTATE(val, sh); | |
1190 | switch ((instr >> 1) & 7) { | |
1191 | case 0: /* rldcl */ | |
3cdfcbfd | 1192 | op->val = val & MASK64_L(mb); |
0016a4cf PM |
1193 | goto logical_done; |
1194 | case 1: /* rldcr */ | |
3cdfcbfd | 1195 | op->val = val & MASK64_R(mb); |
0016a4cf PM |
1196 | goto logical_done; |
1197 | } | |
14cf11af | 1198 | } |
0016a4cf | 1199 | #endif |
3cdfcbfd PM |
1200 | op->type = UNKNOWN; /* illegal instruction */ |
1201 | return 0; | |
0016a4cf | 1202 | |
14cf11af | 1203 | case 31: |
f1bbb99f PM |
1204 | /* isel occupies 32 minor opcodes */ |
1205 | if (((instr >> 1) & 0x1f) == 15) { | |
1206 | mb = (instr >> 6) & 0x1f; /* bc field */ | |
1207 | val = (regs->ccr >> (31 - mb)) & 1; | |
1208 | val2 = (ra) ? regs->gpr[ra] : 0; | |
1209 | ||
1210 | op->val = (val) ? val2 : regs->gpr[rb]; | |
1211 | goto compute_done; | |
1212 | } | |
1213 | ||
0016a4cf | 1214 | switch ((instr >> 1) & 0x3ff) { |
cf87c3f6 PM |
1215 | case 4: /* tw */ |
1216 | if (rd == 0x1f || | |
1217 | (rd & trap_compare((int)regs->gpr[ra], | |
1218 | (int)regs->gpr[rb]))) | |
1219 | goto trap; | |
3cdfcbfd | 1220 | return 1; |
cf87c3f6 PM |
1221 | #ifdef __powerpc64__ |
1222 | case 68: /* td */ | |
1223 | if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) | |
1224 | goto trap; | |
3cdfcbfd | 1225 | return 1; |
cf87c3f6 | 1226 | #endif |
0016a4cf PM |
1227 | case 83: /* mfmsr */ |
1228 | if (regs->msr & MSR_PR) | |
be96f633 PM |
1229 | goto priv; |
1230 | op->type = MFMSR; | |
1231 | op->reg = rd; | |
1232 | return 0; | |
0016a4cf PM |
1233 | case 146: /* mtmsr */ |
1234 | if (regs->msr & MSR_PR) | |
be96f633 PM |
1235 | goto priv; |
1236 | op->type = MTMSR; | |
1237 | op->reg = rd; | |
1238 | op->val = 0xffffffff & ~(MSR_ME | MSR_LE); | |
1239 | return 0; | |
c032524f | 1240 | #ifdef CONFIG_PPC64 |
0016a4cf | 1241 | case 178: /* mtmsrd */ |
0016a4cf | 1242 | if (regs->msr & MSR_PR) |
be96f633 PM |
1243 | goto priv; |
1244 | op->type = MTMSR; | |
1245 | op->reg = rd; | |
1246 | /* only MSR_EE and MSR_RI get changed if bit 15 set */ | |
1247 | /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */ | |
1248 | imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL; | |
1249 | op->val = imm; | |
1250 | return 0; | |
c032524f | 1251 | #endif |
be96f633 | 1252 | |
0016a4cf | 1253 | case 19: /* mfcr */ |
3cdfcbfd | 1254 | imm = 0xffffffffUL; |
64e756c5 AB |
1255 | if ((instr >> 20) & 1) { |
1256 | imm = 0xf0000000UL; | |
1257 | for (sh = 0; sh < 8; ++sh) { | |
3cdfcbfd | 1258 | if (instr & (0x80000 >> sh)) |
64e756c5 | 1259 | break; |
64e756c5 AB |
1260 | imm >>= 4; |
1261 | } | |
64e756c5 | 1262 | } |
3cdfcbfd PM |
1263 | op->val = regs->ccr & imm; |
1264 | goto compute_done; | |
0016a4cf PM |
1265 | |
1266 | case 144: /* mtcrf */ | |
3cdfcbfd | 1267 | op->type = COMPUTE + SETCC; |
0016a4cf PM |
1268 | imm = 0xf0000000UL; |
1269 | val = regs->gpr[rd]; | |
3cdfcbfd | 1270 | op->val = regs->ccr; |
0016a4cf PM |
1271 | for (sh = 0; sh < 8; ++sh) { |
1272 | if (instr & (0x80000 >> sh)) | |
3cdfcbfd | 1273 | op->val = (op->val & ~imm) | |
0016a4cf PM |
1274 | (val & imm); |
1275 | imm >>= 4; | |
1276 | } | |
3cdfcbfd | 1277 | return 1; |
0016a4cf PM |
1278 | |
1279 | case 339: /* mfspr */ | |
be96f633 | 1280 | spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); |
3cdfcbfd PM |
1281 | op->type = MFSPR; |
1282 | op->reg = rd; | |
1283 | op->spr = spr; | |
1284 | if (spr == SPRN_XER || spr == SPRN_LR || | |
1285 | spr == SPRN_CTR) | |
1286 | return 1; | |
1287 | return 0; | |
0016a4cf PM |
1288 | |
1289 | case 467: /* mtspr */ | |
be96f633 | 1290 | spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); |
3cdfcbfd PM |
1291 | op->type = MTSPR; |
1292 | op->val = regs->gpr[rd]; | |
1293 | op->spr = spr; | |
1294 | if (spr == SPRN_XER || spr == SPRN_LR || | |
1295 | spr == SPRN_CTR) | |
1296 | return 1; | |
1297 | return 0; | |
0016a4cf PM |
1298 | |
1299 | /* | |
1300 | * Compare instructions | |
1301 | */ | |
1302 | case 0: /* cmp */ | |
1303 | val = regs->gpr[ra]; | |
1304 | val2 = regs->gpr[rb]; | |
1305 | #ifdef __powerpc64__ | |
1306 | if ((rd & 1) == 0) { | |
1307 | /* word (32-bit) compare */ | |
1308 | val = (int) val; | |
1309 | val2 = (int) val2; | |
1310 | } | |
1311 | #endif | |
3cdfcbfd PM |
1312 | do_cmp_signed(regs, op, val, val2, rd >> 2); |
1313 | return 1; | |
0016a4cf PM |
1314 | |
1315 | case 32: /* cmpl */ | |
1316 | val = regs->gpr[ra]; | |
1317 | val2 = regs->gpr[rb]; | |
1318 | #ifdef __powerpc64__ | |
1319 | if ((rd & 1) == 0) { | |
1320 | /* word (32-bit) compare */ | |
1321 | val = (unsigned int) val; | |
1322 | val2 = (unsigned int) val2; | |
1323 | } | |
1324 | #endif | |
3cdfcbfd PM |
1325 | do_cmp_unsigned(regs, op, val, val2, rd >> 2); |
1326 | return 1; | |
0016a4cf | 1327 | |
02c0f62a | 1328 | case 508: /* cmpb */ |
3cdfcbfd PM |
1329 | do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]); |
1330 | goto logical_done_nocc; | |
02c0f62a | 1331 | |
0016a4cf PM |
1332 | /* |
1333 | * Arithmetic instructions | |
1334 | */ | |
1335 | case 8: /* subfc */ | |
3cdfcbfd | 1336 | add_with_carry(regs, op, rd, ~regs->gpr[ra], |
0016a4cf PM |
1337 | regs->gpr[rb], 1); |
1338 | goto arith_done; | |
1339 | #ifdef __powerpc64__ | |
1340 | case 9: /* mulhdu */ | |
3cdfcbfd | 1341 | asm("mulhdu %0,%1,%2" : "=r" (op->val) : |
0016a4cf PM |
1342 | "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); |
1343 | goto arith_done; | |
1344 | #endif | |
1345 | case 10: /* addc */ | |
3cdfcbfd | 1346 | add_with_carry(regs, op, rd, regs->gpr[ra], |
0016a4cf PM |
1347 | regs->gpr[rb], 0); |
1348 | goto arith_done; | |
1349 | ||
1350 | case 11: /* mulhwu */ | |
3cdfcbfd | 1351 | asm("mulhwu %0,%1,%2" : "=r" (op->val) : |
0016a4cf PM |
1352 | "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); |
1353 | goto arith_done; | |
1354 | ||
1355 | case 40: /* subf */ | |
3cdfcbfd | 1356 | op->val = regs->gpr[rb] - regs->gpr[ra]; |
0016a4cf PM |
1357 | goto arith_done; |
1358 | #ifdef __powerpc64__ | |
1359 | case 73: /* mulhd */ | |
3cdfcbfd | 1360 | asm("mulhd %0,%1,%2" : "=r" (op->val) : |
0016a4cf PM |
1361 | "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); |
1362 | goto arith_done; | |
1363 | #endif | |
1364 | case 75: /* mulhw */ | |
3cdfcbfd | 1365 | asm("mulhw %0,%1,%2" : "=r" (op->val) : |
0016a4cf PM |
1366 | "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); |
1367 | goto arith_done; | |
1368 | ||
1369 | case 104: /* neg */ | |
3cdfcbfd | 1370 | op->val = -regs->gpr[ra]; |
0016a4cf PM |
1371 | goto arith_done; |
1372 | ||
1373 | case 136: /* subfe */ | |
3cdfcbfd PM |
1374 | add_with_carry(regs, op, rd, ~regs->gpr[ra], |
1375 | regs->gpr[rb], regs->xer & XER_CA); | |
0016a4cf PM |
1376 | goto arith_done; |
1377 | ||
1378 | case 138: /* adde */ | |
3cdfcbfd PM |
1379 | add_with_carry(regs, op, rd, regs->gpr[ra], |
1380 | regs->gpr[rb], regs->xer & XER_CA); | |
0016a4cf PM |
1381 | goto arith_done; |
1382 | ||
1383 | case 200: /* subfze */ | |
3cdfcbfd | 1384 | add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L, |
0016a4cf PM |
1385 | regs->xer & XER_CA); |
1386 | goto arith_done; | |
1387 | ||
1388 | case 202: /* addze */ | |
3cdfcbfd | 1389 | add_with_carry(regs, op, rd, regs->gpr[ra], 0L, |
0016a4cf PM |
1390 | regs->xer & XER_CA); |
1391 | goto arith_done; | |
1392 | ||
1393 | case 232: /* subfme */ | |
3cdfcbfd | 1394 | add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L, |
0016a4cf PM |
1395 | regs->xer & XER_CA); |
1396 | goto arith_done; | |
1397 | #ifdef __powerpc64__ | |
1398 | case 233: /* mulld */ | |
3cdfcbfd | 1399 | op->val = regs->gpr[ra] * regs->gpr[rb]; |
0016a4cf PM |
1400 | goto arith_done; |
1401 | #endif | |
1402 | case 234: /* addme */ | |
3cdfcbfd | 1403 | add_with_carry(regs, op, rd, regs->gpr[ra], -1L, |
0016a4cf PM |
1404 | regs->xer & XER_CA); |
1405 | goto arith_done; | |
1406 | ||
1407 | case 235: /* mullw */ | |
3cdfcbfd | 1408 | op->val = (unsigned int) regs->gpr[ra] * |
0016a4cf PM |
1409 | (unsigned int) regs->gpr[rb]; |
1410 | goto arith_done; | |
1411 | ||
1412 | case 266: /* add */ | |
3cdfcbfd | 1413 | op->val = regs->gpr[ra] + regs->gpr[rb]; |
0016a4cf PM |
1414 | goto arith_done; |
1415 | #ifdef __powerpc64__ | |
1416 | case 457: /* divdu */ | |
3cdfcbfd | 1417 | op->val = regs->gpr[ra] / regs->gpr[rb]; |
0016a4cf PM |
1418 | goto arith_done; |
1419 | #endif | |
1420 | case 459: /* divwu */ | |
3cdfcbfd | 1421 | op->val = (unsigned int) regs->gpr[ra] / |
0016a4cf PM |
1422 | (unsigned int) regs->gpr[rb]; |
1423 | goto arith_done; | |
1424 | #ifdef __powerpc64__ | |
1425 | case 489: /* divd */ | |
3cdfcbfd | 1426 | op->val = (long int) regs->gpr[ra] / |
0016a4cf PM |
1427 | (long int) regs->gpr[rb]; |
1428 | goto arith_done; | |
1429 | #endif | |
1430 | case 491: /* divw */ | |
3cdfcbfd | 1431 | op->val = (int) regs->gpr[ra] / |
0016a4cf PM |
1432 | (int) regs->gpr[rb]; |
1433 | goto arith_done; | |
1434 | ||
1435 | ||
1436 | /* | |
1437 | * Logical instructions | |
1438 | */ | |
1439 | case 26: /* cntlzw */ | |
3cdfcbfd | 1440 | op->val = __builtin_clz((unsigned int) regs->gpr[rd]); |
0016a4cf PM |
1441 | goto logical_done; |
1442 | #ifdef __powerpc64__ | |
1443 | case 58: /* cntlzd */ | |
3cdfcbfd | 1444 | op->val = __builtin_clzl(regs->gpr[rd]); |
0016a4cf PM |
1445 | goto logical_done; |
1446 | #endif | |
1447 | case 28: /* and */ | |
3cdfcbfd | 1448 | op->val = regs->gpr[rd] & regs->gpr[rb]; |
0016a4cf PM |
1449 | goto logical_done; |
1450 | ||
1451 | case 60: /* andc */ | |
3cdfcbfd | 1452 | op->val = regs->gpr[rd] & ~regs->gpr[rb]; |
0016a4cf PM |
1453 | goto logical_done; |
1454 | ||
dcbd19b4 | 1455 | case 122: /* popcntb */ |
3cdfcbfd | 1456 | do_popcnt(regs, op, regs->gpr[rd], 8); |
5762e083 | 1457 | goto logical_done_nocc; |
dcbd19b4 | 1458 | |
0016a4cf | 1459 | case 124: /* nor */ |
3cdfcbfd | 1460 | op->val = ~(regs->gpr[rd] | regs->gpr[rb]); |
0016a4cf | 1461 | goto logical_done; |
2c979c48 MB |
1462 | |
1463 | case 154: /* prtyw */ | |
3cdfcbfd | 1464 | do_prty(regs, op, regs->gpr[rd], 32); |
5762e083 | 1465 | goto logical_done_nocc; |
2c979c48 MB |
1466 | |
1467 | case 186: /* prtyd */ | |
3cdfcbfd | 1468 | do_prty(regs, op, regs->gpr[rd], 64); |
5762e083 | 1469 | goto logical_done_nocc; |
f312793d MB |
1470 | #ifdef CONFIG_PPC64 |
1471 | case 252: /* bpermd */ | |
3cdfcbfd | 1472 | do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]); |
5762e083 | 1473 | goto logical_done_nocc; |
f312793d | 1474 | #endif |
0016a4cf | 1475 | case 284: /* xor */ |
3cdfcbfd | 1476 | op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); |
0016a4cf PM |
1477 | goto logical_done; |
1478 | ||
1479 | case 316: /* xor */ | |
3cdfcbfd | 1480 | op->val = regs->gpr[rd] ^ regs->gpr[rb]; |
0016a4cf PM |
1481 | goto logical_done; |
1482 | ||
dcbd19b4 | 1483 | case 378: /* popcntw */ |
3cdfcbfd | 1484 | do_popcnt(regs, op, regs->gpr[rd], 32); |
5762e083 | 1485 | goto logical_done_nocc; |
dcbd19b4 | 1486 | |
0016a4cf | 1487 | case 412: /* orc */ |
3cdfcbfd | 1488 | op->val = regs->gpr[rd] | ~regs->gpr[rb]; |
0016a4cf PM |
1489 | goto logical_done; |
1490 | ||
1491 | case 444: /* or */ | |
3cdfcbfd | 1492 | op->val = regs->gpr[rd] | regs->gpr[rb]; |
0016a4cf PM |
1493 | goto logical_done; |
1494 | ||
1495 | case 476: /* nand */ | |
3cdfcbfd | 1496 | op->val = ~(regs->gpr[rd] & regs->gpr[rb]); |
0016a4cf | 1497 | goto logical_done; |
dcbd19b4 MB |
1498 | #ifdef CONFIG_PPC64 |
1499 | case 506: /* popcntd */ | |
3cdfcbfd | 1500 | do_popcnt(regs, op, regs->gpr[rd], 64); |
5762e083 | 1501 | goto logical_done_nocc; |
dcbd19b4 | 1502 | #endif |
0016a4cf | 1503 | case 922: /* extsh */ |
3cdfcbfd | 1504 | op->val = (signed short) regs->gpr[rd]; |
0016a4cf PM |
1505 | goto logical_done; |
1506 | ||
1507 | case 954: /* extsb */ | |
3cdfcbfd | 1508 | op->val = (signed char) regs->gpr[rd]; |
0016a4cf PM |
1509 | goto logical_done; |
1510 | #ifdef __powerpc64__ | |
1511 | case 986: /* extsw */ | |
3cdfcbfd | 1512 | op->val = (signed int) regs->gpr[rd]; |
0016a4cf PM |
1513 | goto logical_done; |
1514 | #endif | |
1515 | ||
1516 | /* | |
1517 | * Shift instructions | |
1518 | */ | |
1519 | case 24: /* slw */ | |
1520 | sh = regs->gpr[rb] & 0x3f; | |
1521 | if (sh < 32) | |
3cdfcbfd | 1522 | op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; |
0016a4cf | 1523 | else |
3cdfcbfd | 1524 | op->val = 0; |
0016a4cf PM |
1525 | goto logical_done; |
1526 | ||
1527 | case 536: /* srw */ | |
1528 | sh = regs->gpr[rb] & 0x3f; | |
1529 | if (sh < 32) | |
3cdfcbfd | 1530 | op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; |
0016a4cf | 1531 | else |
3cdfcbfd | 1532 | op->val = 0; |
0016a4cf PM |
1533 | goto logical_done; |
1534 | ||
1535 | case 792: /* sraw */ | |
3cdfcbfd | 1536 | op->type = COMPUTE + SETREG + SETXER; |
0016a4cf PM |
1537 | sh = regs->gpr[rb] & 0x3f; |
1538 | ival = (signed int) regs->gpr[rd]; | |
3cdfcbfd PM |
1539 | op->val = ival >> (sh < 32 ? sh : 31); |
1540 | op->xerval = regs->xer; | |
e698b966 | 1541 | if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) |
3cdfcbfd | 1542 | op->xerval |= XER_CA; |
0016a4cf | 1543 | else |
3cdfcbfd | 1544 | op->xerval &= ~XER_CA; |
0016a4cf PM |
1545 | goto logical_done; |
1546 | ||
1547 | case 824: /* srawi */ | |
3cdfcbfd | 1548 | op->type = COMPUTE + SETREG + SETXER; |
0016a4cf PM |
1549 | sh = rb; |
1550 | ival = (signed int) regs->gpr[rd]; | |
3cdfcbfd PM |
1551 | op->val = ival >> sh; |
1552 | op->xerval = regs->xer; | |
e698b966 | 1553 | if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) |
3cdfcbfd | 1554 | op->xerval |= XER_CA; |
0016a4cf | 1555 | else |
3cdfcbfd | 1556 | op->xerval &= ~XER_CA; |
0016a4cf PM |
1557 | goto logical_done; |
1558 | ||
1559 | #ifdef __powerpc64__ | |
1560 | case 27: /* sld */ | |
e698b966 | 1561 | sh = regs->gpr[rb] & 0x7f; |
0016a4cf | 1562 | if (sh < 64) |
3cdfcbfd | 1563 | op->val = regs->gpr[rd] << sh; |
0016a4cf | 1564 | else |
3cdfcbfd | 1565 | op->val = 0; |
0016a4cf PM |
1566 | goto logical_done; |
1567 | ||
1568 | case 539: /* srd */ | |
1569 | sh = regs->gpr[rb] & 0x7f; | |
1570 | if (sh < 64) | |
3cdfcbfd | 1571 | op->val = regs->gpr[rd] >> sh; |
0016a4cf | 1572 | else |
3cdfcbfd | 1573 | op->val = 0; |
0016a4cf PM |
1574 | goto logical_done; |
1575 | ||
1576 | case 794: /* srad */ | |
3cdfcbfd | 1577 | op->type = COMPUTE + SETREG + SETXER; |
0016a4cf PM |
1578 | sh = regs->gpr[rb] & 0x7f; |
1579 | ival = (signed long int) regs->gpr[rd]; | |
3cdfcbfd PM |
1580 | op->val = ival >> (sh < 64 ? sh : 63); |
1581 | op->xerval = regs->xer; | |
e698b966 | 1582 | if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) |
3cdfcbfd | 1583 | op->xerval |= XER_CA; |
0016a4cf | 1584 | else |
3cdfcbfd | 1585 | op->xerval &= ~XER_CA; |
0016a4cf PM |
1586 | goto logical_done; |
1587 | ||
1588 | case 826: /* sradi with sh_5 = 0 */ | |
1589 | case 827: /* sradi with sh_5 = 1 */ | |
3cdfcbfd | 1590 | op->type = COMPUTE + SETREG + SETXER; |
0016a4cf PM |
1591 | sh = rb | ((instr & 2) << 4); |
1592 | ival = (signed long int) regs->gpr[rd]; | |
3cdfcbfd PM |
1593 | op->val = ival >> sh; |
1594 | op->xerval = regs->xer; | |
e698b966 | 1595 | if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) |
3cdfcbfd | 1596 | op->xerval |= XER_CA; |
0016a4cf | 1597 | else |
3cdfcbfd | 1598 | op->xerval &= ~XER_CA; |
0016a4cf PM |
1599 | goto logical_done; |
1600 | #endif /* __powerpc64__ */ | |
1601 | ||
1602 | /* | |
1603 | * Cache instructions | |
1604 | */ | |
1605 | case 54: /* dcbst */ | |
be96f633 PM |
1606 | op->type = MKOP(CACHEOP, DCBST, 0); |
1607 | op->ea = xform_ea(instr, regs); | |
1608 | return 0; | |
0016a4cf PM |
1609 | |
1610 | case 86: /* dcbf */ | |
be96f633 PM |
1611 | op->type = MKOP(CACHEOP, DCBF, 0); |
1612 | op->ea = xform_ea(instr, regs); | |
1613 | return 0; | |
0016a4cf PM |
1614 | |
1615 | case 246: /* dcbtst */ | |
be96f633 PM |
1616 | op->type = MKOP(CACHEOP, DCBTST, 0); |
1617 | op->ea = xform_ea(instr, regs); | |
1618 | op->reg = rd; | |
1619 | return 0; | |
0016a4cf PM |
1620 | |
1621 | case 278: /* dcbt */ | |
be96f633 PM |
1622 | op->type = MKOP(CACHEOP, DCBTST, 0); |
1623 | op->ea = xform_ea(instr, regs); | |
1624 | op->reg = rd; | |
1625 | return 0; | |
cf87c3f6 PM |
1626 | |
1627 | case 982: /* icbi */ | |
1628 | op->type = MKOP(CACHEOP, ICBI, 0); | |
1629 | op->ea = xform_ea(instr, regs); | |
1630 | return 0; | |
14cf11af | 1631 | } |
0016a4cf | 1632 | break; |
14cf11af | 1633 | } |
0016a4cf | 1634 | |
350779a2 PM |
1635 | /* |
1636 | * Loads and stores. | |
1637 | */ | |
be96f633 PM |
1638 | op->type = UNKNOWN; |
1639 | op->update_reg = ra; | |
1640 | op->reg = rd; | |
1641 | op->val = regs->gpr[rd]; | |
1642 | u = (instr >> 20) & UPDATE; | |
350779a2 | 1643 | op->vsx_flags = 0; |
0016a4cf PM |
1644 | |
1645 | switch (opcode) { | |
1646 | case 31: | |
be96f633 PM |
1647 | u = instr & UPDATE; |
1648 | op->ea = xform_ea(instr, regs); | |
0016a4cf PM |
1649 | switch ((instr >> 1) & 0x3ff) { |
1650 | case 20: /* lwarx */ | |
be96f633 PM |
1651 | op->type = MKOP(LARX, 0, 4); |
1652 | break; | |
0016a4cf PM |
1653 | |
1654 | case 150: /* stwcx. */ | |
be96f633 PM |
1655 | op->type = MKOP(STCX, 0, 4); |
1656 | break; | |
0016a4cf PM |
1657 | |
1658 | #ifdef __powerpc64__ | |
1659 | case 84: /* ldarx */ | |
be96f633 PM |
1660 | op->type = MKOP(LARX, 0, 8); |
1661 | break; | |
0016a4cf PM |
1662 | |
1663 | case 214: /* stdcx. */ | |
be96f633 PM |
1664 | op->type = MKOP(STCX, 0, 8); |
1665 | break; | |
0016a4cf | 1666 | |
350779a2 PM |
1667 | case 52: /* lbarx */ |
1668 | op->type = MKOP(LARX, 0, 1); | |
1669 | break; | |
1670 | ||
1671 | case 694: /* stbcx. */ | |
1672 | op->type = MKOP(STCX, 0, 1); | |
1673 | break; | |
1674 | ||
1675 | case 116: /* lharx */ | |
1676 | op->type = MKOP(LARX, 0, 2); | |
1677 | break; | |
1678 | ||
1679 | case 726: /* sthcx. */ | |
1680 | op->type = MKOP(STCX, 0, 2); | |
1681 | break; | |
1682 | ||
1683 | case 276: /* lqarx */ | |
1684 | if (!((rd & 1) || rd == ra || rd == rb)) | |
1685 | op->type = MKOP(LARX, 0, 16); | |
1686 | break; | |
1687 | ||
1688 | case 182: /* stqcx. */ | |
1689 | if (!(rd & 1)) | |
1690 | op->type = MKOP(STCX, 0, 16); | |
be96f633 | 1691 | break; |
0016a4cf PM |
1692 | #endif |
1693 | ||
1694 | case 23: /* lwzx */ | |
1695 | case 55: /* lwzux */ | |
be96f633 PM |
1696 | op->type = MKOP(LOAD, u, 4); |
1697 | break; | |
0016a4cf PM |
1698 | |
1699 | case 87: /* lbzx */ | |
1700 | case 119: /* lbzux */ | |
be96f633 PM |
1701 | op->type = MKOP(LOAD, u, 1); |
1702 | break; | |
0016a4cf PM |
1703 | |
1704 | #ifdef CONFIG_ALTIVEC | |
1705 | case 103: /* lvx */ | |
1706 | case 359: /* lvxl */ | |
be96f633 | 1707 | op->type = MKOP(LOAD_VMX, 0, 16); |
350779a2 | 1708 | op->element_size = 16; |
be96f633 | 1709 | break; |
0016a4cf PM |
1710 | |
1711 | case 231: /* stvx */ | |
1712 | case 487: /* stvxl */ | |
be96f633 PM |
1713 | op->type = MKOP(STORE_VMX, 0, 16); |
1714 | break; | |
0016a4cf PM |
1715 | #endif /* CONFIG_ALTIVEC */ |
1716 | ||
1717 | #ifdef __powerpc64__ | |
350779a2 PM |
1718 | case 21: /* ldx */ |
1719 | case 53: /* ldux */ | |
1720 | op->type = MKOP(LOAD, u, 8); | |
1721 | break; | |
1722 | ||
0016a4cf PM |
1723 | case 149: /* stdx */ |
1724 | case 181: /* stdux */ | |
be96f633 PM |
1725 | op->type = MKOP(STORE, u, 8); |
1726 | break; | |
0016a4cf PM |
1727 | #endif |
1728 | ||
1729 | case 151: /* stwx */ | |
1730 | case 183: /* stwux */ | |
be96f633 PM |
1731 | op->type = MKOP(STORE, u, 4); |
1732 | break; | |
0016a4cf PM |
1733 | |
1734 | case 215: /* stbx */ | |
1735 | case 247: /* stbux */ | |
be96f633 PM |
1736 | op->type = MKOP(STORE, u, 1); |
1737 | break; | |
0016a4cf PM |
1738 | |
1739 | case 279: /* lhzx */ | |
1740 | case 311: /* lhzux */ | |
be96f633 PM |
1741 | op->type = MKOP(LOAD, u, 2); |
1742 | break; | |
0016a4cf PM |
1743 | |
1744 | #ifdef __powerpc64__ | |
1745 | case 341: /* lwax */ | |
1746 | case 373: /* lwaux */ | |
be96f633 PM |
1747 | op->type = MKOP(LOAD, SIGNEXT | u, 4); |
1748 | break; | |
0016a4cf PM |
1749 | #endif |
1750 | ||
1751 | case 343: /* lhax */ | |
1752 | case 375: /* lhaux */ | |
be96f633 PM |
1753 | op->type = MKOP(LOAD, SIGNEXT | u, 2); |
1754 | break; | |
0016a4cf PM |
1755 | |
1756 | case 407: /* sthx */ | |
1757 | case 439: /* sthux */ | |
be96f633 PM |
1758 | op->type = MKOP(STORE, u, 2); |
1759 | break; | |
0016a4cf PM |
1760 | |
1761 | #ifdef __powerpc64__ | |
1762 | case 532: /* ldbrx */ | |
be96f633 PM |
1763 | op->type = MKOP(LOAD, BYTEREV, 8); |
1764 | break; | |
0016a4cf PM |
1765 | |
1766 | #endif | |
c9f6f4ed PM |
1767 | case 533: /* lswx */ |
1768 | op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); | |
1769 | break; | |
0016a4cf PM |
1770 | |
1771 | case 534: /* lwbrx */ | |
be96f633 PM |
1772 | op->type = MKOP(LOAD, BYTEREV, 4); |
1773 | break; | |
0016a4cf | 1774 | |
c9f6f4ed PM |
1775 | case 597: /* lswi */ |
1776 | if (rb == 0) | |
1777 | rb = 32; /* # bytes to load */ | |
1778 | op->type = MKOP(LOAD_MULTI, 0, rb); | |
d120cdbc | 1779 | op->ea = ra ? regs->gpr[ra] : 0; |
c9f6f4ed PM |
1780 | break; |
1781 | ||
b69a1da9 | 1782 | #ifdef CONFIG_PPC_FPU |
0016a4cf PM |
1783 | case 535: /* lfsx */ |
1784 | case 567: /* lfsux */ | |
be96f633 PM |
1785 | op->type = MKOP(LOAD_FP, u, 4); |
1786 | break; | |
0016a4cf PM |
1787 | |
1788 | case 599: /* lfdx */ | |
1789 | case 631: /* lfdux */ | |
be96f633 PM |
1790 | op->type = MKOP(LOAD_FP, u, 8); |
1791 | break; | |
0016a4cf PM |
1792 | |
1793 | case 663: /* stfsx */ | |
1794 | case 695: /* stfsux */ | |
be96f633 PM |
1795 | op->type = MKOP(STORE_FP, u, 4); |
1796 | break; | |
0016a4cf PM |
1797 | |
1798 | case 727: /* stfdx */ | |
1799 | case 759: /* stfdux */ | |
be96f633 PM |
1800 | op->type = MKOP(STORE_FP, u, 8); |
1801 | break; | |
cd64d169 | 1802 | #endif |
0016a4cf PM |
1803 | |
1804 | #ifdef __powerpc64__ | |
1805 | case 660: /* stdbrx */ | |
be96f633 PM |
1806 | op->type = MKOP(STORE, BYTEREV, 8); |
1807 | op->val = byterev_8(regs->gpr[rd]); | |
1808 | break; | |
0016a4cf PM |
1809 | |
1810 | #endif | |
c9f6f4ed PM |
1811 | case 661: /* stswx */ |
1812 | op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); | |
1813 | break; | |
1814 | ||
0016a4cf | 1815 | case 662: /* stwbrx */ |
be96f633 PM |
1816 | op->type = MKOP(STORE, BYTEREV, 4); |
1817 | op->val = byterev_4(regs->gpr[rd]); | |
1818 | break; | |
0016a4cf | 1819 | |
c9f6f4ed PM |
1820 | case 725: |
1821 | if (rb == 0) | |
1822 | rb = 32; /* # bytes to store */ | |
1823 | op->type = MKOP(STORE_MULTI, 0, rb); | |
d120cdbc | 1824 | op->ea = ra ? regs->gpr[ra] : 0; |
c9f6f4ed PM |
1825 | break; |
1826 | ||
0016a4cf | 1827 | case 790: /* lhbrx */ |
be96f633 PM |
1828 | op->type = MKOP(LOAD, BYTEREV, 2); |
1829 | break; | |
0016a4cf PM |
1830 | |
1831 | case 918: /* sthbrx */ | |
be96f633 PM |
1832 | op->type = MKOP(STORE, BYTEREV, 2); |
1833 | op->val = byterev_2(regs->gpr[rd]); | |
1834 | break; | |
0016a4cf PM |
1835 | |
1836 | #ifdef CONFIG_VSX | |
350779a2 PM |
1837 | case 12: /* lxsiwzx */ |
1838 | op->reg = rd | ((instr & 1) << 5); | |
1839 | op->type = MKOP(LOAD_VSX, 0, 4); | |
1840 | op->element_size = 8; | |
1841 | break; | |
1842 | ||
1843 | case 76: /* lxsiwax */ | |
1844 | op->reg = rd | ((instr & 1) << 5); | |
1845 | op->type = MKOP(LOAD_VSX, SIGNEXT, 4); | |
1846 | op->element_size = 8; | |
1847 | break; | |
1848 | ||
1849 | case 140: /* stxsiwx */ | |
1850 | op->reg = rd | ((instr & 1) << 5); | |
1851 | op->type = MKOP(STORE_VSX, 0, 4); | |
1852 | op->element_size = 8; | |
1853 | break; | |
1854 | ||
1855 | case 268: /* lxvx */ | |
1856 | op->reg = rd | ((instr & 1) << 5); | |
1857 | op->type = MKOP(LOAD_VSX, 0, 16); | |
1858 | op->element_size = 16; | |
1859 | op->vsx_flags = VSX_CHECK_VEC; | |
1860 | break; | |
1861 | ||
1862 | case 269: /* lxvl */ | |
1863 | case 301: { /* lxvll */ | |
1864 | int nb; | |
1865 | op->reg = rd | ((instr & 1) << 5); | |
1866 | op->ea = ra ? regs->gpr[ra] : 0; | |
1867 | nb = regs->gpr[rb] & 0xff; | |
1868 | if (nb > 16) | |
1869 | nb = 16; | |
1870 | op->type = MKOP(LOAD_VSX, 0, nb); | |
1871 | op->element_size = 16; | |
1872 | op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | | |
1873 | VSX_CHECK_VEC; | |
1874 | break; | |
1875 | } | |
1876 | case 332: /* lxvdsx */ | |
1877 | op->reg = rd | ((instr & 1) << 5); | |
1878 | op->type = MKOP(LOAD_VSX, 0, 8); | |
1879 | op->element_size = 8; | |
1880 | op->vsx_flags = VSX_SPLAT; | |
1881 | break; | |
1882 | ||
1883 | case 364: /* lxvwsx */ | |
1884 | op->reg = rd | ((instr & 1) << 5); | |
1885 | op->type = MKOP(LOAD_VSX, 0, 4); | |
1886 | op->element_size = 4; | |
1887 | op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC; | |
1888 | break; | |
1889 | ||
1890 | case 396: /* stxvx */ | |
1891 | op->reg = rd | ((instr & 1) << 5); | |
1892 | op->type = MKOP(STORE_VSX, 0, 16); | |
1893 | op->element_size = 16; | |
1894 | op->vsx_flags = VSX_CHECK_VEC; | |
1895 | break; | |
1896 | ||
1897 | case 397: /* stxvl */ | |
1898 | case 429: { /* stxvll */ | |
1899 | int nb; | |
1900 | op->reg = rd | ((instr & 1) << 5); | |
1901 | op->ea = ra ? regs->gpr[ra] : 0; | |
1902 | nb = regs->gpr[rb] & 0xff; | |
1903 | if (nb > 16) | |
1904 | nb = 16; | |
1905 | op->type = MKOP(STORE_VSX, 0, nb); | |
1906 | op->element_size = 16; | |
1907 | op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) | | |
1908 | VSX_CHECK_VEC; | |
1909 | break; | |
1910 | } | |
1911 | case 524: /* lxsspx */ | |
1912 | op->reg = rd | ((instr & 1) << 5); | |
1913 | op->type = MKOP(LOAD_VSX, 0, 4); | |
1914 | op->element_size = 8; | |
1915 | op->vsx_flags = VSX_FPCONV; | |
1916 | break; | |
1917 | ||
1918 | case 588: /* lxsdx */ | |
1919 | op->reg = rd | ((instr & 1) << 5); | |
1920 | op->type = MKOP(LOAD_VSX, 0, 8); | |
1921 | op->element_size = 8; | |
1922 | break; | |
1923 | ||
1924 | case 652: /* stxsspx */ | |
1925 | op->reg = rd | ((instr & 1) << 5); | |
1926 | op->type = MKOP(STORE_VSX, 0, 4); | |
1927 | op->element_size = 8; | |
1928 | op->vsx_flags = VSX_FPCONV; | |
1929 | break; | |
1930 | ||
1931 | case 716: /* stxsdx */ | |
1932 | op->reg = rd | ((instr & 1) << 5); | |
1933 | op->type = MKOP(STORE_VSX, 0, 8); | |
1934 | op->element_size = 8; | |
1935 | break; | |
1936 | ||
1937 | case 780: /* lxvw4x */ | |
1938 | op->reg = rd | ((instr & 1) << 5); | |
1939 | op->type = MKOP(LOAD_VSX, 0, 16); | |
1940 | op->element_size = 4; | |
1941 | break; | |
1942 | ||
1943 | case 781: /* lxsibzx */ | |
1944 | op->reg = rd | ((instr & 1) << 5); | |
1945 | op->type = MKOP(LOAD_VSX, 0, 1); | |
1946 | op->element_size = 8; | |
1947 | op->vsx_flags = VSX_CHECK_VEC; | |
1948 | break; | |
1949 | ||
1950 | case 812: /* lxvh8x */ | |
1951 | op->reg = rd | ((instr & 1) << 5); | |
1952 | op->type = MKOP(LOAD_VSX, 0, 16); | |
1953 | op->element_size = 2; | |
1954 | op->vsx_flags = VSX_CHECK_VEC; | |
1955 | break; | |
1956 | ||
1957 | case 813: /* lxsihzx */ | |
1958 | op->reg = rd | ((instr & 1) << 5); | |
1959 | op->type = MKOP(LOAD_VSX, 0, 2); | |
1960 | op->element_size = 8; | |
1961 | op->vsx_flags = VSX_CHECK_VEC; | |
1962 | break; | |
1963 | ||
0016a4cf | 1964 | case 844: /* lxvd2x */ |
be96f633 | 1965 | op->reg = rd | ((instr & 1) << 5); |
350779a2 PM |
1966 | op->type = MKOP(LOAD_VSX, 0, 16); |
1967 | op->element_size = 8; | |
1968 | break; | |
1969 | ||
1970 | case 876: /* lxvb16x */ | |
1971 | op->reg = rd | ((instr & 1) << 5); | |
1972 | op->type = MKOP(LOAD_VSX, 0, 16); | |
1973 | op->element_size = 1; | |
1974 | op->vsx_flags = VSX_CHECK_VEC; | |
1975 | break; | |
1976 | ||
1977 | case 908: /* stxvw4x */ | |
1978 | op->reg = rd | ((instr & 1) << 5); | |
1979 | op->type = MKOP(STORE_VSX, 0, 16); | |
1980 | op->element_size = 4; | |
1981 | break; | |
1982 | ||
1983 | case 909: /* stxsibx */ | |
1984 | op->reg = rd | ((instr & 1) << 5); | |
1985 | op->type = MKOP(STORE_VSX, 0, 1); | |
1986 | op->element_size = 8; | |
1987 | op->vsx_flags = VSX_CHECK_VEC; | |
1988 | break; | |
1989 | ||
1990 | case 940: /* stxvh8x */ | |
1991 | op->reg = rd | ((instr & 1) << 5); | |
1992 | op->type = MKOP(STORE_VSX, 0, 16); | |
1993 | op->element_size = 2; | |
1994 | op->vsx_flags = VSX_CHECK_VEC; | |
1995 | break; | |
1996 | ||
1997 | case 941: /* stxsihx */ | |
1998 | op->reg = rd | ((instr & 1) << 5); | |
1999 | op->type = MKOP(STORE_VSX, 0, 2); | |
2000 | op->element_size = 8; | |
2001 | op->vsx_flags = VSX_CHECK_VEC; | |
be96f633 | 2002 | break; |
0016a4cf PM |
2003 | |
2004 | case 972: /* stxvd2x */ | |
be96f633 | 2005 | op->reg = rd | ((instr & 1) << 5); |
350779a2 PM |
2006 | op->type = MKOP(STORE_VSX, 0, 16); |
2007 | op->element_size = 8; | |
2008 | break; | |
2009 | ||
2010 | case 1004: /* stxvb16x */ | |
2011 | op->reg = rd | ((instr & 1) << 5); | |
2012 | op->type = MKOP(STORE_VSX, 0, 16); | |
2013 | op->element_size = 1; | |
2014 | op->vsx_flags = VSX_CHECK_VEC; | |
be96f633 | 2015 | break; |
0016a4cf PM |
2016 | |
2017 | #endif /* CONFIG_VSX */ | |
2018 | } | |
2019 | break; | |
2020 | ||
2021 | case 32: /* lwz */ | |
2022 | case 33: /* lwzu */ | |
be96f633 PM |
2023 | op->type = MKOP(LOAD, u, 4); |
2024 | op->ea = dform_ea(instr, regs); | |
2025 | break; | |
0016a4cf PM |
2026 | |
2027 | case 34: /* lbz */ | |
2028 | case 35: /* lbzu */ | |
be96f633 PM |
2029 | op->type = MKOP(LOAD, u, 1); |
2030 | op->ea = dform_ea(instr, regs); | |
2031 | break; | |
0016a4cf PM |
2032 | |
2033 | case 36: /* stw */ | |
8e9f6937 | 2034 | case 37: /* stwu */ |
be96f633 PM |
2035 | op->type = MKOP(STORE, u, 4); |
2036 | op->ea = dform_ea(instr, regs); | |
2037 | break; | |
8e9f6937 | 2038 | |
0016a4cf PM |
2039 | case 38: /* stb */ |
2040 | case 39: /* stbu */ | |
be96f633 PM |
2041 | op->type = MKOP(STORE, u, 1); |
2042 | op->ea = dform_ea(instr, regs); | |
2043 | break; | |
0016a4cf PM |
2044 | |
2045 | case 40: /* lhz */ | |
2046 | case 41: /* lhzu */ | |
be96f633 PM |
2047 | op->type = MKOP(LOAD, u, 2); |
2048 | op->ea = dform_ea(instr, regs); | |
2049 | break; | |
0016a4cf PM |
2050 | |
2051 | case 42: /* lha */ | |
2052 | case 43: /* lhau */ | |
be96f633 PM |
2053 | op->type = MKOP(LOAD, SIGNEXT | u, 2); |
2054 | op->ea = dform_ea(instr, regs); | |
2055 | break; | |
0016a4cf PM |
2056 | |
2057 | case 44: /* sth */ | |
2058 | case 45: /* sthu */ | |
be96f633 PM |
2059 | op->type = MKOP(STORE, u, 2); |
2060 | op->ea = dform_ea(instr, regs); | |
2061 | break; | |
0016a4cf PM |
2062 | |
2063 | case 46: /* lmw */ | |
0016a4cf PM |
2064 | if (ra >= rd) |
2065 | break; /* invalid form, ra in range to load */ | |
c9f6f4ed | 2066 | op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); |
be96f633 PM |
2067 | op->ea = dform_ea(instr, regs); |
2068 | break; | |
0016a4cf PM |
2069 | |
2070 | case 47: /* stmw */ | |
c9f6f4ed | 2071 | op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); |
be96f633 PM |
2072 | op->ea = dform_ea(instr, regs); |
2073 | break; | |
0016a4cf | 2074 | |
cd64d169 | 2075 | #ifdef CONFIG_PPC_FPU |
0016a4cf PM |
2076 | case 48: /* lfs */ |
2077 | case 49: /* lfsu */ | |
be96f633 PM |
2078 | op->type = MKOP(LOAD_FP, u, 4); |
2079 | op->ea = dform_ea(instr, regs); | |
2080 | break; | |
0016a4cf PM |
2081 | |
2082 | case 50: /* lfd */ | |
2083 | case 51: /* lfdu */ | |
be96f633 PM |
2084 | op->type = MKOP(LOAD_FP, u, 8); |
2085 | op->ea = dform_ea(instr, regs); | |
2086 | break; | |
0016a4cf PM |
2087 | |
2088 | case 52: /* stfs */ | |
2089 | case 53: /* stfsu */ | |
be96f633 PM |
2090 | op->type = MKOP(STORE_FP, u, 4); |
2091 | op->ea = dform_ea(instr, regs); | |
2092 | break; | |
0016a4cf PM |
2093 | |
2094 | case 54: /* stfd */ | |
2095 | case 55: /* stfdu */ | |
be96f633 PM |
2096 | op->type = MKOP(STORE_FP, u, 8); |
2097 | op->ea = dform_ea(instr, regs); | |
2098 | break; | |
cd64d169 | 2099 | #endif |
0016a4cf | 2100 | |
350779a2 PM |
2101 | #ifdef __powerpc64__ |
2102 | case 56: /* lq */ | |
2103 | if (!((rd & 1) || (rd == ra))) | |
2104 | op->type = MKOP(LOAD, 0, 16); | |
2105 | op->ea = dqform_ea(instr, regs); | |
2106 | break; | |
2107 | #endif | |
2108 | ||
2109 | #ifdef CONFIG_VSX | |
2110 | case 57: /* lxsd, lxssp */ | |
2111 | op->ea = dsform_ea(instr, regs); | |
2112 | switch (instr & 3) { | |
2113 | case 2: /* lxsd */ | |
2114 | op->reg = rd + 32; | |
2115 | op->type = MKOP(LOAD_VSX, 0, 8); | |
2116 | op->element_size = 8; | |
2117 | op->vsx_flags = VSX_CHECK_VEC; | |
2118 | break; | |
2119 | case 3: /* lxssp */ | |
2120 | op->reg = rd + 32; | |
2121 | op->type = MKOP(LOAD_VSX, 0, 4); | |
2122 | op->element_size = 8; | |
2123 | op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; | |
2124 | break; | |
2125 | } | |
2126 | break; | |
2127 | #endif /* CONFIG_VSX */ | |
2128 | ||
0016a4cf PM |
2129 | #ifdef __powerpc64__ |
2130 | case 58: /* ld[u], lwa */ | |
be96f633 | 2131 | op->ea = dsform_ea(instr, regs); |
0016a4cf PM |
2132 | switch (instr & 3) { |
2133 | case 0: /* ld */ | |
be96f633 PM |
2134 | op->type = MKOP(LOAD, 0, 8); |
2135 | break; | |
0016a4cf | 2136 | case 1: /* ldu */ |
be96f633 PM |
2137 | op->type = MKOP(LOAD, UPDATE, 8); |
2138 | break; | |
0016a4cf | 2139 | case 2: /* lwa */ |
be96f633 PM |
2140 | op->type = MKOP(LOAD, SIGNEXT, 4); |
2141 | break; | |
0016a4cf PM |
2142 | } |
2143 | break; | |
350779a2 PM |
2144 | #endif |
2145 | ||
2146 | #ifdef CONFIG_VSX | |
2147 | case 61: /* lxv, stxsd, stxssp, stxv */ | |
2148 | switch (instr & 7) { | |
2149 | case 1: /* lxv */ | |
2150 | op->ea = dqform_ea(instr, regs); | |
2151 | if (instr & 8) | |
2152 | op->reg = rd + 32; | |
2153 | op->type = MKOP(LOAD_VSX, 0, 16); | |
2154 | op->element_size = 16; | |
2155 | op->vsx_flags = VSX_CHECK_VEC; | |
2156 | break; | |
2157 | ||
2158 | case 2: /* stxsd with LSB of DS field = 0 */ | |
2159 | case 6: /* stxsd with LSB of DS field = 1 */ | |
2160 | op->ea = dsform_ea(instr, regs); | |
2161 | op->reg = rd + 32; | |
2162 | op->type = MKOP(STORE_VSX, 0, 8); | |
2163 | op->element_size = 8; | |
2164 | op->vsx_flags = VSX_CHECK_VEC; | |
2165 | break; | |
2166 | ||
2167 | case 3: /* stxssp with LSB of DS field = 0 */ | |
2168 | case 7: /* stxssp with LSB of DS field = 1 */ | |
2169 | op->ea = dsform_ea(instr, regs); | |
2170 | op->reg = rd + 32; | |
2171 | op->type = MKOP(STORE_VSX, 0, 4); | |
2172 | op->element_size = 8; | |
2173 | op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; | |
2174 | break; | |
2175 | ||
2176 | case 5: /* stxv */ | |
2177 | op->ea = dqform_ea(instr, regs); | |
2178 | if (instr & 8) | |
2179 | op->reg = rd + 32; | |
2180 | op->type = MKOP(STORE_VSX, 0, 16); | |
2181 | op->element_size = 16; | |
2182 | op->vsx_flags = VSX_CHECK_VEC; | |
2183 | break; | |
2184 | } | |
2185 | break; | |
2186 | #endif /* CONFIG_VSX */ | |
0016a4cf | 2187 | |
350779a2 | 2188 | #ifdef __powerpc64__ |
0016a4cf | 2189 | case 62: /* std[u] */ |
be96f633 | 2190 | op->ea = dsform_ea(instr, regs); |
0016a4cf PM |
2191 | switch (instr & 3) { |
2192 | case 0: /* std */ | |
be96f633 PM |
2193 | op->type = MKOP(STORE, 0, 8); |
2194 | break; | |
0016a4cf | 2195 | case 1: /* stdu */ |
be96f633 PM |
2196 | op->type = MKOP(STORE, UPDATE, 8); |
2197 | break; | |
350779a2 PM |
2198 | case 2: /* stq */ |
2199 | if (!(rd & 1)) | |
2200 | op->type = MKOP(STORE, 0, 16); | |
2201 | break; | |
0016a4cf PM |
2202 | } |
2203 | break; | |
2204 | #endif /* __powerpc64__ */ | |
2205 | ||
2206 | } | |
be96f633 | 2207 | return 0; |
0016a4cf PM |
2208 | |
2209 | logical_done: | |
2210 | if (instr & 1) | |
3cdfcbfd PM |
2211 | set_cr0(regs, op, ra); |
2212 | logical_done_nocc: | |
2213 | op->reg = ra; | |
2214 | op->type |= SETREG; | |
2215 | return 1; | |
0016a4cf PM |
2216 | |
2217 | arith_done: | |
2218 | if (instr & 1) | |
3cdfcbfd PM |
2219 | set_cr0(regs, op, rd); |
2220 | compute_done: | |
2221 | op->reg = rd; | |
2222 | op->type |= SETREG; | |
be96f633 PM |
2223 | return 1; |
2224 | ||
2225 | priv: | |
2226 | op->type = INTERRUPT | 0x700; | |
2227 | op->val = SRR1_PROGPRIV; | |
2228 | return 0; | |
2229 | ||
cf87c3f6 PM |
2230 | trap: |
2231 | op->type = INTERRUPT | 0x700; | |
2232 | op->val = SRR1_PROGTRAP; | |
2233 | return 0; | |
be96f633 PM |
2234 | } |
2235 | EXPORT_SYMBOL_GPL(analyse_instr); | |
71f6e58e | 2236 | NOKPROBE_SYMBOL(analyse_instr); |
be96f633 PM |
2237 | |
2238 | /* | |
2239 | * For PPC32 we always use stwu with r1 to change the stack pointer. | |
2240 | * So this emulated store may corrupt the exception frame, now we | |
2241 | * have to provide the exception frame trampoline, which is pushed | |
2242 | * below the kprobed function stack. So we only update gpr[1] but | |
2243 | * don't emulate the real store operation. We will do real store | |
2244 | * operation safely in exception return code by checking this flag. | |
2245 | */ | |
71f6e58e | 2246 | static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs) |
be96f633 PM |
2247 | { |
2248 | #ifdef CONFIG_PPC32 | |
2249 | /* | |
2250 | * Check if we will touch kernel stack overflow | |
2251 | */ | |
2252 | if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) { | |
2253 | printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n"); | |
2254 | return -EINVAL; | |
2255 | } | |
2256 | #endif /* CONFIG_PPC32 */ | |
2257 | /* | |
2258 | * Check if we already set since that means we'll | |
2259 | * lose the previous value. | |
2260 | */ | |
2261 | WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE)); | |
2262 | set_thread_flag(TIF_EMULATE_STACK_STORE); | |
2263 | return 0; | |
2264 | } | |
2265 | ||
71f6e58e | 2266 | static nokprobe_inline void do_signext(unsigned long *valp, int size) |
be96f633 PM |
2267 | { |
2268 | switch (size) { | |
2269 | case 2: | |
2270 | *valp = (signed short) *valp; | |
2271 | break; | |
2272 | case 4: | |
2273 | *valp = (signed int) *valp; | |
2274 | break; | |
2275 | } | |
2276 | } | |
2277 | ||
71f6e58e | 2278 | static nokprobe_inline void do_byterev(unsigned long *valp, int size) |
be96f633 PM |
2279 | { |
2280 | switch (size) { | |
2281 | case 2: | |
2282 | *valp = byterev_2(*valp); | |
2283 | break; | |
2284 | case 4: | |
2285 | *valp = byterev_4(*valp); | |
2286 | break; | |
2287 | #ifdef __powerpc64__ | |
2288 | case 8: | |
2289 | *valp = byterev_8(*valp); | |
2290 | break; | |
2291 | #endif | |
2292 | } | |
2293 | } | |
2294 | ||
3cdfcbfd PM |
2295 | /* |
2296 | * Emulate an instruction that can be executed just by updating | |
2297 | * fields in *regs. | |
2298 | */ | |
2299 | void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) | |
2300 | { | |
2301 | unsigned long next_pc; | |
2302 | ||
2303 | next_pc = truncate_if_32bit(regs->msr, regs->nip + 4); | |
2304 | switch (op->type & INSTR_TYPE_MASK) { | |
2305 | case COMPUTE: | |
2306 | if (op->type & SETREG) | |
2307 | regs->gpr[op->reg] = op->val; | |
2308 | if (op->type & SETCC) | |
2309 | regs->ccr = op->ccval; | |
2310 | if (op->type & SETXER) | |
2311 | regs->xer = op->xerval; | |
2312 | break; | |
2313 | ||
2314 | case BRANCH: | |
2315 | if (op->type & SETLK) | |
2316 | regs->link = next_pc; | |
2317 | if (op->type & BRTAKEN) | |
2318 | next_pc = op->val; | |
2319 | if (op->type & DECCTR) | |
2320 | --regs->ctr; | |
2321 | break; | |
2322 | ||
2323 | case BARRIER: | |
2324 | switch (op->type & BARRIER_MASK) { | |
2325 | case BARRIER_SYNC: | |
2326 | mb(); | |
2327 | break; | |
2328 | case BARRIER_ISYNC: | |
2329 | isync(); | |
2330 | break; | |
2331 | case BARRIER_EIEIO: | |
2332 | eieio(); | |
2333 | break; | |
2334 | case BARRIER_LWSYNC: | |
2335 | asm volatile("lwsync" : : : "memory"); | |
2336 | break; | |
2337 | case BARRIER_PTESYNC: | |
2338 | asm volatile("ptesync" : : : "memory"); | |
2339 | break; | |
2340 | } | |
2341 | break; | |
2342 | ||
2343 | case MFSPR: | |
2344 | switch (op->spr) { | |
2345 | case SPRN_XER: | |
2346 | regs->gpr[op->reg] = regs->xer & 0xffffffffUL; | |
2347 | break; | |
2348 | case SPRN_LR: | |
2349 | regs->gpr[op->reg] = regs->link; | |
2350 | break; | |
2351 | case SPRN_CTR: | |
2352 | regs->gpr[op->reg] = regs->ctr; | |
2353 | break; | |
2354 | default: | |
2355 | WARN_ON_ONCE(1); | |
2356 | } | |
2357 | break; | |
2358 | ||
2359 | case MTSPR: | |
2360 | switch (op->spr) { | |
2361 | case SPRN_XER: | |
2362 | regs->xer = op->val & 0xffffffffUL; | |
2363 | break; | |
2364 | case SPRN_LR: | |
2365 | regs->link = op->val; | |
2366 | break; | |
2367 | case SPRN_CTR: | |
2368 | regs->ctr = op->val; | |
2369 | break; | |
2370 | default: | |
2371 | WARN_ON_ONCE(1); | |
2372 | } | |
2373 | break; | |
2374 | ||
2375 | default: | |
2376 | WARN_ON_ONCE(1); | |
2377 | } | |
2378 | regs->nip = next_pc; | |
2379 | } | |
2380 | ||
be96f633 PM |
2381 | /* |
2382 | * Emulate instructions that cause a transfer of control, | |
2383 | * loads and stores, and a few other instructions. | |
2384 | * Returns 1 if the step was emulated, 0 if not, | |
2385 | * or -1 if the instruction is one that should not be stepped, | |
2386 | * such as an rfid, or a mtmsrd that would clear MSR_RI. | |
2387 | */ | |
71f6e58e | 2388 | int emulate_step(struct pt_regs *regs, unsigned int instr) |
be96f633 PM |
2389 | { |
2390 | struct instruction_op op; | |
d120cdbc | 2391 | int r, err, size, type; |
be96f633 PM |
2392 | unsigned long val; |
2393 | unsigned int cr; | |
c9f6f4ed | 2394 | int i, rd, nb; |
d120cdbc | 2395 | unsigned long ea; |
be96f633 PM |
2396 | |
2397 | r = analyse_instr(&op, regs, instr); | |
3cdfcbfd | 2398 | if (r < 0) |
be96f633 | 2399 | return r; |
3cdfcbfd PM |
2400 | if (r > 0) { |
2401 | emulate_update_regs(regs, &op); | |
2402 | return 1; | |
2403 | } | |
be96f633 PM |
2404 | |
2405 | err = 0; | |
2406 | size = GETSIZE(op.type); | |
d120cdbc PM |
2407 | type = op.type & INSTR_TYPE_MASK; |
2408 | ||
2409 | ea = op.ea; | |
2410 | if (OP_IS_LOAD_STORE(type) || type == CACHEOP) | |
2411 | ea = truncate_if_32bit(regs->msr, op.ea); | |
2412 | ||
2413 | switch (type) { | |
be96f633 | 2414 | case CACHEOP: |
d120cdbc | 2415 | if (!address_ok(regs, ea, 8)) |
be96f633 PM |
2416 | return 0; |
2417 | switch (op.type & CACHEOP_MASK) { | |
2418 | case DCBST: | |
d120cdbc | 2419 | __cacheop_user_asmx(ea, err, "dcbst"); |
be96f633 PM |
2420 | break; |
2421 | case DCBF: | |
d120cdbc | 2422 | __cacheop_user_asmx(ea, err, "dcbf"); |
be96f633 PM |
2423 | break; |
2424 | case DCBTST: | |
2425 | if (op.reg == 0) | |
d120cdbc | 2426 | prefetchw((void *) ea); |
be96f633 PM |
2427 | break; |
2428 | case DCBT: | |
2429 | if (op.reg == 0) | |
d120cdbc | 2430 | prefetch((void *) ea); |
be96f633 | 2431 | break; |
cf87c3f6 | 2432 | case ICBI: |
d120cdbc | 2433 | __cacheop_user_asmx(ea, err, "icbi"); |
cf87c3f6 | 2434 | break; |
be96f633 PM |
2435 | } |
2436 | if (err) | |
2437 | return 0; | |
2438 | goto instr_done; | |
2439 | ||
2440 | case LARX: | |
d120cdbc | 2441 | if (ea & (size - 1)) |
be96f633 | 2442 | break; /* can't handle misaligned */ |
d120cdbc | 2443 | if (!address_ok(regs, ea, size)) |
3c4b66a6 | 2444 | return 0; |
be96f633 PM |
2445 | err = 0; |
2446 | switch (size) { | |
350779a2 PM |
2447 | #ifdef __powerpc64__ |
2448 | case 1: | |
d120cdbc | 2449 | __get_user_asmx(val, ea, err, "lbarx"); |
350779a2 PM |
2450 | break; |
2451 | case 2: | |
d120cdbc | 2452 | __get_user_asmx(val, ea, err, "lharx"); |
350779a2 PM |
2453 | break; |
2454 | #endif | |
be96f633 | 2455 | case 4: |
d120cdbc | 2456 | __get_user_asmx(val, ea, err, "lwarx"); |
be96f633 | 2457 | break; |
dd217310 | 2458 | #ifdef __powerpc64__ |
be96f633 | 2459 | case 8: |
d120cdbc | 2460 | __get_user_asmx(val, ea, err, "ldarx"); |
be96f633 | 2461 | break; |
350779a2 | 2462 | case 16: |
d120cdbc | 2463 | err = do_lqarx(ea, ®s->gpr[op.reg]); |
350779a2 | 2464 | goto ldst_done; |
dd217310 | 2465 | #endif |
be96f633 PM |
2466 | default: |
2467 | return 0; | |
2468 | } | |
2469 | if (!err) | |
2470 | regs->gpr[op.reg] = val; | |
2471 | goto ldst_done; | |
2472 | ||
2473 | case STCX: | |
d120cdbc | 2474 | if (ea & (size - 1)) |
be96f633 | 2475 | break; /* can't handle misaligned */ |
d120cdbc | 2476 | if (!address_ok(regs, ea, size)) |
3c4b66a6 | 2477 | return 0; |
be96f633 PM |
2478 | err = 0; |
2479 | switch (size) { | |
350779a2 PM |
2480 | #ifdef __powerpc64__ |
2481 | case 1: | |
d120cdbc | 2482 | __put_user_asmx(op.val, ea, err, "stbcx.", cr); |
350779a2 PM |
2483 | break; |
2484 | case 2: | |
d120cdbc | 2485 | __put_user_asmx(op.val, ea, err, "stbcx.", cr); |
350779a2 PM |
2486 | break; |
2487 | #endif | |
be96f633 | 2488 | case 4: |
d120cdbc | 2489 | __put_user_asmx(op.val, ea, err, "stwcx.", cr); |
be96f633 | 2490 | break; |
dd217310 | 2491 | #ifdef __powerpc64__ |
be96f633 | 2492 | case 8: |
d120cdbc | 2493 | __put_user_asmx(op.val, ea, err, "stdcx.", cr); |
be96f633 | 2494 | break; |
350779a2 | 2495 | case 16: |
d120cdbc | 2496 | err = do_stqcx(ea, regs->gpr[op.reg], |
350779a2 PM |
2497 | regs->gpr[op.reg + 1], &cr); |
2498 | break; | |
dd217310 | 2499 | #endif |
be96f633 PM |
2500 | default: |
2501 | return 0; | |
2502 | } | |
2503 | if (!err) | |
2504 | regs->ccr = (regs->ccr & 0x0fffffff) | | |
2505 | (cr & 0xe0000000) | | |
2506 | ((regs->xer >> 3) & 0x10000000); | |
2507 | goto ldst_done; | |
2508 | ||
2509 | case LOAD: | |
350779a2 PM |
2510 | #ifdef __powerpc64__ |
2511 | if (size == 16) { | |
d120cdbc | 2512 | err = emulate_lq(regs, ea, op.reg); |
350779a2 PM |
2513 | goto ldst_done; |
2514 | } | |
2515 | #endif | |
d120cdbc | 2516 | err = read_mem(®s->gpr[op.reg], ea, size, regs); |
be96f633 PM |
2517 | if (!err) { |
2518 | if (op.type & SIGNEXT) | |
2519 | do_signext(®s->gpr[op.reg], size); | |
2520 | if (op.type & BYTEREV) | |
2521 | do_byterev(®s->gpr[op.reg], size); | |
2522 | } | |
2523 | goto ldst_done; | |
2524 | ||
7048c846 | 2525 | #ifdef CONFIG_PPC_FPU |
be96f633 | 2526 | case LOAD_FP: |
ee0a54d7 PM |
2527 | if (!(regs->msr & MSR_FP)) |
2528 | return 0; | |
be96f633 | 2529 | if (size == 4) |
d120cdbc | 2530 | err = do_fp_load(op.reg, do_lfs, ea, size, regs); |
be96f633 | 2531 | else |
d120cdbc | 2532 | err = do_fp_load(op.reg, do_lfd, ea, size, regs); |
be96f633 | 2533 | goto ldst_done; |
7048c846 | 2534 | #endif |
be96f633 PM |
2535 | #ifdef CONFIG_ALTIVEC |
2536 | case LOAD_VMX: | |
ee0a54d7 PM |
2537 | if (!(regs->msr & MSR_VEC)) |
2538 | return 0; | |
d120cdbc | 2539 | err = do_vec_load(op.reg, do_lvx, ea, regs); |
be96f633 PM |
2540 | goto ldst_done; |
2541 | #endif | |
2542 | #ifdef CONFIG_VSX | |
350779a2 | 2543 | case LOAD_VSX: { |
e0a0986b | 2544 | u8 mem[16]; |
350779a2 PM |
2545 | union vsx_reg buf; |
2546 | unsigned long msrbit = MSR_VSX; | |
2547 | ||
2548 | /* | |
2549 | * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX | |
2550 | * when the target of the instruction is a vector register. | |
2551 | */ | |
2552 | if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC)) | |
2553 | msrbit = MSR_VEC; | |
2554 | if (!(regs->msr & msrbit)) | |
ee0a54d7 | 2555 | return 0; |
d120cdbc | 2556 | if (!address_ok(regs, ea, size) || |
e0a0986b | 2557 | copy_mem_in(mem, ea, size)) |
350779a2 PM |
2558 | return 0; |
2559 | ||
2560 | emulate_vsx_load(&op, &buf, mem); | |
2561 | load_vsrn(op.reg, &buf); | |
be96f633 | 2562 | goto ldst_done; |
350779a2 | 2563 | } |
be96f633 PM |
2564 | #endif |
2565 | case LOAD_MULTI: | |
2566 | if (regs->msr & MSR_LE) | |
2567 | return 0; | |
2568 | rd = op.reg; | |
c9f6f4ed PM |
2569 | for (i = 0; i < size; i += 4) { |
2570 | nb = size - i; | |
2571 | if (nb > 4) | |
2572 | nb = 4; | |
d120cdbc | 2573 | err = read_mem(®s->gpr[rd], ea, nb, regs); |
be96f633 PM |
2574 | if (err) |
2575 | return 0; | |
c9f6f4ed PM |
2576 | if (nb < 4) /* left-justify last bytes */ |
2577 | regs->gpr[rd] <<= 32 - 8 * nb; | |
d120cdbc | 2578 | ea += 4; |
c9f6f4ed PM |
2579 | ++rd; |
2580 | } | |
be96f633 PM |
2581 | goto instr_done; |
2582 | ||
2583 | case STORE: | |
350779a2 PM |
2584 | #ifdef __powerpc64__ |
2585 | if (size == 16) { | |
d120cdbc | 2586 | err = emulate_stq(regs, ea, op.reg); |
350779a2 PM |
2587 | goto ldst_done; |
2588 | } | |
2589 | #endif | |
be96f633 PM |
2590 | if ((op.type & UPDATE) && size == sizeof(long) && |
2591 | op.reg == 1 && op.update_reg == 1 && | |
2592 | !(regs->msr & MSR_PR) && | |
d120cdbc PM |
2593 | ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { |
2594 | err = handle_stack_update(ea, regs); | |
be96f633 PM |
2595 | goto ldst_done; |
2596 | } | |
d120cdbc | 2597 | err = write_mem(op.val, ea, size, regs); |
be96f633 PM |
2598 | goto ldst_done; |
2599 | ||
7048c846 | 2600 | #ifdef CONFIG_PPC_FPU |
be96f633 | 2601 | case STORE_FP: |
ee0a54d7 PM |
2602 | if (!(regs->msr & MSR_FP)) |
2603 | return 0; | |
be96f633 | 2604 | if (size == 4) |
d120cdbc | 2605 | err = do_fp_store(op.reg, do_stfs, ea, size, regs); |
be96f633 | 2606 | else |
d120cdbc | 2607 | err = do_fp_store(op.reg, do_stfd, ea, size, regs); |
be96f633 | 2608 | goto ldst_done; |
7048c846 | 2609 | #endif |
be96f633 PM |
2610 | #ifdef CONFIG_ALTIVEC |
2611 | case STORE_VMX: | |
ee0a54d7 PM |
2612 | if (!(regs->msr & MSR_VEC)) |
2613 | return 0; | |
d120cdbc | 2614 | err = do_vec_store(op.reg, do_stvx, ea, regs); |
be96f633 PM |
2615 | goto ldst_done; |
2616 | #endif | |
2617 | #ifdef CONFIG_VSX | |
350779a2 | 2618 | case STORE_VSX: { |
e0a0986b | 2619 | u8 mem[16]; |
350779a2 PM |
2620 | union vsx_reg buf; |
2621 | unsigned long msrbit = MSR_VSX; | |
2622 | ||
2623 | /* | |
2624 | * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX | |
2625 | * when the target of the instruction is a vector register. | |
2626 | */ | |
2627 | if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC)) | |
2628 | msrbit = MSR_VEC; | |
2629 | if (!(regs->msr & msrbit)) | |
2630 | return 0; | |
d120cdbc | 2631 | if (!address_ok(regs, ea, size)) |
350779a2 PM |
2632 | return 0; |
2633 | ||
2634 | store_vsrn(op.reg, &buf); | |
2635 | emulate_vsx_store(&op, &buf, mem); | |
e0a0986b | 2636 | if (copy_mem_out(mem, ea, size)) |
ee0a54d7 | 2637 | return 0; |
be96f633 | 2638 | goto ldst_done; |
350779a2 | 2639 | } |
be96f633 PM |
2640 | #endif |
2641 | case STORE_MULTI: | |
2642 | if (regs->msr & MSR_LE) | |
2643 | return 0; | |
2644 | rd = op.reg; | |
c9f6f4ed PM |
2645 | for (i = 0; i < size; i += 4) { |
2646 | val = regs->gpr[rd]; | |
2647 | nb = size - i; | |
2648 | if (nb > 4) | |
2649 | nb = 4; | |
2650 | else | |
2651 | val >>= 32 - 8 * nb; | |
d120cdbc | 2652 | err = write_mem(val, ea, nb, regs); |
be96f633 PM |
2653 | if (err) |
2654 | return 0; | |
d120cdbc | 2655 | ea += 4; |
c9f6f4ed PM |
2656 | ++rd; |
2657 | } | |
be96f633 PM |
2658 | goto instr_done; |
2659 | ||
2660 | case MFMSR: | |
2661 | regs->gpr[op.reg] = regs->msr & MSR_MASK; | |
2662 | goto instr_done; | |
2663 | ||
2664 | case MTMSR: | |
2665 | val = regs->gpr[op.reg]; | |
2666 | if ((val & MSR_RI) == 0) | |
2667 | /* can't step mtmsr[d] that would clear MSR_RI */ | |
2668 | return -1; | |
2669 | /* here op.val is the mask of bits to change */ | |
2670 | regs->msr = (regs->msr & ~op.val) | (val & op.val); | |
2671 | goto instr_done; | |
2672 | ||
2673 | #ifdef CONFIG_PPC64 | |
2674 | case SYSCALL: /* sc */ | |
2675 | /* | |
2676 | * N.B. this uses knowledge about how the syscall | |
2677 | * entry code works. If that is changed, this will | |
2678 | * need to be changed also. | |
2679 | */ | |
2680 | if (regs->gpr[0] == 0x1ebe && | |
2681 | cpu_has_feature(CPU_FTR_REAL_LE)) { | |
2682 | regs->msr ^= MSR_LE; | |
2683 | goto instr_done; | |
2684 | } | |
2685 | regs->gpr[9] = regs->gpr[13]; | |
2686 | regs->gpr[10] = MSR_KERNEL; | |
2687 | regs->gpr[11] = regs->nip + 4; | |
2688 | regs->gpr[12] = regs->msr & MSR_MASK; | |
2689 | regs->gpr[13] = (unsigned long) get_paca(); | |
2690 | regs->nip = (unsigned long) &system_call_common; | |
2691 | regs->msr = MSR_KERNEL; | |
2692 | return 1; | |
2693 | ||
2694 | case RFI: | |
2695 | return -1; | |
2696 | #endif | |
2697 | } | |
2698 | return 0; | |
2699 | ||
2700 | ldst_done: | |
2701 | if (err) | |
2702 | return 0; | |
2703 | if (op.type & UPDATE) | |
2704 | regs->gpr[op.update_reg] = op.ea; | |
2705 | ||
2706 | instr_done: | |
2707 | regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); | |
2708 | return 1; | |
14cf11af | 2709 | } |
71f6e58e | 2710 | NOKPROBE_SYMBOL(emulate_step); |