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d30f6e48 SW |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
16 | * | |
17 | * Author: Varun Sethi <varun.sethi@freescale.com> | |
18 | * Author: Scott Wood <scotwood@freescale.com> | |
19 | * | |
20 | * This file is derived from arch/powerpc/kvm/booke_interrupts.S | |
21 | */ | |
22 | ||
23 | #include <asm/ppc_asm.h> | |
24 | #include <asm/kvm_asm.h> | |
25 | #include <asm/reg.h> | |
26 | #include <asm/mmu-44x.h> | |
27 | #include <asm/page.h> | |
28 | #include <asm/asm-compat.h> | |
29 | #include <asm/asm-offsets.h> | |
30 | #include <asm/bitsperlong.h> | |
1d628af7 | 31 | #include <asm/thread_info.h> |
d30f6e48 SW |
32 | |
33 | #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */ | |
34 | ||
35 | #define GET_VCPU(vcpu, thread) \ | |
36 | PPC_LL vcpu, THREAD_KVM_VCPU(thread) | |
37 | ||
d30f6e48 SW |
38 | #define LONGBYTES (BITS_PER_LONG / 8) |
39 | ||
40 | #define VCPU_GPR(n) (VCPU_GPRS + (n * LONGBYTES)) | |
41 | #define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES)) | |
42 | ||
43 | /* The host stack layout: */ | |
44 | #define HOST_R1 (0 * LONGBYTES) /* Implied by stwu. */ | |
45 | #define HOST_CALLEE_LR (1 * LONGBYTES) | |
46 | #define HOST_RUN (2 * LONGBYTES) /* struct kvm_run */ | |
47 | /* | |
48 | * r2 is special: it holds 'current', and it made nonvolatile in the | |
49 | * kernel with the -ffixed-r2 gcc option. | |
50 | */ | |
51 | #define HOST_R2 (3 * LONGBYTES) | |
f6127716 AG |
52 | #define HOST_CR (4 * LONGBYTES) |
53 | #define HOST_NV_GPRS (5 * LONGBYTES) | |
d30f6e48 SW |
54 | #define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES)) |
55 | #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES) | |
56 | #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */ | |
57 | #define HOST_STACK_LR (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */ | |
58 | ||
59 | #define NEED_EMU 0x00000001 /* emulation -- save nv regs */ | |
60 | #define NEED_DEAR 0x00000002 /* save faulting DEAR */ | |
61 | #define NEED_ESR 0x00000004 /* save faulting ESR */ | |
62 | ||
63 | /* | |
64 | * On entry: | |
65 | * r4 = vcpu, r5 = srr0, r6 = srr1 | |
66 | * saved in vcpu: cr, ctr, r3-r13 | |
67 | */ | |
68 | .macro kvm_handler_common intno, srr0, flags | |
a2723ce7 AG |
69 | /* Restore host stack pointer */ |
70 | PPC_STL r1, VCPU_GPR(r1)(r4) | |
71 | PPC_STL r2, VCPU_GPR(r2)(r4) | |
72 | PPC_LL r1, VCPU_HOST_STACK(r4) | |
73 | PPC_LL r2, HOST_R2(r1) | |
74 | ||
d30f6e48 SW |
75 | mfspr r10, SPRN_PID |
76 | lwz r8, VCPU_HOST_PID(r4) | |
77 | PPC_LL r11, VCPU_SHARED(r4) | |
78 | PPC_STL r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */ | |
79 | li r14, \intno | |
80 | ||
81 | stw r10, VCPU_GUEST_PID(r4) | |
82 | mtspr SPRN_PID, r8 | |
83 | ||
d30f6e48 SW |
84 | #ifdef CONFIG_KVM_EXIT_TIMING |
85 | /* save exit time */ | |
86 | 1: mfspr r7, SPRN_TBRU | |
87 | mfspr r8, SPRN_TBRL | |
88 | mfspr r9, SPRN_TBRU | |
89 | cmpw r9, r7 | |
90 | PPC_STL r8, VCPU_TIMING_EXIT_TBL(r4) | |
91 | bne- 1b | |
92 | PPC_STL r9, VCPU_TIMING_EXIT_TBU(r4) | |
93 | #endif | |
94 | ||
95 | oris r8, r6, MSR_CE@h | |
185e4188 | 96 | PPC_STD(r6, VCPU_SHARED_MSR, r11) |
d30f6e48 SW |
97 | ori r8, r8, MSR_ME | MSR_RI |
98 | PPC_STL r5, VCPU_PC(r4) | |
99 | ||
100 | /* | |
101 | * Make sure CE/ME/RI are set (if appropriate for exception type) | |
102 | * whether or not the guest had it set. Since mfmsr/mtmsr are | |
103 | * somewhat expensive, skip in the common case where the guest | |
104 | * had all these bits set (and thus they're still set if | |
105 | * appropriate for the exception type). | |
106 | */ | |
107 | cmpw r6, r8 | |
d30f6e48 SW |
108 | beq 1f |
109 | mfmsr r7 | |
110 | .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0 | |
111 | oris r7, r7, MSR_CE@h | |
112 | .endif | |
113 | .if \srr0 != SPRN_MCSRR0 | |
114 | ori r7, r7, MSR_ME | MSR_RI | |
115 | .endif | |
116 | mtmsr r7 | |
117 | 1: | |
118 | ||
119 | .if \flags & NEED_EMU | |
120 | /* | |
121 | * This assumes you have external PID support. | |
122 | * To support a bookehv CPU without external PID, you'll | |
123 | * need to look up the TLB entry and create a temporary mapping. | |
124 | * | |
125 | * FIXME: we don't currently handle if the lwepx faults. PR-mode | |
126 | * booke doesn't handle it either. Since Linux doesn't use | |
127 | * broadcast tlbivax anymore, the only way this should happen is | |
128 | * if the guest maps its memory execute-but-not-read, or if we | |
129 | * somehow take a TLB miss in the middle of this entry code and | |
130 | * evict the relevant entry. On e500mc, all kernel lowmem is | |
131 | * bolted into TLB1 large page mappings, and we don't use | |
132 | * broadcast invalidates, so we should not take a TLB miss here. | |
133 | * | |
134 | * Later we'll need to deal with faults here. Disallowing guest | |
135 | * mappings that are execute-but-not-read could be an option on | |
136 | * e500mc, but not on chips with an LRAT if it is used. | |
137 | */ | |
138 | ||
139 | mfspr r3, SPRN_EPLC /* will already have correct ELPID and EGS */ | |
140 | PPC_STL r15, VCPU_GPR(r15)(r4) | |
141 | PPC_STL r16, VCPU_GPR(r16)(r4) | |
142 | PPC_STL r17, VCPU_GPR(r17)(r4) | |
143 | PPC_STL r18, VCPU_GPR(r18)(r4) | |
144 | PPC_STL r19, VCPU_GPR(r19)(r4) | |
145 | mr r8, r3 | |
146 | PPC_STL r20, VCPU_GPR(r20)(r4) | |
147 | rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS | |
148 | PPC_STL r21, VCPU_GPR(r21)(r4) | |
149 | rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR | |
150 | PPC_STL r22, VCPU_GPR(r22)(r4) | |
151 | rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID | |
152 | PPC_STL r23, VCPU_GPR(r23)(r4) | |
153 | PPC_STL r24, VCPU_GPR(r24)(r4) | |
154 | PPC_STL r25, VCPU_GPR(r25)(r4) | |
155 | PPC_STL r26, VCPU_GPR(r26)(r4) | |
156 | PPC_STL r27, VCPU_GPR(r27)(r4) | |
157 | PPC_STL r28, VCPU_GPR(r28)(r4) | |
158 | PPC_STL r29, VCPU_GPR(r29)(r4) | |
159 | PPC_STL r30, VCPU_GPR(r30)(r4) | |
160 | PPC_STL r31, VCPU_GPR(r31)(r4) | |
161 | mtspr SPRN_EPLC, r8 | |
1d628af7 AG |
162 | |
163 | /* disable preemption, so we are sure we hit the fixup handler */ | |
164 | #ifdef CONFIG_PPC64 | |
165 | clrrdi r8,r1,THREAD_SHIFT | |
166 | #else | |
167 | rlwinm r8,r1,0,0,31-THREAD_SHIFT /* current thread_info */ | |
168 | #endif | |
169 | li r7, 1 | |
170 | stw r7, TI_PREEMPT(r8) | |
171 | ||
d30f6e48 | 172 | isync |
1d628af7 AG |
173 | |
174 | /* | |
175 | * In case the read goes wrong, we catch it and write an invalid value | |
176 | * in LAST_INST instead. | |
177 | */ | |
178 | 1: lwepx r9, 0, r5 | |
179 | 2: | |
180 | .section .fixup, "ax" | |
181 | 3: li r9, KVM_INST_FETCH_FAILED | |
182 | b 2b | |
183 | .previous | |
184 | .section __ex_table,"a" | |
185 | PPC_LONG_ALIGN | |
186 | PPC_LONG 1b,3b | |
187 | .previous | |
188 | ||
d30f6e48 | 189 | mtspr SPRN_EPLC, r3 |
1d628af7 AG |
190 | li r7, 0 |
191 | stw r7, TI_PREEMPT(r8) | |
d30f6e48 SW |
192 | stw r9, VCPU_LAST_INST(r4) |
193 | .endif | |
194 | ||
195 | .if \flags & NEED_ESR | |
196 | mfspr r8, SPRN_ESR | |
197 | PPC_STL r8, VCPU_FAULT_ESR(r4) | |
198 | .endif | |
199 | ||
200 | .if \flags & NEED_DEAR | |
201 | mfspr r9, SPRN_DEAR | |
202 | PPC_STL r9, VCPU_FAULT_DEAR(r4) | |
203 | .endif | |
204 | ||
205 | b kvmppc_resume_host | |
206 | .endm | |
207 | ||
208 | /* | |
209 | * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h | |
210 | */ | |
211 | .macro kvm_handler intno srr0, srr1, flags | |
212 | _GLOBAL(kvmppc_handler_\intno\()_\srr1) | |
213 | GET_VCPU(r11, r10) | |
214 | PPC_STL r3, VCPU_GPR(r3)(r11) | |
215 | mfspr r3, SPRN_SPRG_RSCRATCH0 | |
216 | PPC_STL r4, VCPU_GPR(r4)(r11) | |
217 | PPC_LL r4, THREAD_NORMSAVE(0)(r10) | |
218 | PPC_STL r5, VCPU_GPR(r5)(r11) | |
219 | PPC_STL r13, VCPU_CR(r11) | |
220 | mfspr r5, \srr0 | |
221 | PPC_STL r3, VCPU_GPR(r10)(r11) | |
222 | PPC_LL r3, THREAD_NORMSAVE(2)(r10) | |
223 | PPC_STL r6, VCPU_GPR(r6)(r11) | |
224 | PPC_STL r4, VCPU_GPR(r11)(r11) | |
225 | mfspr r6, \srr1 | |
226 | PPC_STL r7, VCPU_GPR(r7)(r11) | |
227 | PPC_STL r8, VCPU_GPR(r8)(r11) | |
228 | PPC_STL r9, VCPU_GPR(r9)(r11) | |
229 | PPC_STL r3, VCPU_GPR(r13)(r11) | |
230 | mfctr r7 | |
231 | PPC_STL r12, VCPU_GPR(r12)(r11) | |
232 | PPC_STL r7, VCPU_CTR(r11) | |
233 | mr r4, r11 | |
234 | kvm_handler_common \intno, \srr0, \flags | |
235 | .endm | |
236 | ||
237 | .macro kvm_lvl_handler intno scratch srr0, srr1, flags | |
238 | _GLOBAL(kvmppc_handler_\intno\()_\srr1) | |
239 | mfspr r10, SPRN_SPRG_THREAD | |
240 | GET_VCPU(r11, r10) | |
241 | PPC_STL r3, VCPU_GPR(r3)(r11) | |
242 | mfspr r3, \scratch | |
243 | PPC_STL r4, VCPU_GPR(r4)(r11) | |
244 | PPC_LL r4, GPR9(r8) | |
245 | PPC_STL r5, VCPU_GPR(r5)(r11) | |
246 | PPC_STL r9, VCPU_CR(r11) | |
247 | mfspr r5, \srr0 | |
248 | PPC_STL r3, VCPU_GPR(r8)(r11) | |
249 | PPC_LL r3, GPR10(r8) | |
250 | PPC_STL r6, VCPU_GPR(r6)(r11) | |
251 | PPC_STL r4, VCPU_GPR(r9)(r11) | |
252 | mfspr r6, \srr1 | |
253 | PPC_LL r4, GPR11(r8) | |
254 | PPC_STL r7, VCPU_GPR(r7)(r11) | |
255 | PPC_STL r8, VCPU_GPR(r8)(r11) | |
256 | PPC_STL r3, VCPU_GPR(r10)(r11) | |
257 | mfctr r7 | |
258 | PPC_STL r12, VCPU_GPR(r12)(r11) | |
259 | PPC_STL r4, VCPU_GPR(r11)(r11) | |
260 | PPC_STL r7, VCPU_CTR(r11) | |
261 | mr r4, r11 | |
262 | kvm_handler_common \intno, \srr0, \flags | |
263 | .endm | |
264 | ||
265 | kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \ | |
266 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
267 | kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \ | |
268 | SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0 | |
269 | kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \ | |
270 | SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR) | |
271 | kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR | |
272 | kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0 | |
273 | kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \ | |
274 | SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR) | |
275 | kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR | |
276 | kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 | |
277 | kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0 | |
278 | kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 | |
279 | kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0 | |
280 | kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0 | |
281 | kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \ | |
282 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
283 | kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \ | |
284 | SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR) | |
285 | kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0 | |
286 | kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 | |
287 | kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0 | |
288 | kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0 | |
289 | kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0 | |
290 | kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0 | |
291 | kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \ | |
292 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
293 | kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU | |
294 | kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0 | |
295 | kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0 | |
296 | kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \ | |
297 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
298 | kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \ | |
299 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
300 | kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \ | |
301 | SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0 | |
302 | ||
303 | ||
304 | /* Registers: | |
305 | * SPRG_SCRATCH0: guest r10 | |
306 | * r4: vcpu pointer | |
307 | * r11: vcpu->arch.shared | |
308 | * r14: KVM exit number | |
309 | */ | |
310 | _GLOBAL(kvmppc_resume_host) | |
311 | /* Save remaining volatile guest register state to vcpu. */ | |
312 | mfspr r3, SPRN_VRSAVE | |
313 | PPC_STL r0, VCPU_GPR(r0)(r4) | |
d30f6e48 SW |
314 | mflr r5 |
315 | mfspr r6, SPRN_SPRG4 | |
d30f6e48 SW |
316 | PPC_STL r5, VCPU_LR(r4) |
317 | mfspr r7, SPRN_SPRG5 | |
318 | PPC_STL r3, VCPU_VRSAVE(r4) | |
30124906 | 319 | PPC_STD(r6, VCPU_SHARED_SPRG4, r11) |
d30f6e48 | 320 | mfspr r8, SPRN_SPRG6 |
30124906 | 321 | PPC_STD(r7, VCPU_SHARED_SPRG5, r11) |
d30f6e48 | 322 | mfspr r9, SPRN_SPRG7 |
30124906 | 323 | PPC_STD(r8, VCPU_SHARED_SPRG6, r11) |
d30f6e48 | 324 | mfxer r3 |
30124906 | 325 | PPC_STD(r9, VCPU_SHARED_SPRG7, r11) |
d30f6e48 SW |
326 | |
327 | /* save guest MAS registers and restore host mas4 & mas6 */ | |
328 | mfspr r5, SPRN_MAS0 | |
329 | PPC_STL r3, VCPU_XER(r4) | |
330 | mfspr r6, SPRN_MAS1 | |
331 | stw r5, VCPU_SHARED_MAS0(r11) | |
332 | mfspr r7, SPRN_MAS2 | |
333 | stw r6, VCPU_SHARED_MAS1(r11) | |
185e4188 | 334 | PPC_STD(r7, VCPU_SHARED_MAS2, r11) |
d30f6e48 SW |
335 | mfspr r5, SPRN_MAS3 |
336 | mfspr r6, SPRN_MAS4 | |
337 | stw r5, VCPU_SHARED_MAS7_3+4(r11) | |
338 | mfspr r7, SPRN_MAS6 | |
339 | stw r6, VCPU_SHARED_MAS4(r11) | |
340 | mfspr r5, SPRN_MAS7 | |
341 | lwz r6, VCPU_HOST_MAS4(r4) | |
342 | stw r7, VCPU_SHARED_MAS6(r11) | |
343 | lwz r8, VCPU_HOST_MAS6(r4) | |
344 | mtspr SPRN_MAS4, r6 | |
345 | stw r5, VCPU_SHARED_MAS7_3+0(r11) | |
346 | mtspr SPRN_MAS6, r8 | |
e9ba39c1 | 347 | /* Enable MAS register updates via exception */ |
d30f6e48 SW |
348 | mfspr r3, SPRN_EPCR |
349 | rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH | |
350 | mtspr SPRN_EPCR, r3 | |
351 | isync | |
352 | ||
d30f6e48 SW |
353 | /* Switch to kernel stack and jump to handler. */ |
354 | PPC_LL r3, HOST_RUN(r1) | |
355 | mr r5, r14 /* intno */ | |
356 | mr r14, r4 /* Save vcpu pointer. */ | |
357 | bl kvmppc_handle_exit | |
358 | ||
359 | /* Restore vcpu pointer and the nonvolatiles we used. */ | |
360 | mr r4, r14 | |
361 | PPC_LL r14, VCPU_GPR(r14)(r4) | |
362 | ||
363 | andi. r5, r3, RESUME_FLAG_NV | |
364 | beq skip_nv_load | |
365 | PPC_LL r15, VCPU_GPR(r15)(r4) | |
366 | PPC_LL r16, VCPU_GPR(r16)(r4) | |
367 | PPC_LL r17, VCPU_GPR(r17)(r4) | |
368 | PPC_LL r18, VCPU_GPR(r18)(r4) | |
369 | PPC_LL r19, VCPU_GPR(r19)(r4) | |
370 | PPC_LL r20, VCPU_GPR(r20)(r4) | |
371 | PPC_LL r21, VCPU_GPR(r21)(r4) | |
372 | PPC_LL r22, VCPU_GPR(r22)(r4) | |
373 | PPC_LL r23, VCPU_GPR(r23)(r4) | |
374 | PPC_LL r24, VCPU_GPR(r24)(r4) | |
375 | PPC_LL r25, VCPU_GPR(r25)(r4) | |
376 | PPC_LL r26, VCPU_GPR(r26)(r4) | |
377 | PPC_LL r27, VCPU_GPR(r27)(r4) | |
378 | PPC_LL r28, VCPU_GPR(r28)(r4) | |
379 | PPC_LL r29, VCPU_GPR(r29)(r4) | |
380 | PPC_LL r30, VCPU_GPR(r30)(r4) | |
381 | PPC_LL r31, VCPU_GPR(r31)(r4) | |
382 | skip_nv_load: | |
383 | /* Should we return to the guest? */ | |
384 | andi. r5, r3, RESUME_FLAG_HOST | |
385 | beq lightweight_exit | |
386 | ||
387 | srawi r3, r3, 2 /* Shift -ERR back down. */ | |
388 | ||
389 | heavyweight_exit: | |
390 | /* Not returning to guest. */ | |
391 | PPC_LL r5, HOST_STACK_LR(r1) | |
f6127716 | 392 | lwz r6, HOST_CR(r1) |
d30f6e48 SW |
393 | |
394 | /* | |
395 | * We already saved guest volatile register state; now save the | |
396 | * non-volatiles. | |
397 | */ | |
398 | ||
399 | PPC_STL r15, VCPU_GPR(r15)(r4) | |
400 | PPC_STL r16, VCPU_GPR(r16)(r4) | |
401 | PPC_STL r17, VCPU_GPR(r17)(r4) | |
402 | PPC_STL r18, VCPU_GPR(r18)(r4) | |
403 | PPC_STL r19, VCPU_GPR(r19)(r4) | |
404 | PPC_STL r20, VCPU_GPR(r20)(r4) | |
405 | PPC_STL r21, VCPU_GPR(r21)(r4) | |
406 | PPC_STL r22, VCPU_GPR(r22)(r4) | |
407 | PPC_STL r23, VCPU_GPR(r23)(r4) | |
408 | PPC_STL r24, VCPU_GPR(r24)(r4) | |
409 | PPC_STL r25, VCPU_GPR(r25)(r4) | |
410 | PPC_STL r26, VCPU_GPR(r26)(r4) | |
411 | PPC_STL r27, VCPU_GPR(r27)(r4) | |
412 | PPC_STL r28, VCPU_GPR(r28)(r4) | |
413 | PPC_STL r29, VCPU_GPR(r29)(r4) | |
414 | PPC_STL r30, VCPU_GPR(r30)(r4) | |
415 | PPC_STL r31, VCPU_GPR(r31)(r4) | |
416 | ||
417 | /* Load host non-volatile register state from host stack. */ | |
418 | PPC_LL r14, HOST_NV_GPR(r14)(r1) | |
419 | PPC_LL r15, HOST_NV_GPR(r15)(r1) | |
420 | PPC_LL r16, HOST_NV_GPR(r16)(r1) | |
421 | PPC_LL r17, HOST_NV_GPR(r17)(r1) | |
422 | PPC_LL r18, HOST_NV_GPR(r18)(r1) | |
423 | PPC_LL r19, HOST_NV_GPR(r19)(r1) | |
424 | PPC_LL r20, HOST_NV_GPR(r20)(r1) | |
425 | PPC_LL r21, HOST_NV_GPR(r21)(r1) | |
426 | PPC_LL r22, HOST_NV_GPR(r22)(r1) | |
427 | PPC_LL r23, HOST_NV_GPR(r23)(r1) | |
428 | PPC_LL r24, HOST_NV_GPR(r24)(r1) | |
429 | PPC_LL r25, HOST_NV_GPR(r25)(r1) | |
430 | PPC_LL r26, HOST_NV_GPR(r26)(r1) | |
431 | PPC_LL r27, HOST_NV_GPR(r27)(r1) | |
432 | PPC_LL r28, HOST_NV_GPR(r28)(r1) | |
433 | PPC_LL r29, HOST_NV_GPR(r29)(r1) | |
434 | PPC_LL r30, HOST_NV_GPR(r30)(r1) | |
435 | PPC_LL r31, HOST_NV_GPR(r31)(r1) | |
436 | ||
437 | /* Return to kvm_vcpu_run(). */ | |
438 | mtlr r5 | |
f6127716 | 439 | mtcr r6 |
d30f6e48 SW |
440 | addi r1, r1, HOST_STACK_SIZE |
441 | /* r3 still contains the return code from kvmppc_handle_exit(). */ | |
442 | blr | |
443 | ||
444 | /* Registers: | |
445 | * r3: kvm_run pointer | |
446 | * r4: vcpu pointer | |
447 | */ | |
448 | _GLOBAL(__kvmppc_vcpu_run) | |
449 | stwu r1, -HOST_STACK_SIZE(r1) | |
450 | PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */ | |
451 | ||
452 | /* Save host state to stack. */ | |
453 | PPC_STL r3, HOST_RUN(r1) | |
454 | mflr r3 | |
f6127716 | 455 | mfcr r5 |
d30f6e48 SW |
456 | PPC_STL r3, HOST_STACK_LR(r1) |
457 | ||
f6127716 AG |
458 | stw r5, HOST_CR(r1) |
459 | ||
d30f6e48 SW |
460 | /* Save host non-volatile register state to stack. */ |
461 | PPC_STL r14, HOST_NV_GPR(r14)(r1) | |
462 | PPC_STL r15, HOST_NV_GPR(r15)(r1) | |
463 | PPC_STL r16, HOST_NV_GPR(r16)(r1) | |
464 | PPC_STL r17, HOST_NV_GPR(r17)(r1) | |
465 | PPC_STL r18, HOST_NV_GPR(r18)(r1) | |
466 | PPC_STL r19, HOST_NV_GPR(r19)(r1) | |
467 | PPC_STL r20, HOST_NV_GPR(r20)(r1) | |
468 | PPC_STL r21, HOST_NV_GPR(r21)(r1) | |
469 | PPC_STL r22, HOST_NV_GPR(r22)(r1) | |
470 | PPC_STL r23, HOST_NV_GPR(r23)(r1) | |
471 | PPC_STL r24, HOST_NV_GPR(r24)(r1) | |
472 | PPC_STL r25, HOST_NV_GPR(r25)(r1) | |
473 | PPC_STL r26, HOST_NV_GPR(r26)(r1) | |
474 | PPC_STL r27, HOST_NV_GPR(r27)(r1) | |
475 | PPC_STL r28, HOST_NV_GPR(r28)(r1) | |
476 | PPC_STL r29, HOST_NV_GPR(r29)(r1) | |
477 | PPC_STL r30, HOST_NV_GPR(r30)(r1) | |
478 | PPC_STL r31, HOST_NV_GPR(r31)(r1) | |
479 | ||
480 | /* Load guest non-volatiles. */ | |
481 | PPC_LL r14, VCPU_GPR(r14)(r4) | |
482 | PPC_LL r15, VCPU_GPR(r15)(r4) | |
483 | PPC_LL r16, VCPU_GPR(r16)(r4) | |
484 | PPC_LL r17, VCPU_GPR(r17)(r4) | |
485 | PPC_LL r18, VCPU_GPR(r18)(r4) | |
486 | PPC_LL r19, VCPU_GPR(r19)(r4) | |
487 | PPC_LL r20, VCPU_GPR(r20)(r4) | |
488 | PPC_LL r21, VCPU_GPR(r21)(r4) | |
489 | PPC_LL r22, VCPU_GPR(r22)(r4) | |
490 | PPC_LL r23, VCPU_GPR(r23)(r4) | |
491 | PPC_LL r24, VCPU_GPR(r24)(r4) | |
492 | PPC_LL r25, VCPU_GPR(r25)(r4) | |
493 | PPC_LL r26, VCPU_GPR(r26)(r4) | |
494 | PPC_LL r27, VCPU_GPR(r27)(r4) | |
495 | PPC_LL r28, VCPU_GPR(r28)(r4) | |
496 | PPC_LL r29, VCPU_GPR(r29)(r4) | |
497 | PPC_LL r30, VCPU_GPR(r30)(r4) | |
498 | PPC_LL r31, VCPU_GPR(r31)(r4) | |
499 | ||
500 | ||
501 | lightweight_exit: | |
502 | PPC_STL r2, HOST_R2(r1) | |
503 | ||
504 | mfspr r3, SPRN_PID | |
505 | stw r3, VCPU_HOST_PID(r4) | |
506 | lwz r3, VCPU_GUEST_PID(r4) | |
507 | mtspr SPRN_PID, r3 | |
508 | ||
d30f6e48 | 509 | PPC_LL r11, VCPU_SHARED(r4) |
e9ba39c1 AG |
510 | /* Disable MAS register updates via exception */ |
511 | mfspr r3, SPRN_EPCR | |
512 | oris r3, r3, SPRN_EPCR_DMIUH@h | |
513 | mtspr SPRN_EPCR, r3 | |
514 | isync | |
d30f6e48 SW |
515 | /* Save host mas4 and mas6 and load guest MAS registers */ |
516 | mfspr r3, SPRN_MAS4 | |
517 | stw r3, VCPU_HOST_MAS4(r4) | |
518 | mfspr r3, SPRN_MAS6 | |
519 | stw r3, VCPU_HOST_MAS6(r4) | |
520 | lwz r3, VCPU_SHARED_MAS0(r11) | |
521 | lwz r5, VCPU_SHARED_MAS1(r11) | |
185e4188 | 522 | PPC_LD(r6, VCPU_SHARED_MAS2, r11) |
d30f6e48 SW |
523 | lwz r7, VCPU_SHARED_MAS7_3+4(r11) |
524 | lwz r8, VCPU_SHARED_MAS4(r11) | |
525 | mtspr SPRN_MAS0, r3 | |
526 | mtspr SPRN_MAS1, r5 | |
527 | mtspr SPRN_MAS2, r6 | |
528 | mtspr SPRN_MAS3, r7 | |
529 | mtspr SPRN_MAS4, r8 | |
530 | lwz r3, VCPU_SHARED_MAS6(r11) | |
531 | lwz r5, VCPU_SHARED_MAS7_3+0(r11) | |
532 | mtspr SPRN_MAS6, r3 | |
533 | mtspr SPRN_MAS7, r5 | |
d30f6e48 SW |
534 | |
535 | /* | |
536 | * Host interrupt handlers may have clobbered these guest-readable | |
537 | * SPRGs, so we need to reload them here with the guest's values. | |
538 | */ | |
539 | lwz r3, VCPU_VRSAVE(r4) | |
30124906 | 540 | PPC_LD(r5, VCPU_SHARED_SPRG4, r11) |
d30f6e48 | 541 | mtspr SPRN_VRSAVE, r3 |
30124906 | 542 | PPC_LD(r6, VCPU_SHARED_SPRG5, r11) |
d30f6e48 | 543 | mtspr SPRN_SPRG4W, r5 |
30124906 | 544 | PPC_LD(r7, VCPU_SHARED_SPRG6, r11) |
d30f6e48 | 545 | mtspr SPRN_SPRG5W, r6 |
30124906 | 546 | PPC_LD(r8, VCPU_SHARED_SPRG7, r11) |
d30f6e48 SW |
547 | mtspr SPRN_SPRG6W, r7 |
548 | mtspr SPRN_SPRG7W, r8 | |
549 | ||
550 | /* Load some guest volatiles. */ | |
551 | PPC_LL r3, VCPU_LR(r4) | |
552 | PPC_LL r5, VCPU_XER(r4) | |
553 | PPC_LL r6, VCPU_CTR(r4) | |
554 | PPC_LL r7, VCPU_CR(r4) | |
555 | PPC_LL r8, VCPU_PC(r4) | |
185e4188 | 556 | PPC_LD(r9, VCPU_SHARED_MSR, r11) |
d30f6e48 SW |
557 | PPC_LL r0, VCPU_GPR(r0)(r4) |
558 | PPC_LL r1, VCPU_GPR(r1)(r4) | |
559 | PPC_LL r2, VCPU_GPR(r2)(r4) | |
560 | PPC_LL r10, VCPU_GPR(r10)(r4) | |
561 | PPC_LL r11, VCPU_GPR(r11)(r4) | |
562 | PPC_LL r12, VCPU_GPR(r12)(r4) | |
563 | PPC_LL r13, VCPU_GPR(r13)(r4) | |
564 | mtlr r3 | |
565 | mtxer r5 | |
566 | mtctr r6 | |
d30f6e48 SW |
567 | mtsrr0 r8 |
568 | mtsrr1 r9 | |
569 | ||
570 | #ifdef CONFIG_KVM_EXIT_TIMING | |
571 | /* save enter time */ | |
572 | 1: | |
573 | mfspr r6, SPRN_TBRU | |
c0fe7b09 | 574 | mfspr r9, SPRN_TBRL |
d30f6e48 SW |
575 | mfspr r8, SPRN_TBRU |
576 | cmpw r8, r6 | |
c0fe7b09 | 577 | PPC_STL r9, VCPU_TIMING_LAST_ENTER_TBL(r4) |
d30f6e48 SW |
578 | bne 1b |
579 | PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4) | |
580 | #endif | |
581 | ||
c0fe7b09 BB |
582 | /* |
583 | * Don't execute any instruction which can change CR after | |
584 | * below instruction. | |
585 | */ | |
586 | mtcr r7 | |
587 | ||
d30f6e48 SW |
588 | /* Finish loading guest volatiles and jump to guest. */ |
589 | PPC_LL r5, VCPU_GPR(r5)(r4) | |
590 | PPC_LL r6, VCPU_GPR(r6)(r4) | |
591 | PPC_LL r7, VCPU_GPR(r7)(r4) | |
592 | PPC_LL r8, VCPU_GPR(r8)(r4) | |
593 | PPC_LL r9, VCPU_GPR(r9)(r4) | |
594 | ||
595 | PPC_LL r3, VCPU_GPR(r3)(r4) | |
596 | PPC_LL r4, VCPU_GPR(r4)(r4) | |
597 | rfi |