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d30f6e48 SW |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
16 | * | |
17 | * Author: Varun Sethi <varun.sethi@freescale.com> | |
18 | * Author: Scott Wood <scotwood@freescale.com> | |
19 | * | |
20 | * This file is derived from arch/powerpc/kvm/booke_interrupts.S | |
21 | */ | |
22 | ||
23 | #include <asm/ppc_asm.h> | |
24 | #include <asm/kvm_asm.h> | |
25 | #include <asm/reg.h> | |
26 | #include <asm/mmu-44x.h> | |
27 | #include <asm/page.h> | |
28 | #include <asm/asm-compat.h> | |
29 | #include <asm/asm-offsets.h> | |
30 | #include <asm/bitsperlong.h> | |
1d628af7 | 31 | #include <asm/thread_info.h> |
d30f6e48 SW |
32 | |
33 | #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */ | |
34 | ||
35 | #define GET_VCPU(vcpu, thread) \ | |
36 | PPC_LL vcpu, THREAD_KVM_VCPU(thread) | |
37 | ||
d30f6e48 SW |
38 | #define LONGBYTES (BITS_PER_LONG / 8) |
39 | ||
d30f6e48 SW |
40 | #define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES)) |
41 | ||
42 | /* The host stack layout: */ | |
43 | #define HOST_R1 (0 * LONGBYTES) /* Implied by stwu. */ | |
44 | #define HOST_CALLEE_LR (1 * LONGBYTES) | |
45 | #define HOST_RUN (2 * LONGBYTES) /* struct kvm_run */ | |
46 | /* | |
47 | * r2 is special: it holds 'current', and it made nonvolatile in the | |
48 | * kernel with the -ffixed-r2 gcc option. | |
49 | */ | |
50 | #define HOST_R2 (3 * LONGBYTES) | |
f6127716 AG |
51 | #define HOST_CR (4 * LONGBYTES) |
52 | #define HOST_NV_GPRS (5 * LONGBYTES) | |
38df8501 AG |
53 | #define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES)) |
54 | #define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n) | |
55 | #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES) | |
d30f6e48 SW |
56 | #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */ |
57 | #define HOST_STACK_LR (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */ | |
58 | ||
59 | #define NEED_EMU 0x00000001 /* emulation -- save nv regs */ | |
60 | #define NEED_DEAR 0x00000002 /* save faulting DEAR */ | |
61 | #define NEED_ESR 0x00000004 /* save faulting ESR */ | |
62 | ||
63 | /* | |
64 | * On entry: | |
65 | * r4 = vcpu, r5 = srr0, r6 = srr1 | |
66 | * saved in vcpu: cr, ctr, r3-r13 | |
67 | */ | |
68 | .macro kvm_handler_common intno, srr0, flags | |
a2723ce7 | 69 | /* Restore host stack pointer */ |
c75df6f9 MN |
70 | PPC_STL r1, VCPU_GPR(R1)(r4) |
71 | PPC_STL r2, VCPU_GPR(R2)(r4) | |
a2723ce7 AG |
72 | PPC_LL r1, VCPU_HOST_STACK(r4) |
73 | PPC_LL r2, HOST_R2(r1) | |
74 | ||
d30f6e48 SW |
75 | mfspr r10, SPRN_PID |
76 | lwz r8, VCPU_HOST_PID(r4) | |
77 | PPC_LL r11, VCPU_SHARED(r4) | |
c75df6f9 | 78 | PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */ |
d30f6e48 SW |
79 | li r14, \intno |
80 | ||
81 | stw r10, VCPU_GUEST_PID(r4) | |
82 | mtspr SPRN_PID, r8 | |
83 | ||
d30f6e48 SW |
84 | #ifdef CONFIG_KVM_EXIT_TIMING |
85 | /* save exit time */ | |
86 | 1: mfspr r7, SPRN_TBRU | |
87 | mfspr r8, SPRN_TBRL | |
88 | mfspr r9, SPRN_TBRU | |
89 | cmpw r9, r7 | |
518f040c | 90 | stw r8, VCPU_TIMING_EXIT_TBL(r4) |
d30f6e48 | 91 | bne- 1b |
518f040c | 92 | stw r9, VCPU_TIMING_EXIT_TBU(r4) |
d30f6e48 SW |
93 | #endif |
94 | ||
95 | oris r8, r6, MSR_CE@h | |
185e4188 | 96 | PPC_STD(r6, VCPU_SHARED_MSR, r11) |
d30f6e48 SW |
97 | ori r8, r8, MSR_ME | MSR_RI |
98 | PPC_STL r5, VCPU_PC(r4) | |
99 | ||
100 | /* | |
101 | * Make sure CE/ME/RI are set (if appropriate for exception type) | |
102 | * whether or not the guest had it set. Since mfmsr/mtmsr are | |
103 | * somewhat expensive, skip in the common case where the guest | |
104 | * had all these bits set (and thus they're still set if | |
105 | * appropriate for the exception type). | |
106 | */ | |
107 | cmpw r6, r8 | |
d30f6e48 SW |
108 | beq 1f |
109 | mfmsr r7 | |
110 | .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0 | |
111 | oris r7, r7, MSR_CE@h | |
112 | .endif | |
113 | .if \srr0 != SPRN_MCSRR0 | |
114 | ori r7, r7, MSR_ME | MSR_RI | |
115 | .endif | |
116 | mtmsr r7 | |
117 | 1: | |
118 | ||
119 | .if \flags & NEED_EMU | |
120 | /* | |
121 | * This assumes you have external PID support. | |
122 | * To support a bookehv CPU without external PID, you'll | |
123 | * need to look up the TLB entry and create a temporary mapping. | |
124 | * | |
125 | * FIXME: we don't currently handle if the lwepx faults. PR-mode | |
126 | * booke doesn't handle it either. Since Linux doesn't use | |
127 | * broadcast tlbivax anymore, the only way this should happen is | |
128 | * if the guest maps its memory execute-but-not-read, or if we | |
129 | * somehow take a TLB miss in the middle of this entry code and | |
130 | * evict the relevant entry. On e500mc, all kernel lowmem is | |
131 | * bolted into TLB1 large page mappings, and we don't use | |
132 | * broadcast invalidates, so we should not take a TLB miss here. | |
133 | * | |
134 | * Later we'll need to deal with faults here. Disallowing guest | |
135 | * mappings that are execute-but-not-read could be an option on | |
136 | * e500mc, but not on chips with an LRAT if it is used. | |
137 | */ | |
138 | ||
139 | mfspr r3, SPRN_EPLC /* will already have correct ELPID and EGS */ | |
c75df6f9 MN |
140 | PPC_STL r15, VCPU_GPR(R15)(r4) |
141 | PPC_STL r16, VCPU_GPR(R16)(r4) | |
142 | PPC_STL r17, VCPU_GPR(R17)(r4) | |
143 | PPC_STL r18, VCPU_GPR(R18)(r4) | |
144 | PPC_STL r19, VCPU_GPR(R19)(r4) | |
d30f6e48 | 145 | mr r8, r3 |
c75df6f9 | 146 | PPC_STL r20, VCPU_GPR(R20)(r4) |
d30f6e48 | 147 | rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS |
c75df6f9 | 148 | PPC_STL r21, VCPU_GPR(R21)(r4) |
d30f6e48 | 149 | rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR |
c75df6f9 | 150 | PPC_STL r22, VCPU_GPR(R22)(r4) |
d30f6e48 | 151 | rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID |
c75df6f9 MN |
152 | PPC_STL r23, VCPU_GPR(R23)(r4) |
153 | PPC_STL r24, VCPU_GPR(R24)(r4) | |
154 | PPC_STL r25, VCPU_GPR(R25)(r4) | |
155 | PPC_STL r26, VCPU_GPR(R26)(r4) | |
156 | PPC_STL r27, VCPU_GPR(R27)(r4) | |
157 | PPC_STL r28, VCPU_GPR(R28)(r4) | |
158 | PPC_STL r29, VCPU_GPR(R29)(r4) | |
159 | PPC_STL r30, VCPU_GPR(R30)(r4) | |
160 | PPC_STL r31, VCPU_GPR(R31)(r4) | |
d30f6e48 | 161 | mtspr SPRN_EPLC, r8 |
1d628af7 AG |
162 | |
163 | /* disable preemption, so we are sure we hit the fixup handler */ | |
9778b696 | 164 | CURRENT_THREAD_INFO(r8, r1) |
1d628af7 AG |
165 | li r7, 1 |
166 | stw r7, TI_PREEMPT(r8) | |
167 | ||
d30f6e48 | 168 | isync |
1d628af7 AG |
169 | |
170 | /* | |
171 | * In case the read goes wrong, we catch it and write an invalid value | |
172 | * in LAST_INST instead. | |
173 | */ | |
174 | 1: lwepx r9, 0, r5 | |
175 | 2: | |
176 | .section .fixup, "ax" | |
177 | 3: li r9, KVM_INST_FETCH_FAILED | |
178 | b 2b | |
179 | .previous | |
180 | .section __ex_table,"a" | |
181 | PPC_LONG_ALIGN | |
182 | PPC_LONG 1b,3b | |
183 | .previous | |
184 | ||
d30f6e48 | 185 | mtspr SPRN_EPLC, r3 |
1d628af7 AG |
186 | li r7, 0 |
187 | stw r7, TI_PREEMPT(r8) | |
d30f6e48 SW |
188 | stw r9, VCPU_LAST_INST(r4) |
189 | .endif | |
190 | ||
191 | .if \flags & NEED_ESR | |
192 | mfspr r8, SPRN_ESR | |
193 | PPC_STL r8, VCPU_FAULT_ESR(r4) | |
194 | .endif | |
195 | ||
196 | .if \flags & NEED_DEAR | |
197 | mfspr r9, SPRN_DEAR | |
198 | PPC_STL r9, VCPU_FAULT_DEAR(r4) | |
199 | .endif | |
200 | ||
201 | b kvmppc_resume_host | |
202 | .endm | |
203 | ||
204 | /* | |
205 | * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h | |
206 | */ | |
207 | .macro kvm_handler intno srr0, srr1, flags | |
208 | _GLOBAL(kvmppc_handler_\intno\()_\srr1) | |
209 | GET_VCPU(r11, r10) | |
c75df6f9 | 210 | PPC_STL r3, VCPU_GPR(R3)(r11) |
d30f6e48 | 211 | mfspr r3, SPRN_SPRG_RSCRATCH0 |
c75df6f9 | 212 | PPC_STL r4, VCPU_GPR(R4)(r11) |
d30f6e48 | 213 | PPC_LL r4, THREAD_NORMSAVE(0)(r10) |
c75df6f9 | 214 | PPC_STL r5, VCPU_GPR(R5)(r11) |
518f040c | 215 | stw r13, VCPU_CR(r11) |
d30f6e48 | 216 | mfspr r5, \srr0 |
c75df6f9 | 217 | PPC_STL r3, VCPU_GPR(R10)(r11) |
d30f6e48 | 218 | PPC_LL r3, THREAD_NORMSAVE(2)(r10) |
c75df6f9 MN |
219 | PPC_STL r6, VCPU_GPR(R6)(r11) |
220 | PPC_STL r4, VCPU_GPR(R11)(r11) | |
d30f6e48 | 221 | mfspr r6, \srr1 |
c75df6f9 MN |
222 | PPC_STL r7, VCPU_GPR(R7)(r11) |
223 | PPC_STL r8, VCPU_GPR(R8)(r11) | |
224 | PPC_STL r9, VCPU_GPR(R9)(r11) | |
225 | PPC_STL r3, VCPU_GPR(R13)(r11) | |
d30f6e48 | 226 | mfctr r7 |
c75df6f9 | 227 | PPC_STL r12, VCPU_GPR(R12)(r11) |
d30f6e48 SW |
228 | PPC_STL r7, VCPU_CTR(r11) |
229 | mr r4, r11 | |
230 | kvm_handler_common \intno, \srr0, \flags | |
231 | .endm | |
232 | ||
233 | .macro kvm_lvl_handler intno scratch srr0, srr1, flags | |
234 | _GLOBAL(kvmppc_handler_\intno\()_\srr1) | |
235 | mfspr r10, SPRN_SPRG_THREAD | |
236 | GET_VCPU(r11, r10) | |
c75df6f9 | 237 | PPC_STL r3, VCPU_GPR(R3)(r11) |
d30f6e48 | 238 | mfspr r3, \scratch |
c75df6f9 | 239 | PPC_STL r4, VCPU_GPR(R4)(r11) |
d30f6e48 | 240 | PPC_LL r4, GPR9(r8) |
c75df6f9 | 241 | PPC_STL r5, VCPU_GPR(R5)(r11) |
518f040c | 242 | stw r9, VCPU_CR(r11) |
d30f6e48 | 243 | mfspr r5, \srr0 |
c75df6f9 | 244 | PPC_STL r3, VCPU_GPR(R8)(r11) |
d30f6e48 | 245 | PPC_LL r3, GPR10(r8) |
c75df6f9 MN |
246 | PPC_STL r6, VCPU_GPR(R6)(r11) |
247 | PPC_STL r4, VCPU_GPR(R9)(r11) | |
d30f6e48 SW |
248 | mfspr r6, \srr1 |
249 | PPC_LL r4, GPR11(r8) | |
c75df6f9 MN |
250 | PPC_STL r7, VCPU_GPR(R7)(r11) |
251 | PPC_STL r3, VCPU_GPR(R10)(r11) | |
d30f6e48 | 252 | mfctr r7 |
c75df6f9 MN |
253 | PPC_STL r12, VCPU_GPR(R12)(r11) |
254 | PPC_STL r13, VCPU_GPR(R13)(r11) | |
255 | PPC_STL r4, VCPU_GPR(R11)(r11) | |
d30f6e48 SW |
256 | PPC_STL r7, VCPU_CTR(r11) |
257 | mr r4, r11 | |
258 | kvm_handler_common \intno, \srr0, \flags | |
259 | .endm | |
260 | ||
261 | kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \ | |
262 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
263 | kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \ | |
264 | SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0 | |
265 | kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \ | |
9997782e | 266 | SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR) |
d30f6e48 SW |
267 | kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR |
268 | kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0 | |
269 | kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \ | |
270 | SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR) | |
271 | kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR | |
272 | kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 | |
273 | kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0 | |
274 | kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 | |
275 | kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0 | |
276 | kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0 | |
277 | kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \ | |
278 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
279 | kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \ | |
280 | SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR) | |
281 | kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0 | |
282 | kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0 | |
283 | kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0 | |
284 | kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0 | |
285 | kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0 | |
286 | kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0 | |
287 | kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \ | |
288 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
289 | kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU | |
290 | kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0 | |
291 | kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0 | |
292 | kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \ | |
293 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
294 | kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \ | |
295 | SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0 | |
296 | kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \ | |
297 | SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0 | |
298 | ||
299 | ||
300 | /* Registers: | |
301 | * SPRG_SCRATCH0: guest r10 | |
302 | * r4: vcpu pointer | |
303 | * r11: vcpu->arch.shared | |
304 | * r14: KVM exit number | |
305 | */ | |
306 | _GLOBAL(kvmppc_resume_host) | |
307 | /* Save remaining volatile guest register state to vcpu. */ | |
308 | mfspr r3, SPRN_VRSAVE | |
c75df6f9 | 309 | PPC_STL r0, VCPU_GPR(R0)(r4) |
d30f6e48 SW |
310 | mflr r5 |
311 | mfspr r6, SPRN_SPRG4 | |
d30f6e48 SW |
312 | PPC_STL r5, VCPU_LR(r4) |
313 | mfspr r7, SPRN_SPRG5 | |
518f040c | 314 | stw r3, VCPU_VRSAVE(r4) |
30124906 | 315 | PPC_STD(r6, VCPU_SHARED_SPRG4, r11) |
d30f6e48 | 316 | mfspr r8, SPRN_SPRG6 |
30124906 | 317 | PPC_STD(r7, VCPU_SHARED_SPRG5, r11) |
d30f6e48 | 318 | mfspr r9, SPRN_SPRG7 |
30124906 | 319 | PPC_STD(r8, VCPU_SHARED_SPRG6, r11) |
d30f6e48 | 320 | mfxer r3 |
30124906 | 321 | PPC_STD(r9, VCPU_SHARED_SPRG7, r11) |
d30f6e48 SW |
322 | |
323 | /* save guest MAS registers and restore host mas4 & mas6 */ | |
324 | mfspr r5, SPRN_MAS0 | |
325 | PPC_STL r3, VCPU_XER(r4) | |
326 | mfspr r6, SPRN_MAS1 | |
327 | stw r5, VCPU_SHARED_MAS0(r11) | |
328 | mfspr r7, SPRN_MAS2 | |
329 | stw r6, VCPU_SHARED_MAS1(r11) | |
185e4188 | 330 | PPC_STD(r7, VCPU_SHARED_MAS2, r11) |
d30f6e48 SW |
331 | mfspr r5, SPRN_MAS3 |
332 | mfspr r6, SPRN_MAS4 | |
333 | stw r5, VCPU_SHARED_MAS7_3+4(r11) | |
334 | mfspr r7, SPRN_MAS6 | |
335 | stw r6, VCPU_SHARED_MAS4(r11) | |
336 | mfspr r5, SPRN_MAS7 | |
337 | lwz r6, VCPU_HOST_MAS4(r4) | |
338 | stw r7, VCPU_SHARED_MAS6(r11) | |
339 | lwz r8, VCPU_HOST_MAS6(r4) | |
340 | mtspr SPRN_MAS4, r6 | |
341 | stw r5, VCPU_SHARED_MAS7_3+0(r11) | |
342 | mtspr SPRN_MAS6, r8 | |
e9ba39c1 | 343 | /* Enable MAS register updates via exception */ |
d30f6e48 SW |
344 | mfspr r3, SPRN_EPCR |
345 | rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH | |
346 | mtspr SPRN_EPCR, r3 | |
347 | isync | |
348 | ||
d30f6e48 SW |
349 | /* Switch to kernel stack and jump to handler. */ |
350 | PPC_LL r3, HOST_RUN(r1) | |
351 | mr r5, r14 /* intno */ | |
352 | mr r14, r4 /* Save vcpu pointer. */ | |
353 | bl kvmppc_handle_exit | |
354 | ||
355 | /* Restore vcpu pointer and the nonvolatiles we used. */ | |
356 | mr r4, r14 | |
c75df6f9 | 357 | PPC_LL r14, VCPU_GPR(R14)(r4) |
d30f6e48 SW |
358 | |
359 | andi. r5, r3, RESUME_FLAG_NV | |
360 | beq skip_nv_load | |
c75df6f9 MN |
361 | PPC_LL r15, VCPU_GPR(R15)(r4) |
362 | PPC_LL r16, VCPU_GPR(R16)(r4) | |
363 | PPC_LL r17, VCPU_GPR(R17)(r4) | |
364 | PPC_LL r18, VCPU_GPR(R18)(r4) | |
365 | PPC_LL r19, VCPU_GPR(R19)(r4) | |
366 | PPC_LL r20, VCPU_GPR(R20)(r4) | |
367 | PPC_LL r21, VCPU_GPR(R21)(r4) | |
368 | PPC_LL r22, VCPU_GPR(R22)(r4) | |
369 | PPC_LL r23, VCPU_GPR(R23)(r4) | |
370 | PPC_LL r24, VCPU_GPR(R24)(r4) | |
371 | PPC_LL r25, VCPU_GPR(R25)(r4) | |
372 | PPC_LL r26, VCPU_GPR(R26)(r4) | |
373 | PPC_LL r27, VCPU_GPR(R27)(r4) | |
374 | PPC_LL r28, VCPU_GPR(R28)(r4) | |
375 | PPC_LL r29, VCPU_GPR(R29)(r4) | |
376 | PPC_LL r30, VCPU_GPR(R30)(r4) | |
377 | PPC_LL r31, VCPU_GPR(R31)(r4) | |
d30f6e48 SW |
378 | skip_nv_load: |
379 | /* Should we return to the guest? */ | |
380 | andi. r5, r3, RESUME_FLAG_HOST | |
381 | beq lightweight_exit | |
382 | ||
383 | srawi r3, r3, 2 /* Shift -ERR back down. */ | |
384 | ||
385 | heavyweight_exit: | |
386 | /* Not returning to guest. */ | |
387 | PPC_LL r5, HOST_STACK_LR(r1) | |
f6127716 | 388 | lwz r6, HOST_CR(r1) |
d30f6e48 SW |
389 | |
390 | /* | |
391 | * We already saved guest volatile register state; now save the | |
392 | * non-volatiles. | |
393 | */ | |
394 | ||
c75df6f9 MN |
395 | PPC_STL r15, VCPU_GPR(R15)(r4) |
396 | PPC_STL r16, VCPU_GPR(R16)(r4) | |
397 | PPC_STL r17, VCPU_GPR(R17)(r4) | |
398 | PPC_STL r18, VCPU_GPR(R18)(r4) | |
399 | PPC_STL r19, VCPU_GPR(R19)(r4) | |
400 | PPC_STL r20, VCPU_GPR(R20)(r4) | |
401 | PPC_STL r21, VCPU_GPR(R21)(r4) | |
402 | PPC_STL r22, VCPU_GPR(R22)(r4) | |
403 | PPC_STL r23, VCPU_GPR(R23)(r4) | |
404 | PPC_STL r24, VCPU_GPR(R24)(r4) | |
405 | PPC_STL r25, VCPU_GPR(R25)(r4) | |
406 | PPC_STL r26, VCPU_GPR(R26)(r4) | |
407 | PPC_STL r27, VCPU_GPR(R27)(r4) | |
408 | PPC_STL r28, VCPU_GPR(R28)(r4) | |
409 | PPC_STL r29, VCPU_GPR(R29)(r4) | |
410 | PPC_STL r30, VCPU_GPR(R30)(r4) | |
411 | PPC_STL r31, VCPU_GPR(R31)(r4) | |
d30f6e48 SW |
412 | |
413 | /* Load host non-volatile register state from host stack. */ | |
38df8501 AG |
414 | PPC_LL r14, HOST_NV_GPR(R14)(r1) |
415 | PPC_LL r15, HOST_NV_GPR(R15)(r1) | |
416 | PPC_LL r16, HOST_NV_GPR(R16)(r1) | |
417 | PPC_LL r17, HOST_NV_GPR(R17)(r1) | |
418 | PPC_LL r18, HOST_NV_GPR(R18)(r1) | |
419 | PPC_LL r19, HOST_NV_GPR(R19)(r1) | |
420 | PPC_LL r20, HOST_NV_GPR(R20)(r1) | |
421 | PPC_LL r21, HOST_NV_GPR(R21)(r1) | |
422 | PPC_LL r22, HOST_NV_GPR(R22)(r1) | |
423 | PPC_LL r23, HOST_NV_GPR(R23)(r1) | |
424 | PPC_LL r24, HOST_NV_GPR(R24)(r1) | |
425 | PPC_LL r25, HOST_NV_GPR(R25)(r1) | |
426 | PPC_LL r26, HOST_NV_GPR(R26)(r1) | |
427 | PPC_LL r27, HOST_NV_GPR(R27)(r1) | |
428 | PPC_LL r28, HOST_NV_GPR(R28)(r1) | |
429 | PPC_LL r29, HOST_NV_GPR(R29)(r1) | |
430 | PPC_LL r30, HOST_NV_GPR(R30)(r1) | |
431 | PPC_LL r31, HOST_NV_GPR(R31)(r1) | |
d30f6e48 SW |
432 | |
433 | /* Return to kvm_vcpu_run(). */ | |
434 | mtlr r5 | |
f6127716 | 435 | mtcr r6 |
d30f6e48 SW |
436 | addi r1, r1, HOST_STACK_SIZE |
437 | /* r3 still contains the return code from kvmppc_handle_exit(). */ | |
438 | blr | |
439 | ||
440 | /* Registers: | |
441 | * r3: kvm_run pointer | |
442 | * r4: vcpu pointer | |
443 | */ | |
444 | _GLOBAL(__kvmppc_vcpu_run) | |
445 | stwu r1, -HOST_STACK_SIZE(r1) | |
446 | PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */ | |
447 | ||
448 | /* Save host state to stack. */ | |
449 | PPC_STL r3, HOST_RUN(r1) | |
450 | mflr r3 | |
f6127716 | 451 | mfcr r5 |
d30f6e48 SW |
452 | PPC_STL r3, HOST_STACK_LR(r1) |
453 | ||
f6127716 AG |
454 | stw r5, HOST_CR(r1) |
455 | ||
d30f6e48 | 456 | /* Save host non-volatile register state to stack. */ |
38df8501 AG |
457 | PPC_STL r14, HOST_NV_GPR(R14)(r1) |
458 | PPC_STL r15, HOST_NV_GPR(R15)(r1) | |
459 | PPC_STL r16, HOST_NV_GPR(R16)(r1) | |
460 | PPC_STL r17, HOST_NV_GPR(R17)(r1) | |
461 | PPC_STL r18, HOST_NV_GPR(R18)(r1) | |
462 | PPC_STL r19, HOST_NV_GPR(R19)(r1) | |
463 | PPC_STL r20, HOST_NV_GPR(R20)(r1) | |
464 | PPC_STL r21, HOST_NV_GPR(R21)(r1) | |
465 | PPC_STL r22, HOST_NV_GPR(R22)(r1) | |
466 | PPC_STL r23, HOST_NV_GPR(R23)(r1) | |
467 | PPC_STL r24, HOST_NV_GPR(R24)(r1) | |
468 | PPC_STL r25, HOST_NV_GPR(R25)(r1) | |
469 | PPC_STL r26, HOST_NV_GPR(R26)(r1) | |
470 | PPC_STL r27, HOST_NV_GPR(R27)(r1) | |
471 | PPC_STL r28, HOST_NV_GPR(R28)(r1) | |
472 | PPC_STL r29, HOST_NV_GPR(R29)(r1) | |
473 | PPC_STL r30, HOST_NV_GPR(R30)(r1) | |
474 | PPC_STL r31, HOST_NV_GPR(R31)(r1) | |
d30f6e48 SW |
475 | |
476 | /* Load guest non-volatiles. */ | |
c75df6f9 MN |
477 | PPC_LL r14, VCPU_GPR(R14)(r4) |
478 | PPC_LL r15, VCPU_GPR(R15)(r4) | |
479 | PPC_LL r16, VCPU_GPR(R16)(r4) | |
480 | PPC_LL r17, VCPU_GPR(R17)(r4) | |
481 | PPC_LL r18, VCPU_GPR(R18)(r4) | |
482 | PPC_LL r19, VCPU_GPR(R19)(r4) | |
483 | PPC_LL r20, VCPU_GPR(R20)(r4) | |
484 | PPC_LL r21, VCPU_GPR(R21)(r4) | |
485 | PPC_LL r22, VCPU_GPR(R22)(r4) | |
486 | PPC_LL r23, VCPU_GPR(R23)(r4) | |
487 | PPC_LL r24, VCPU_GPR(R24)(r4) | |
488 | PPC_LL r25, VCPU_GPR(R25)(r4) | |
489 | PPC_LL r26, VCPU_GPR(R26)(r4) | |
490 | PPC_LL r27, VCPU_GPR(R27)(r4) | |
491 | PPC_LL r28, VCPU_GPR(R28)(r4) | |
492 | PPC_LL r29, VCPU_GPR(R29)(r4) | |
493 | PPC_LL r30, VCPU_GPR(R30)(r4) | |
494 | PPC_LL r31, VCPU_GPR(R31)(r4) | |
d30f6e48 SW |
495 | |
496 | ||
497 | lightweight_exit: | |
498 | PPC_STL r2, HOST_R2(r1) | |
499 | ||
500 | mfspr r3, SPRN_PID | |
501 | stw r3, VCPU_HOST_PID(r4) | |
502 | lwz r3, VCPU_GUEST_PID(r4) | |
503 | mtspr SPRN_PID, r3 | |
504 | ||
d30f6e48 | 505 | PPC_LL r11, VCPU_SHARED(r4) |
e9ba39c1 AG |
506 | /* Disable MAS register updates via exception */ |
507 | mfspr r3, SPRN_EPCR | |
508 | oris r3, r3, SPRN_EPCR_DMIUH@h | |
509 | mtspr SPRN_EPCR, r3 | |
510 | isync | |
d30f6e48 SW |
511 | /* Save host mas4 and mas6 and load guest MAS registers */ |
512 | mfspr r3, SPRN_MAS4 | |
513 | stw r3, VCPU_HOST_MAS4(r4) | |
514 | mfspr r3, SPRN_MAS6 | |
515 | stw r3, VCPU_HOST_MAS6(r4) | |
516 | lwz r3, VCPU_SHARED_MAS0(r11) | |
517 | lwz r5, VCPU_SHARED_MAS1(r11) | |
185e4188 | 518 | PPC_LD(r6, VCPU_SHARED_MAS2, r11) |
d30f6e48 SW |
519 | lwz r7, VCPU_SHARED_MAS7_3+4(r11) |
520 | lwz r8, VCPU_SHARED_MAS4(r11) | |
521 | mtspr SPRN_MAS0, r3 | |
522 | mtspr SPRN_MAS1, r5 | |
523 | mtspr SPRN_MAS2, r6 | |
524 | mtspr SPRN_MAS3, r7 | |
525 | mtspr SPRN_MAS4, r8 | |
526 | lwz r3, VCPU_SHARED_MAS6(r11) | |
527 | lwz r5, VCPU_SHARED_MAS7_3+0(r11) | |
528 | mtspr SPRN_MAS6, r3 | |
529 | mtspr SPRN_MAS7, r5 | |
d30f6e48 SW |
530 | |
531 | /* | |
532 | * Host interrupt handlers may have clobbered these guest-readable | |
533 | * SPRGs, so we need to reload them here with the guest's values. | |
534 | */ | |
535 | lwz r3, VCPU_VRSAVE(r4) | |
30124906 | 536 | PPC_LD(r5, VCPU_SHARED_SPRG4, r11) |
d30f6e48 | 537 | mtspr SPRN_VRSAVE, r3 |
30124906 | 538 | PPC_LD(r6, VCPU_SHARED_SPRG5, r11) |
d30f6e48 | 539 | mtspr SPRN_SPRG4W, r5 |
30124906 | 540 | PPC_LD(r7, VCPU_SHARED_SPRG6, r11) |
d30f6e48 | 541 | mtspr SPRN_SPRG5W, r6 |
30124906 | 542 | PPC_LD(r8, VCPU_SHARED_SPRG7, r11) |
d30f6e48 SW |
543 | mtspr SPRN_SPRG6W, r7 |
544 | mtspr SPRN_SPRG7W, r8 | |
545 | ||
546 | /* Load some guest volatiles. */ | |
547 | PPC_LL r3, VCPU_LR(r4) | |
548 | PPC_LL r5, VCPU_XER(r4) | |
549 | PPC_LL r6, VCPU_CTR(r4) | |
518f040c | 550 | lwz r7, VCPU_CR(r4) |
d30f6e48 | 551 | PPC_LL r8, VCPU_PC(r4) |
185e4188 | 552 | PPC_LD(r9, VCPU_SHARED_MSR, r11) |
c75df6f9 MN |
553 | PPC_LL r0, VCPU_GPR(R0)(r4) |
554 | PPC_LL r1, VCPU_GPR(R1)(r4) | |
555 | PPC_LL r2, VCPU_GPR(R2)(r4) | |
556 | PPC_LL r10, VCPU_GPR(R10)(r4) | |
557 | PPC_LL r11, VCPU_GPR(R11)(r4) | |
558 | PPC_LL r12, VCPU_GPR(R12)(r4) | |
559 | PPC_LL r13, VCPU_GPR(R13)(r4) | |
d30f6e48 SW |
560 | mtlr r3 |
561 | mtxer r5 | |
562 | mtctr r6 | |
d30f6e48 SW |
563 | mtsrr0 r8 |
564 | mtsrr1 r9 | |
565 | ||
566 | #ifdef CONFIG_KVM_EXIT_TIMING | |
567 | /* save enter time */ | |
568 | 1: | |
569 | mfspr r6, SPRN_TBRU | |
c0fe7b09 | 570 | mfspr r9, SPRN_TBRL |
d30f6e48 SW |
571 | mfspr r8, SPRN_TBRU |
572 | cmpw r8, r6 | |
518f040c | 573 | stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4) |
d30f6e48 | 574 | bne 1b |
518f040c | 575 | stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4) |
d30f6e48 SW |
576 | #endif |
577 | ||
c0fe7b09 BB |
578 | /* |
579 | * Don't execute any instruction which can change CR after | |
580 | * below instruction. | |
581 | */ | |
582 | mtcr r7 | |
583 | ||
d30f6e48 | 584 | /* Finish loading guest volatiles and jump to guest. */ |
c75df6f9 MN |
585 | PPC_LL r5, VCPU_GPR(R5)(r4) |
586 | PPC_LL r6, VCPU_GPR(R6)(r4) | |
587 | PPC_LL r7, VCPU_GPR(R7)(r4) | |
588 | PPC_LL r8, VCPU_GPR(R8)(r4) | |
589 | PPC_LL r9, VCPU_GPR(R9)(r4) | |
590 | ||
591 | PPC_LL r3, VCPU_GPR(R3)(r4) | |
592 | PPC_LL r4, VCPU_GPR(R4)(r4) | |
d30f6e48 | 593 | rfi |