Commit | Line | Data |
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d0c7dc03 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2008 | |
dfd4d47e | 16 | * Copyright 2011 Freescale Semiconductor, Inc. |
d0c7dc03 HB |
17 | * |
18 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/kvm_host.h> | |
22 | #include <asm/disassemble.h> | |
23 | ||
24 | #include "booke.h" | |
25 | ||
26 | #define OP_19_XOP_RFI 50 | |
0c1fc3c3 | 27 | #define OP_19_XOP_RFCI 51 |
d0c7dc03 HB |
28 | |
29 | #define OP_31_XOP_MFMSR 83 | |
30 | #define OP_31_XOP_WRTEE 131 | |
31 | #define OP_31_XOP_MTMSR 146 | |
32 | #define OP_31_XOP_WRTEEI 163 | |
33 | ||
34 | static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu) | |
35 | { | |
de7906c3 AG |
36 | vcpu->arch.pc = vcpu->arch.shared->srr0; |
37 | kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1); | |
d0c7dc03 HB |
38 | } |
39 | ||
0c1fc3c3 BB |
40 | static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu) |
41 | { | |
42 | vcpu->arch.pc = vcpu->arch.csrr0; | |
43 | kvmppc_set_msr(vcpu, vcpu->arch.csrr1); | |
44 | } | |
45 | ||
d0c7dc03 HB |
46 | int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, |
47 | unsigned int inst, int *advance) | |
48 | { | |
49 | int emulated = EMULATE_DONE; | |
c46dc9a8 AG |
50 | int rs = get_rs(inst); |
51 | int rt = get_rt(inst); | |
d0c7dc03 HB |
52 | |
53 | switch (get_op(inst)) { | |
54 | case 19: | |
55 | switch (get_xop(inst)) { | |
56 | case OP_19_XOP_RFI: | |
57 | kvmppc_emul_rfi(vcpu); | |
58 | kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS); | |
59 | *advance = 0; | |
60 | break; | |
61 | ||
0c1fc3c3 BB |
62 | case OP_19_XOP_RFCI: |
63 | kvmppc_emul_rfci(vcpu); | |
64 | kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS); | |
65 | *advance = 0; | |
66 | break; | |
67 | ||
d0c7dc03 HB |
68 | default: |
69 | emulated = EMULATE_FAIL; | |
70 | break; | |
71 | } | |
72 | break; | |
73 | ||
74 | case 31: | |
75 | switch (get_xop(inst)) { | |
76 | ||
77 | case OP_31_XOP_MFMSR: | |
666e7252 | 78 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr); |
d0c7dc03 HB |
79 | kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS); |
80 | break; | |
81 | ||
82 | case OP_31_XOP_MTMSR: | |
d0c7dc03 | 83 | kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS); |
8e5b26b5 | 84 | kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs)); |
d0c7dc03 HB |
85 | break; |
86 | ||
87 | case OP_31_XOP_WRTEE: | |
666e7252 | 88 | vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE) |
8e5b26b5 | 89 | | (kvmppc_get_gpr(vcpu, rs) & MSR_EE); |
d0c7dc03 HB |
90 | kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS); |
91 | break; | |
92 | ||
93 | case OP_31_XOP_WRTEEI: | |
666e7252 | 94 | vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE) |
d0c7dc03 HB |
95 | | (inst & MSR_EE); |
96 | kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS); | |
97 | break; | |
98 | ||
99 | default: | |
100 | emulated = EMULATE_FAIL; | |
101 | } | |
102 | ||
103 | break; | |
104 | ||
105 | default: | |
106 | emulated = EMULATE_FAIL; | |
107 | } | |
108 | ||
109 | return emulated; | |
110 | } | |
111 | ||
d30f6e48 SW |
112 | /* |
113 | * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode). | |
114 | * Their backing store is in real registers, and these functions | |
115 | * will return the wrong result if called for them in another context | |
116 | * (such as debugging). | |
117 | */ | |
54771e62 | 118 | int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val) |
d0c7dc03 HB |
119 | { |
120 | int emulated = EMULATE_DONE; | |
121 | ||
122 | switch (sprn) { | |
123 | case SPRN_DEAR: | |
54771e62 AG |
124 | vcpu->arch.shared->dar = spr_val; |
125 | break; | |
d0c7dc03 | 126 | case SPRN_ESR: |
54771e62 AG |
127 | vcpu->arch.shared->esr = spr_val; |
128 | break; | |
0c1fc3c3 BB |
129 | case SPRN_CSRR0: |
130 | vcpu->arch.csrr0 = spr_val; | |
131 | break; | |
132 | case SPRN_CSRR1: | |
133 | vcpu->arch.csrr1 = spr_val; | |
134 | break; | |
d0c7dc03 | 135 | case SPRN_DBCR0: |
6df8d3fc | 136 | vcpu->arch.dbg_reg.dbcr0 = spr_val; |
54771e62 | 137 | break; |
d0c7dc03 | 138 | case SPRN_DBCR1: |
6df8d3fc | 139 | vcpu->arch.dbg_reg.dbcr1 = spr_val; |
54771e62 | 140 | break; |
f7b200af | 141 | case SPRN_DBSR: |
54771e62 AG |
142 | vcpu->arch.dbsr &= ~spr_val; |
143 | break; | |
d0c7dc03 | 144 | case SPRN_TSR: |
dfd4d47e SW |
145 | kvmppc_clr_tsr_bits(vcpu, spr_val); |
146 | break; | |
d0c7dc03 | 147 | case SPRN_TCR: |
f61c94bb BB |
148 | /* |
149 | * WRC is a 2-bit field that is supposed to preserve its | |
150 | * value once written to non-zero. | |
151 | */ | |
152 | if (vcpu->arch.tcr & TCR_WRC_MASK) { | |
153 | spr_val &= ~TCR_WRC_MASK; | |
154 | spr_val |= vcpu->arch.tcr & TCR_WRC_MASK; | |
155 | } | |
dfd4d47e | 156 | kvmppc_set_tcr(vcpu, spr_val); |
d0c7dc03 HB |
157 | break; |
158 | ||
21bd000a BB |
159 | case SPRN_DECAR: |
160 | vcpu->arch.decar = spr_val; | |
161 | break; | |
d30f6e48 SW |
162 | /* |
163 | * Note: SPRG4-7 are user-readable. | |
164 | * These values are loaded into the real SPRGs when resuming the | |
165 | * guest (PR-mode only). | |
166 | */ | |
d0c7dc03 | 167 | case SPRN_SPRG4: |
54771e62 AG |
168 | vcpu->arch.shared->sprg4 = spr_val; |
169 | break; | |
d0c7dc03 | 170 | case SPRN_SPRG5: |
54771e62 AG |
171 | vcpu->arch.shared->sprg5 = spr_val; |
172 | break; | |
d0c7dc03 | 173 | case SPRN_SPRG6: |
54771e62 AG |
174 | vcpu->arch.shared->sprg6 = spr_val; |
175 | break; | |
d0c7dc03 | 176 | case SPRN_SPRG7: |
54771e62 AG |
177 | vcpu->arch.shared->sprg7 = spr_val; |
178 | break; | |
d0c7dc03 HB |
179 | |
180 | case SPRN_IVPR: | |
8e5b26b5 | 181 | vcpu->arch.ivpr = spr_val; |
d30f6e48 SW |
182 | #ifdef CONFIG_KVM_BOOKE_HV |
183 | mtspr(SPRN_GIVPR, spr_val); | |
184 | #endif | |
d0c7dc03 HB |
185 | break; |
186 | case SPRN_IVOR0: | |
8e5b26b5 | 187 | vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val; |
d0c7dc03 HB |
188 | break; |
189 | case SPRN_IVOR1: | |
8e5b26b5 | 190 | vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val; |
d0c7dc03 HB |
191 | break; |
192 | case SPRN_IVOR2: | |
8e5b26b5 | 193 | vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val; |
d30f6e48 SW |
194 | #ifdef CONFIG_KVM_BOOKE_HV |
195 | mtspr(SPRN_GIVOR2, spr_val); | |
196 | #endif | |
d0c7dc03 HB |
197 | break; |
198 | case SPRN_IVOR3: | |
8e5b26b5 | 199 | vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val; |
d0c7dc03 HB |
200 | break; |
201 | case SPRN_IVOR4: | |
8e5b26b5 | 202 | vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val; |
d0c7dc03 HB |
203 | break; |
204 | case SPRN_IVOR5: | |
8e5b26b5 | 205 | vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val; |
d0c7dc03 HB |
206 | break; |
207 | case SPRN_IVOR6: | |
8e5b26b5 | 208 | vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val; |
d0c7dc03 HB |
209 | break; |
210 | case SPRN_IVOR7: | |
8e5b26b5 | 211 | vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val; |
d0c7dc03 HB |
212 | break; |
213 | case SPRN_IVOR8: | |
8e5b26b5 | 214 | vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val; |
d30f6e48 SW |
215 | #ifdef CONFIG_KVM_BOOKE_HV |
216 | mtspr(SPRN_GIVOR8, spr_val); | |
217 | #endif | |
d0c7dc03 HB |
218 | break; |
219 | case SPRN_IVOR9: | |
8e5b26b5 | 220 | vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val; |
d0c7dc03 HB |
221 | break; |
222 | case SPRN_IVOR10: | |
8e5b26b5 | 223 | vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val; |
d0c7dc03 HB |
224 | break; |
225 | case SPRN_IVOR11: | |
8e5b26b5 | 226 | vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val; |
d0c7dc03 HB |
227 | break; |
228 | case SPRN_IVOR12: | |
8e5b26b5 | 229 | vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val; |
d0c7dc03 HB |
230 | break; |
231 | case SPRN_IVOR13: | |
8e5b26b5 | 232 | vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val; |
d0c7dc03 HB |
233 | break; |
234 | case SPRN_IVOR14: | |
8e5b26b5 | 235 | vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val; |
d0c7dc03 HB |
236 | break; |
237 | case SPRN_IVOR15: | |
8e5b26b5 | 238 | vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val; |
d0c7dc03 HB |
239 | break; |
240 | ||
241 | default: | |
242 | emulated = EMULATE_FAIL; | |
243 | } | |
244 | ||
245 | return emulated; | |
246 | } | |
247 | ||
54771e62 | 248 | int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val) |
d0c7dc03 HB |
249 | { |
250 | int emulated = EMULATE_DONE; | |
251 | ||
252 | switch (sprn) { | |
253 | case SPRN_IVPR: | |
54771e62 AG |
254 | *spr_val = vcpu->arch.ivpr; |
255 | break; | |
d0c7dc03 | 256 | case SPRN_DEAR: |
54771e62 AG |
257 | *spr_val = vcpu->arch.shared->dar; |
258 | break; | |
d0c7dc03 | 259 | case SPRN_ESR: |
54771e62 AG |
260 | *spr_val = vcpu->arch.shared->esr; |
261 | break; | |
0c1fc3c3 BB |
262 | case SPRN_CSRR0: |
263 | *spr_val = vcpu->arch.csrr0; | |
264 | break; | |
265 | case SPRN_CSRR1: | |
266 | *spr_val = vcpu->arch.csrr1; | |
267 | break; | |
d0c7dc03 | 268 | case SPRN_DBCR0: |
6df8d3fc | 269 | *spr_val = vcpu->arch.dbg_reg.dbcr0; |
54771e62 | 270 | break; |
d0c7dc03 | 271 | case SPRN_DBCR1: |
6df8d3fc | 272 | *spr_val = vcpu->arch.dbg_reg.dbcr1; |
54771e62 | 273 | break; |
f7b200af | 274 | case SPRN_DBSR: |
54771e62 AG |
275 | *spr_val = vcpu->arch.dbsr; |
276 | break; | |
dfd4d47e | 277 | case SPRN_TSR: |
54771e62 AG |
278 | *spr_val = vcpu->arch.tsr; |
279 | break; | |
dfd4d47e | 280 | case SPRN_TCR: |
54771e62 AG |
281 | *spr_val = vcpu->arch.tcr; |
282 | break; | |
d0c7dc03 HB |
283 | |
284 | case SPRN_IVOR0: | |
54771e62 | 285 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; |
d0c7dc03 HB |
286 | break; |
287 | case SPRN_IVOR1: | |
54771e62 | 288 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; |
d0c7dc03 HB |
289 | break; |
290 | case SPRN_IVOR2: | |
54771e62 | 291 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; |
d0c7dc03 HB |
292 | break; |
293 | case SPRN_IVOR3: | |
54771e62 | 294 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; |
d0c7dc03 HB |
295 | break; |
296 | case SPRN_IVOR4: | |
54771e62 | 297 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; |
d0c7dc03 HB |
298 | break; |
299 | case SPRN_IVOR5: | |
54771e62 | 300 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; |
d0c7dc03 HB |
301 | break; |
302 | case SPRN_IVOR6: | |
54771e62 | 303 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; |
d0c7dc03 HB |
304 | break; |
305 | case SPRN_IVOR7: | |
54771e62 | 306 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; |
d0c7dc03 HB |
307 | break; |
308 | case SPRN_IVOR8: | |
54771e62 | 309 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; |
d0c7dc03 HB |
310 | break; |
311 | case SPRN_IVOR9: | |
54771e62 | 312 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; |
d0c7dc03 HB |
313 | break; |
314 | case SPRN_IVOR10: | |
54771e62 | 315 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; |
d0c7dc03 HB |
316 | break; |
317 | case SPRN_IVOR11: | |
54771e62 | 318 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; |
d0c7dc03 HB |
319 | break; |
320 | case SPRN_IVOR12: | |
54771e62 | 321 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; |
d0c7dc03 HB |
322 | break; |
323 | case SPRN_IVOR13: | |
54771e62 | 324 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; |
d0c7dc03 HB |
325 | break; |
326 | case SPRN_IVOR14: | |
54771e62 | 327 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; |
d0c7dc03 HB |
328 | break; |
329 | case SPRN_IVOR15: | |
54771e62 | 330 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; |
d0c7dc03 HB |
331 | break; |
332 | ||
333 | default: | |
334 | emulated = EMULATE_FAIL; | |
335 | } | |
336 | ||
337 | return emulated; | |
338 | } |