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d0c7dc03 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2008 | |
dfd4d47e | 16 | * Copyright 2011 Freescale Semiconductor, Inc. |
d0c7dc03 HB |
17 | * |
18 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/kvm_host.h> | |
22 | #include <asm/disassemble.h> | |
23 | ||
24 | #include "booke.h" | |
25 | ||
26 | #define OP_19_XOP_RFI 50 | |
27 | ||
28 | #define OP_31_XOP_MFMSR 83 | |
29 | #define OP_31_XOP_WRTEE 131 | |
30 | #define OP_31_XOP_MTMSR 146 | |
31 | #define OP_31_XOP_WRTEEI 163 | |
32 | ||
33 | static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu) | |
34 | { | |
de7906c3 AG |
35 | vcpu->arch.pc = vcpu->arch.shared->srr0; |
36 | kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1); | |
d0c7dc03 HB |
37 | } |
38 | ||
39 | int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
40 | unsigned int inst, int *advance) | |
41 | { | |
42 | int emulated = EMULATE_DONE; | |
c46dc9a8 AG |
43 | int rs = get_rs(inst); |
44 | int rt = get_rt(inst); | |
d0c7dc03 HB |
45 | |
46 | switch (get_op(inst)) { | |
47 | case 19: | |
48 | switch (get_xop(inst)) { | |
49 | case OP_19_XOP_RFI: | |
50 | kvmppc_emul_rfi(vcpu); | |
51 | kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS); | |
52 | *advance = 0; | |
53 | break; | |
54 | ||
55 | default: | |
56 | emulated = EMULATE_FAIL; | |
57 | break; | |
58 | } | |
59 | break; | |
60 | ||
61 | case 31: | |
62 | switch (get_xop(inst)) { | |
63 | ||
64 | case OP_31_XOP_MFMSR: | |
666e7252 | 65 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr); |
d0c7dc03 HB |
66 | kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS); |
67 | break; | |
68 | ||
69 | case OP_31_XOP_MTMSR: | |
d0c7dc03 | 70 | kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS); |
8e5b26b5 | 71 | kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs)); |
d0c7dc03 HB |
72 | break; |
73 | ||
74 | case OP_31_XOP_WRTEE: | |
666e7252 | 75 | vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE) |
8e5b26b5 | 76 | | (kvmppc_get_gpr(vcpu, rs) & MSR_EE); |
d0c7dc03 HB |
77 | kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS); |
78 | break; | |
79 | ||
80 | case OP_31_XOP_WRTEEI: | |
666e7252 | 81 | vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE) |
d0c7dc03 HB |
82 | | (inst & MSR_EE); |
83 | kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS); | |
84 | break; | |
85 | ||
86 | default: | |
87 | emulated = EMULATE_FAIL; | |
88 | } | |
89 | ||
90 | break; | |
91 | ||
92 | default: | |
93 | emulated = EMULATE_FAIL; | |
94 | } | |
95 | ||
96 | return emulated; | |
97 | } | |
98 | ||
d30f6e48 SW |
99 | /* |
100 | * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode). | |
101 | * Their backing store is in real registers, and these functions | |
102 | * will return the wrong result if called for them in another context | |
103 | * (such as debugging). | |
104 | */ | |
54771e62 | 105 | int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val) |
d0c7dc03 HB |
106 | { |
107 | int emulated = EMULATE_DONE; | |
108 | ||
109 | switch (sprn) { | |
110 | case SPRN_DEAR: | |
54771e62 AG |
111 | vcpu->arch.shared->dar = spr_val; |
112 | break; | |
d0c7dc03 | 113 | case SPRN_ESR: |
54771e62 AG |
114 | vcpu->arch.shared->esr = spr_val; |
115 | break; | |
d0c7dc03 | 116 | case SPRN_DBCR0: |
54771e62 AG |
117 | vcpu->arch.dbcr0 = spr_val; |
118 | break; | |
d0c7dc03 | 119 | case SPRN_DBCR1: |
54771e62 AG |
120 | vcpu->arch.dbcr1 = spr_val; |
121 | break; | |
f7b200af | 122 | case SPRN_DBSR: |
54771e62 AG |
123 | vcpu->arch.dbsr &= ~spr_val; |
124 | break; | |
d0c7dc03 | 125 | case SPRN_TSR: |
dfd4d47e SW |
126 | kvmppc_clr_tsr_bits(vcpu, spr_val); |
127 | break; | |
d0c7dc03 | 128 | case SPRN_TCR: |
dfd4d47e | 129 | kvmppc_set_tcr(vcpu, spr_val); |
d0c7dc03 HB |
130 | break; |
131 | ||
d30f6e48 SW |
132 | /* |
133 | * Note: SPRG4-7 are user-readable. | |
134 | * These values are loaded into the real SPRGs when resuming the | |
135 | * guest (PR-mode only). | |
136 | */ | |
d0c7dc03 | 137 | case SPRN_SPRG4: |
54771e62 AG |
138 | vcpu->arch.shared->sprg4 = spr_val; |
139 | break; | |
d0c7dc03 | 140 | case SPRN_SPRG5: |
54771e62 AG |
141 | vcpu->arch.shared->sprg5 = spr_val; |
142 | break; | |
d0c7dc03 | 143 | case SPRN_SPRG6: |
54771e62 AG |
144 | vcpu->arch.shared->sprg6 = spr_val; |
145 | break; | |
d0c7dc03 | 146 | case SPRN_SPRG7: |
54771e62 AG |
147 | vcpu->arch.shared->sprg7 = spr_val; |
148 | break; | |
d0c7dc03 HB |
149 | |
150 | case SPRN_IVPR: | |
8e5b26b5 | 151 | vcpu->arch.ivpr = spr_val; |
d30f6e48 SW |
152 | #ifdef CONFIG_KVM_BOOKE_HV |
153 | mtspr(SPRN_GIVPR, spr_val); | |
154 | #endif | |
d0c7dc03 HB |
155 | break; |
156 | case SPRN_IVOR0: | |
8e5b26b5 | 157 | vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val; |
d0c7dc03 HB |
158 | break; |
159 | case SPRN_IVOR1: | |
8e5b26b5 | 160 | vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val; |
d0c7dc03 HB |
161 | break; |
162 | case SPRN_IVOR2: | |
8e5b26b5 | 163 | vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val; |
d30f6e48 SW |
164 | #ifdef CONFIG_KVM_BOOKE_HV |
165 | mtspr(SPRN_GIVOR2, spr_val); | |
166 | #endif | |
d0c7dc03 HB |
167 | break; |
168 | case SPRN_IVOR3: | |
8e5b26b5 | 169 | vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val; |
d0c7dc03 HB |
170 | break; |
171 | case SPRN_IVOR4: | |
8e5b26b5 | 172 | vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val; |
d0c7dc03 HB |
173 | break; |
174 | case SPRN_IVOR5: | |
8e5b26b5 | 175 | vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val; |
d0c7dc03 HB |
176 | break; |
177 | case SPRN_IVOR6: | |
8e5b26b5 | 178 | vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val; |
d0c7dc03 HB |
179 | break; |
180 | case SPRN_IVOR7: | |
8e5b26b5 | 181 | vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val; |
d0c7dc03 HB |
182 | break; |
183 | case SPRN_IVOR8: | |
8e5b26b5 | 184 | vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val; |
d30f6e48 SW |
185 | #ifdef CONFIG_KVM_BOOKE_HV |
186 | mtspr(SPRN_GIVOR8, spr_val); | |
187 | #endif | |
d0c7dc03 HB |
188 | break; |
189 | case SPRN_IVOR9: | |
8e5b26b5 | 190 | vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val; |
d0c7dc03 HB |
191 | break; |
192 | case SPRN_IVOR10: | |
8e5b26b5 | 193 | vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val; |
d0c7dc03 HB |
194 | break; |
195 | case SPRN_IVOR11: | |
8e5b26b5 | 196 | vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val; |
d0c7dc03 HB |
197 | break; |
198 | case SPRN_IVOR12: | |
8e5b26b5 | 199 | vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val; |
d0c7dc03 HB |
200 | break; |
201 | case SPRN_IVOR13: | |
8e5b26b5 | 202 | vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val; |
d0c7dc03 HB |
203 | break; |
204 | case SPRN_IVOR14: | |
8e5b26b5 | 205 | vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val; |
d0c7dc03 HB |
206 | break; |
207 | case SPRN_IVOR15: | |
8e5b26b5 | 208 | vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val; |
d0c7dc03 HB |
209 | break; |
210 | ||
211 | default: | |
212 | emulated = EMULATE_FAIL; | |
213 | } | |
214 | ||
215 | return emulated; | |
216 | } | |
217 | ||
54771e62 | 218 | int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val) |
d0c7dc03 HB |
219 | { |
220 | int emulated = EMULATE_DONE; | |
221 | ||
222 | switch (sprn) { | |
223 | case SPRN_IVPR: | |
54771e62 AG |
224 | *spr_val = vcpu->arch.ivpr; |
225 | break; | |
d0c7dc03 | 226 | case SPRN_DEAR: |
54771e62 AG |
227 | *spr_val = vcpu->arch.shared->dar; |
228 | break; | |
d0c7dc03 | 229 | case SPRN_ESR: |
54771e62 AG |
230 | *spr_val = vcpu->arch.shared->esr; |
231 | break; | |
d0c7dc03 | 232 | case SPRN_DBCR0: |
54771e62 AG |
233 | *spr_val = vcpu->arch.dbcr0; |
234 | break; | |
d0c7dc03 | 235 | case SPRN_DBCR1: |
54771e62 AG |
236 | *spr_val = vcpu->arch.dbcr1; |
237 | break; | |
f7b200af | 238 | case SPRN_DBSR: |
54771e62 AG |
239 | *spr_val = vcpu->arch.dbsr; |
240 | break; | |
dfd4d47e | 241 | case SPRN_TSR: |
54771e62 AG |
242 | *spr_val = vcpu->arch.tsr; |
243 | break; | |
dfd4d47e | 244 | case SPRN_TCR: |
54771e62 AG |
245 | *spr_val = vcpu->arch.tcr; |
246 | break; | |
d0c7dc03 HB |
247 | |
248 | case SPRN_IVOR0: | |
54771e62 | 249 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; |
d0c7dc03 HB |
250 | break; |
251 | case SPRN_IVOR1: | |
54771e62 | 252 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; |
d0c7dc03 HB |
253 | break; |
254 | case SPRN_IVOR2: | |
54771e62 | 255 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; |
d0c7dc03 HB |
256 | break; |
257 | case SPRN_IVOR3: | |
54771e62 | 258 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; |
d0c7dc03 HB |
259 | break; |
260 | case SPRN_IVOR4: | |
54771e62 | 261 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; |
d0c7dc03 HB |
262 | break; |
263 | case SPRN_IVOR5: | |
54771e62 | 264 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; |
d0c7dc03 HB |
265 | break; |
266 | case SPRN_IVOR6: | |
54771e62 | 267 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; |
d0c7dc03 HB |
268 | break; |
269 | case SPRN_IVOR7: | |
54771e62 | 270 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; |
d0c7dc03 HB |
271 | break; |
272 | case SPRN_IVOR8: | |
54771e62 | 273 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; |
d0c7dc03 HB |
274 | break; |
275 | case SPRN_IVOR9: | |
54771e62 | 276 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; |
d0c7dc03 HB |
277 | break; |
278 | case SPRN_IVOR10: | |
54771e62 | 279 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; |
d0c7dc03 HB |
280 | break; |
281 | case SPRN_IVOR11: | |
54771e62 | 282 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; |
d0c7dc03 HB |
283 | break; |
284 | case SPRN_IVOR12: | |
54771e62 | 285 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; |
d0c7dc03 HB |
286 | break; |
287 | case SPRN_IVOR13: | |
54771e62 | 288 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; |
d0c7dc03 HB |
289 | break; |
290 | case SPRN_IVOR14: | |
54771e62 | 291 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; |
d0c7dc03 HB |
292 | break; |
293 | case SPRN_IVOR15: | |
54771e62 | 294 | *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; |
d0c7dc03 HB |
295 | break; |
296 | ||
297 | default: | |
298 | emulated = EMULATE_FAIL; | |
299 | } | |
300 | ||
301 | return emulated; | |
302 | } |