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Merge branch 'vmwgfx-fixes-5.3' of git://people.freedesktop.org/~thomash/linux into...
[linux-2.6-block.git] / arch / powerpc / kvm / booke_emulate.c
CommitLineData
d94d71cb 1// SPDX-License-Identifier: GPL-2.0-only
d0c7dc03 2/*
d0c7dc03
HB		 3 *
4 * Copyright IBM Corp. 2008
dfd4d47e 5 * Copyright 2011 Freescale Semiconductor, Inc.
d0c7dc03
HB		 6 *
7 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
8 */
9
10#include <linux/kvm_host.h>
11#include <asm/disassemble.h>
12
13#include "booke.h"
14
15#define OP_19_XOP_RFI 50
0c1fc3c3 16#define OP_19_XOP_RFCI 51
c8ca97ca 17#define OP_19_XOP_RFDI 39
d0c7dc03
HB		 18
19#define OP_31_XOP_MFMSR 83
20#define OP_31_XOP_WRTEE 131
21#define OP_31_XOP_MTMSR 146
22#define OP_31_XOP_WRTEEI 163
23
24static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
25{
173c520a 26 vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
de7906c3 27 kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
d0c7dc03
HB		 28}
29
c8ca97ca
BB		 30static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
31{
173c520a 32 vcpu->arch.regs.nip = vcpu->arch.dsrr0;
c8ca97ca
BB		 33 kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
34}
35
0c1fc3c3
BB		 36static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
37{
173c520a 38 vcpu->arch.regs.nip = vcpu->arch.csrr0;
0c1fc3c3
BB		 39 kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
40}
41
d0c7dc03
HB		 42int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
43 unsigned int inst, int *advance)
44{
45 int emulated = EMULATE_DONE;
c46dc9a8
AG		 46 int rs = get_rs(inst);
47 int rt = get_rt(inst);
d0c7dc03
HB		 48
49 switch (get_op(inst)) {
50 case 19:
51 switch (get_xop(inst)) {
52 case OP_19_XOP_RFI:
53 kvmppc_emul_rfi(vcpu);
54 kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
55 *advance = 0;
56 break;
57
0c1fc3c3
BB		 58 case OP_19_XOP_RFCI:
59 kvmppc_emul_rfci(vcpu);
60 kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
61 *advance = 0;
62 break;
63
c8ca97ca
BB		 64 case OP_19_XOP_RFDI:
65 kvmppc_emul_rfdi(vcpu);
66 kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
67 *advance = 0;
68 break;
69
d0c7dc03
HB		 70 default:
71 emulated = EMULATE_FAIL;
72 break;
73 }
74 break;
75
76 case 31:
77 switch (get_xop(inst)) {
78
79 case OP_31_XOP_MFMSR:
666e7252 80 kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
d0c7dc03
HB		 81 kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
82 break;
83
84 case OP_31_XOP_MTMSR:
d0c7dc03 85 kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
8e5b26b5 86 kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
d0c7dc03
HB		 87 break;
88
89 case OP_31_XOP_WRTEE:
666e7252 90 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
8e5b26b5 91 | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
d0c7dc03
HB		 92 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
93 break;
94
95 case OP_31_XOP_WRTEEI:
666e7252 96 vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
d0c7dc03
HB		 97 | (inst & MSR_EE);
98 kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
99 break;
100
101 default:
102 emulated = EMULATE_FAIL;
103 }
104
105 break;
106
107 default:
108 emulated = EMULATE_FAIL;
109 }
110
111 return emulated;
112}
113
d30f6e48
SW		 114/*
115 * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
116 * Their backing store is in real registers, and these functions
117 * will return the wrong result if called for them in another context
118 * (such as debugging).
119 */
54771e62 120int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
d0c7dc03
HB		 121{
122 int emulated = EMULATE_DONE;
2f699a59 123 bool debug_inst = false;
d0c7dc03
HB		 124
125 switch (sprn) {
126 case SPRN_DEAR:
54771e62
AG		 127 vcpu->arch.shared->dar = spr_val;
128 break;
d0c7dc03 129 case SPRN_ESR:
54771e62
AG		 130 vcpu->arch.shared->esr = spr_val;
131 break;
0c1fc3c3
BB		 132 case SPRN_CSRR0:
133 vcpu->arch.csrr0 = spr_val;
134 break;
135 case SPRN_CSRR1:
136 vcpu->arch.csrr1 = spr_val;
137 break;
2f699a59
BB		 138 case SPRN_DSRR0:
139 vcpu->arch.dsrr0 = spr_val;
140 break;
141 case SPRN_DSRR1:
142 vcpu->arch.dsrr1 = spr_val;
143 break;
144 case SPRN_IAC1:
145 /*
146 * If userspace is debugging guest then guest
147 * can not access debug registers.
148 */
149 if (vcpu->guest_debug)
150 break;
151
152 debug_inst = true;
153 vcpu->arch.dbg_reg.iac1 = spr_val;
154 break;
155 case SPRN_IAC2:
156 /*
157 * If userspace is debugging guest then guest
158 * can not access debug registers.
159 */
160 if (vcpu->guest_debug)
161 break;
162
163 debug_inst = true;
164 vcpu->arch.dbg_reg.iac2 = spr_val;
165 break;
166#if CONFIG_PPC_ADV_DEBUG_IACS > 2
167 case SPRN_IAC3:
168 /*
169 * If userspace is debugging guest then guest
170 * can not access debug registers.
171 */
172 if (vcpu->guest_debug)
173 break;
174
175 debug_inst = true;
176 vcpu->arch.dbg_reg.iac3 = spr_val;
177 break;
178 case SPRN_IAC4:
179 /*
180 * If userspace is debugging guest then guest
181 * can not access debug registers.
182 */
183 if (vcpu->guest_debug)
184 break;
185
186 debug_inst = true;
187 vcpu->arch.dbg_reg.iac4 = spr_val;
188 break;
189#endif
190 case SPRN_DAC1:
191 /*
192 * If userspace is debugging guest then guest
193 * can not access debug registers.
194 */
195 if (vcpu->guest_debug)
196 break;
197
198 debug_inst = true;
199 vcpu->arch.dbg_reg.dac1 = spr_val;
200 break;
201 case SPRN_DAC2:
202 /*
203 * If userspace is debugging guest then guest
204 * can not access debug registers.
205 */
206 if (vcpu->guest_debug)
207 break;
208
209 debug_inst = true;
210 vcpu->arch.dbg_reg.dac2 = spr_val;
211 break;
d0c7dc03 212 case SPRN_DBCR0:
2f699a59
BB		 213 /*
214 * If userspace is debugging guest then guest
215 * can not access debug registers.
216 */
217 if (vcpu->guest_debug)
218 break;
219
220 debug_inst = true;
221 spr_val &= (DBCR0_IDM | DBCR0_IC | DBCR0_BT | DBCR0_TIE |
222 DBCR0_IAC1 | DBCR0_IAC2 | DBCR0_IAC3 | DBCR0_IAC4 |
223 DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W);
224
6df8d3fc 225 vcpu->arch.dbg_reg.dbcr0 = spr_val;
54771e62 226 break;
d0c7dc03 227 case SPRN_DBCR1:
2f699a59
BB		 228 /*
229 * If userspace is debugging guest then guest
230 * can not access debug registers.
231 */
232 if (vcpu->guest_debug)
233 break;
234
235 debug_inst = true;
6df8d3fc 236 vcpu->arch.dbg_reg.dbcr1 = spr_val;
54771e62 237 break;
2f699a59
BB		 238 case SPRN_DBCR2:
239 /*
240 * If userspace is debugging guest then guest
241 * can not access debug registers.
242 */
243 if (vcpu->guest_debug)
244 break;
245
246 debug_inst = true;
247 vcpu->arch.dbg_reg.dbcr2 = spr_val;
248 break;
f7b200af 249 case SPRN_DBSR:
2f699a59
BB		 250 /*
251 * If userspace is debugging guest then guest
252 * can not access debug registers.
253 */
254 if (vcpu->guest_debug)
255 break;
256
54771e62 257 vcpu->arch.dbsr &= ~spr_val;
2f699a59
BB		 258 if (!(vcpu->arch.dbsr & ~DBSR_IDE))
259 kvmppc_core_dequeue_debug(vcpu);
54771e62 260 break;
d0c7dc03 261 case SPRN_TSR:
dfd4d47e
SW		 262 kvmppc_clr_tsr_bits(vcpu, spr_val);
263 break;
d0c7dc03 264 case SPRN_TCR:
f61c94bb
BB		 265 /*
266 * WRC is a 2-bit field that is supposed to preserve its
267 * value once written to non-zero.
268 */
269 if (vcpu->arch.tcr & TCR_WRC_MASK) {
270 spr_val &= ~TCR_WRC_MASK;
271 spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
272 }
dfd4d47e 273 kvmppc_set_tcr(vcpu, spr_val);
d0c7dc03
HB		 274 break;
275
21bd000a
BB		 276 case SPRN_DECAR:
277 vcpu->arch.decar = spr_val;
278 break;
d30f6e48
SW		 279 /*
280 * Note: SPRG4-7 are user-readable.
281 * These values are loaded into the real SPRGs when resuming the
282 * guest (PR-mode only).
283 */
d0c7dc03 284 case SPRN_SPRG4:
c1b8a01b 285 kvmppc_set_sprg4(vcpu, spr_val);
54771e62 286 break;
d0c7dc03 287 case SPRN_SPRG5:
c1b8a01b 288 kvmppc_set_sprg5(vcpu, spr_val);
54771e62 289 break;
d0c7dc03 290 case SPRN_SPRG6:
c1b8a01b 291 kvmppc_set_sprg6(vcpu, spr_val);
54771e62 292 break;
d0c7dc03 293 case SPRN_SPRG7:
c1b8a01b 294 kvmppc_set_sprg7(vcpu, spr_val);
54771e62 295 break;
d0c7dc03
HB		 296
297 case SPRN_IVPR:
8e5b26b5 298 vcpu->arch.ivpr = spr_val;
d30f6e48
SW		 299#ifdef CONFIG_KVM_BOOKE_HV
300 mtspr(SPRN_GIVPR, spr_val);
301#endif
d0c7dc03
HB		 302 break;
303 case SPRN_IVOR0:
8e5b26b5 304 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
d0c7dc03
HB		 305 break;
306 case SPRN_IVOR1:
8e5b26b5 307 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
d0c7dc03
HB		 308 break;
309 case SPRN_IVOR2:
8e5b26b5 310 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
d30f6e48
SW		 311#ifdef CONFIG_KVM_BOOKE_HV
312 mtspr(SPRN_GIVOR2, spr_val);
313#endif
d0c7dc03
HB		 314 break;
315 case SPRN_IVOR3:
8e5b26b5 316 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
d0c7dc03
HB		 317 break;
318 case SPRN_IVOR4:
8e5b26b5 319 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
d0c7dc03
HB		 320 break;
321 case SPRN_IVOR5:
8e5b26b5 322 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
d0c7dc03
HB		 323 break;
324 case SPRN_IVOR6:
8e5b26b5 325 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
d0c7dc03
HB		 326 break;
327 case SPRN_IVOR7:
8e5b26b5 328 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
d0c7dc03
HB		 329 break;
330 case SPRN_IVOR8:
8e5b26b5 331 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
d30f6e48
SW		 332#ifdef CONFIG_KVM_BOOKE_HV
333 mtspr(SPRN_GIVOR8, spr_val);
334#endif
d0c7dc03
HB		 335 break;
336 case SPRN_IVOR9:
8e5b26b5 337 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
d0c7dc03
HB		 338 break;
339 case SPRN_IVOR10:
8e5b26b5 340 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
d0c7dc03
HB		 341 break;
342 case SPRN_IVOR11:
8e5b26b5 343 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
d0c7dc03
HB		 344 break;
345 case SPRN_IVOR12:
8e5b26b5 346 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
d0c7dc03
HB		 347 break;
348 case SPRN_IVOR13:
8e5b26b5 349 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
d0c7dc03
HB		 350 break;
351 case SPRN_IVOR14:
8e5b26b5 352 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
d0c7dc03
HB		 353 break;
354 case SPRN_IVOR15:
8e5b26b5 355 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
d0c7dc03 356 break;
50c871ed
AG		 357 case SPRN_MCSR:
358 vcpu->arch.mcsr &= ~spr_val;
359 break;
38f98824
MC		 360#if defined(CONFIG_64BIT)
361 case SPRN_EPCR:
362 kvmppc_set_epcr(vcpu, spr_val);
363#ifdef CONFIG_KVM_BOOKE_HV
364 mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
365#endif
366 break;
367#endif
d0c7dc03
HB		 368 default:
369 emulated = EMULATE_FAIL;
370 }
371
2f699a59
BB		 372 if (debug_inst) {
373 current->thread.debug = vcpu->arch.dbg_reg;
374 switch_booke_debug_regs(&vcpu->arch.dbg_reg);
375 }
d0c7dc03
HB		 376 return emulated;
377}
378
54771e62 379int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
d0c7dc03
HB		 380{
381 int emulated = EMULATE_DONE;
382
383 switch (sprn) {
384 case SPRN_IVPR:
54771e62
AG		 385 *spr_val = vcpu->arch.ivpr;
386 break;
d0c7dc03 387 case SPRN_DEAR:
54771e62
AG		 388 *spr_val = vcpu->arch.shared->dar;
389 break;
d0c7dc03 390 case SPRN_ESR:
54771e62
AG		 391 *spr_val = vcpu->arch.shared->esr;
392 break;
37ecb257
AG		 393 case SPRN_EPR:
394 *spr_val = vcpu->arch.epr;
395 break;
0c1fc3c3
BB		 396 case SPRN_CSRR0:
397 *spr_val = vcpu->arch.csrr0;
398 break;
399 case SPRN_CSRR1:
400 *spr_val = vcpu->arch.csrr1;
401 break;
2f699a59
BB		 402 case SPRN_DSRR0:
403 *spr_val = vcpu->arch.dsrr0;
404 break;
405 case SPRN_DSRR1:
406 *spr_val = vcpu->arch.dsrr1;
407 break;
408 case SPRN_IAC1:
409 *spr_val = vcpu->arch.dbg_reg.iac1;
410 break;
411 case SPRN_IAC2:
412 *spr_val = vcpu->arch.dbg_reg.iac2;
413 break;
414#if CONFIG_PPC_ADV_DEBUG_IACS > 2
415 case SPRN_IAC3:
416 *spr_val = vcpu->arch.dbg_reg.iac3;
417 break;
418 case SPRN_IAC4:
419 *spr_val = vcpu->arch.dbg_reg.iac4;
420 break;
421#endif
422 case SPRN_DAC1:
423 *spr_val = vcpu->arch.dbg_reg.dac1;
424 break;
425 case SPRN_DAC2:
426 *spr_val = vcpu->arch.dbg_reg.dac2;
427 break;
d0c7dc03 428 case SPRN_DBCR0:
6df8d3fc 429 *spr_val = vcpu->arch.dbg_reg.dbcr0;
348ba710
BB		 430 if (vcpu->guest_debug)
431 *spr_val = *spr_val | DBCR0_EDM;
54771e62 432 break;
d0c7dc03 433 case SPRN_DBCR1:
6df8d3fc 434 *spr_val = vcpu->arch.dbg_reg.dbcr1;
54771e62 435 break;
2f699a59
BB		 436 case SPRN_DBCR2:
437 *spr_val = vcpu->arch.dbg_reg.dbcr2;
438 break;
f7b200af 439 case SPRN_DBSR:
54771e62
AG		 440 *spr_val = vcpu->arch.dbsr;
441 break;
dfd4d47e 442 case SPRN_TSR:
54771e62
AG		 443 *spr_val = vcpu->arch.tsr;
444 break;
dfd4d47e 445 case SPRN_TCR:
54771e62
AG		 446 *spr_val = vcpu->arch.tcr;
447 break;
d0c7dc03
HB		 448
449 case SPRN_IVOR0:
54771e62 450 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
d0c7dc03
HB		 451 break;
452 case SPRN_IVOR1:
54771e62 453 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
d0c7dc03
HB		 454 break;
455 case SPRN_IVOR2:
54771e62 456 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
d0c7dc03
HB		 457 break;
458 case SPRN_IVOR3:
54771e62 459 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
d0c7dc03
HB		 460 break;
461 case SPRN_IVOR4:
54771e62 462 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
d0c7dc03
HB		 463 break;
464 case SPRN_IVOR5:
54771e62 465 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
d0c7dc03
HB		 466 break;
467 case SPRN_IVOR6:
54771e62 468 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
d0c7dc03
HB		 469 break;
470 case SPRN_IVOR7:
54771e62 471 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
d0c7dc03
HB		 472 break;
473 case SPRN_IVOR8:
54771e62 474 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
d0c7dc03
HB		 475 break;
476 case SPRN_IVOR9:
54771e62 477 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
d0c7dc03
HB		 478 break;
479 case SPRN_IVOR10:
54771e62 480 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
d0c7dc03
HB		 481 break;
482 case SPRN_IVOR11:
54771e62 483 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
d0c7dc03
HB		 484 break;
485 case SPRN_IVOR12:
54771e62 486 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
d0c7dc03
HB		 487 break;
488 case SPRN_IVOR13:
54771e62 489 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
d0c7dc03
HB		 490 break;
491 case SPRN_IVOR14:
54771e62 492 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
d0c7dc03
HB		 493 break;
494 case SPRN_IVOR15:
54771e62 495 *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
d0c7dc03 496 break;
50c871ed
AG		 497 case SPRN_MCSR:
498 *spr_val = vcpu->arch.mcsr;
499 break;
38f98824
MC		 500#if defined(CONFIG_64BIT)
501 case SPRN_EPCR:
502 *spr_val = vcpu->arch.epcr;
503 break;
504#endif
d0c7dc03
HB		 505
506 default:
507 emulated = EMULATE_FAIL;
508 }
509
510 return emulated;
511}
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