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KVM: PPC: Remove the tasklet used by the hrtimer
[linux-2.6-block.git] / arch / powerpc / kvm / booke.c
CommitLineData
bbf45ba5
HB		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
4cd35f67 16 * Copyright 2010-2011 Freescale Semiconductor, Inc.
bbf45ba5
HB		 17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
d30f6e48
SW		 20 * Scott Wood <scottwood@freescale.com>
21 * Varun Sethi <varun.sethi@freescale.com>
bbf45ba5
HB		 22 */
23
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/kvm_host.h>
5a0e3ad6 27#include <linux/gfp.h>
bbf45ba5
HB		 28#include <linux/module.h>
29#include <linux/vmalloc.h>
30#include <linux/fs.h>
7924bd41 31
bbf45ba5
HB		 32#include <asm/cputable.h>
33#include <asm/uaccess.h>
34#include <asm/kvm_ppc.h>
d9fbd03d 35#include <asm/cacheflush.h>
d30f6e48
SW		 36#include <asm/dbell.h>
37#include <asm/hw_irq.h>
38#include <asm/irq.h>
b50df19c 39#include <asm/time.h>
bbf45ba5 40
d30f6e48 41#include "timing.h"
75f74f0d 42#include "booke.h"
dba291f2
AK		 43
44#define CREATE_TRACE_POINTS
45#include "trace_booke.h"
bbf45ba5 46
d9fbd03d
HB		 47unsigned long kvmppc_booke_handlers;
48
bbf45ba5
HB		 49#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
50#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
51
52struct kvm_stats_debugfs_item debugfs_entries[] = {
bbf45ba5 53 { "mmio", VCPU_STAT(mmio_exits) },
bbf45ba5 54 { "sig", VCPU_STAT(signal_exits) },
bbf45ba5
HB		 55 { "itlb_r", VCPU_STAT(itlb_real_miss_exits) },
56 { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) },
57 { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) },
58 { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) },
59 { "sysc", VCPU_STAT(syscall_exits) },
60 { "isi", VCPU_STAT(isi_exits) },
61 { "dsi", VCPU_STAT(dsi_exits) },
62 { "inst_emu", VCPU_STAT(emulated_inst_exits) },
63 { "dec", VCPU_STAT(dec_exits) },
64 { "ext_intr", VCPU_STAT(ext_intr_exits) },
45c5eb67 65 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
d30f6e48
SW		 66 { "doorbell", VCPU_STAT(dbell_exits) },
67 { "guest doorbell", VCPU_STAT(gdbell_exits) },
cf1c5ca4 68 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
bbf45ba5
HB		 69 { NULL }
70};
71
bbf45ba5
HB		 72/* TODO: use vcpu_printf() */
73void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
74{
75 int i;
76
666e7252 77 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
5cf8ca22 78 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
de7906c3
AG		 79 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
80 vcpu->arch.shared->srr1);
bbf45ba5
HB		 81
82 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
83
84 for (i = 0; i < 32; i += 4) {
5cf8ca22 85 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i,
8e5b26b5
AG		 86 kvmppc_get_gpr(vcpu, i),
87 kvmppc_get_gpr(vcpu, i+1),
88 kvmppc_get_gpr(vcpu, i+2),
89 kvmppc_get_gpr(vcpu, i+3));
bbf45ba5
HB		 90 }
91}
92
4cd35f67
SW		 93#ifdef CONFIG_SPE
94void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
95{
96 preempt_disable();
97 enable_kernel_spe();
98 kvmppc_save_guest_spe(vcpu);
99 vcpu->arch.shadow_msr &= ~MSR_SPE;
100 preempt_enable();
101}
102
103static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
104{
105 preempt_disable();
106 enable_kernel_spe();
107 kvmppc_load_guest_spe(vcpu);
108 vcpu->arch.shadow_msr |= MSR_SPE;
109 preempt_enable();
110}
111
112static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
113{
114 if (vcpu->arch.shared->msr & MSR_SPE) {
115 if (!(vcpu->arch.shadow_msr & MSR_SPE))
116 kvmppc_vcpu_enable_spe(vcpu);
117 } else if (vcpu->arch.shadow_msr & MSR_SPE) {
118 kvmppc_vcpu_disable_spe(vcpu);
119 }
120}
121#else
122static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
123{
124}
125#endif
126
3efc7da6
MC		 127/*
128 * Load up guest vcpu FP state if it's needed.
129 * It also set the MSR_FP in thread so that host know
130 * we're holding FPU, and then host can help to save
131 * guest vcpu FP state if other threads require to use FPU.
132 * This simulates an FP unavailable fault.
133 *
134 * It requires to be called with preemption disabled.
135 */
136static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
137{
138#ifdef CONFIG_PPC_FPU
139 if (!(current->thread.regs->msr & MSR_FP)) {
140 enable_kernel_fp();
141 load_fp_state(&vcpu->arch.fp);
142 current->thread.fp_save_area = &vcpu->arch.fp;
143 current->thread.regs->msr |= MSR_FP;
144 }
145#endif
146}
147
148/*
149 * Save guest vcpu FP state into thread.
150 * It requires to be called with preemption disabled.
151 */
152static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
153{
154#ifdef CONFIG_PPC_FPU
155 if (current->thread.regs->msr & MSR_FP)
156 giveup_fpu(current);
157 current->thread.fp_save_area = NULL;
158#endif
159}
160
7a08c274
AG		 161static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
162{
163#if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
164 /* We always treat the FP bit as enabled from the host
165 perspective, so only need to adjust the shadow MSR */
166 vcpu->arch.shadow_msr &= ~MSR_FP;
167 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP;
168#endif
169}
170
95d80a29
MC		 171/*
172 * Simulate AltiVec unavailable fault to load guest state
173 * from thread to AltiVec unit.
174 * It requires to be called with preemption disabled.
175 */
176static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu)
177{
178#ifdef CONFIG_ALTIVEC
179 if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
180 if (!(current->thread.regs->msr & MSR_VEC)) {
181 enable_kernel_altivec();
182 load_vr_state(&vcpu->arch.vr);
183 current->thread.vr_save_area = &vcpu->arch.vr;
184 current->thread.regs->msr |= MSR_VEC;
185 }
186 }
187#endif
188}
189
190/*
191 * Save guest vcpu AltiVec state into thread.
192 * It requires to be called with preemption disabled.
193 */
194static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu)
195{
196#ifdef CONFIG_ALTIVEC
197 if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
198 if (current->thread.regs->msr & MSR_VEC)
199 giveup_altivec(current);
200 current->thread.vr_save_area = NULL;
201 }
202#endif
203}
204
ce11e48b
BB		 205static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
206{
207 /* Synchronize guest's desire to get debug interrupts into shadow MSR */
208#ifndef CONFIG_KVM_BOOKE_HV
209 vcpu->arch.shadow_msr &= ~MSR_DE;
210 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE;
211#endif
212
213 /* Force enable debug interrupts when user space wants to debug */
214 if (vcpu->guest_debug) {
215#ifdef CONFIG_KVM_BOOKE_HV
216 /*
217 * Since there is no shadow MSR, sync MSR_DE into the guest
218 * visible MSR.
219 */
220 vcpu->arch.shared->msr |= MSR_DE;
221#else
222 vcpu->arch.shadow_msr |= MSR_DE;
223 vcpu->arch.shared->msr &= ~MSR_DE;
224#endif
225 }
226}
227
dd9ebf1f
LY		 228/*
229 * Helper function for "full" MSR writes. No need to call this if only
230 * EE/CE/ME/DE/RI are changing.
231 */
4cd35f67
SW		 232void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
233{
dd9ebf1f 234 u32 old_msr = vcpu->arch.shared->msr;
4cd35f67 235
d30f6e48
SW		 236#ifdef CONFIG_KVM_BOOKE_HV
237 new_msr |= MSR_GS;
238#endif
239
4cd35f67
SW		 240 vcpu->arch.shared->msr = new_msr;
241
dd9ebf1f 242 kvmppc_mmu_msr_notify(vcpu, old_msr);
4cd35f67 243 kvmppc_vcpu_sync_spe(vcpu);
7a08c274 244 kvmppc_vcpu_sync_fpu(vcpu);
ce11e48b 245 kvmppc_vcpu_sync_debug(vcpu);
4cd35f67
SW		 246}
247
d4cf3892
HB		 248static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
249 unsigned int priority)
9dd921cf 250{
6346046c 251 trace_kvm_booke_queue_irqprio(vcpu, priority);
9dd921cf
HB		 252 set_bit(priority, &vcpu->arch.pending_exceptions);
253}
254
8de12015
AG		 255void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
256 ulong dear_flags, ulong esr_flags)
9dd921cf 257{
daf5e271
LY		 258 vcpu->arch.queued_dear = dear_flags;
259 vcpu->arch.queued_esr = esr_flags;
260 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
261}
262
8de12015
AG		 263void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
264 ulong dear_flags, ulong esr_flags)
daf5e271
LY		 265{
266 vcpu->arch.queued_dear = dear_flags;
267 vcpu->arch.queued_esr = esr_flags;
268 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
269}
270
8de12015
AG		 271void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu)
272{
273 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
274}
275
276void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong esr_flags)
daf5e271
LY		 277{
278 vcpu->arch.queued_esr = esr_flags;
279 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE);
280}
281
011da899
AG		 282static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags,
283 ulong esr_flags)
284{
285 vcpu->arch.queued_dear = dear_flags;
286 vcpu->arch.queued_esr = esr_flags;
287 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT);
288}
289
daf5e271
LY		 290void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
291{
292 vcpu->arch.queued_esr = esr_flags;
d4cf3892 293 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
9dd921cf
HB		 294}
295
296void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
297{
d4cf3892 298 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
9dd921cf
HB		 299}
300
301int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
302{
d4cf3892 303 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
9dd921cf
HB		 304}
305
7706664d
AG		 306void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu)
307{
308 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
309}
310
9dd921cf
HB		 311void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
312 struct kvm_interrupt *irq)
313{
c5335f17
AG		 314 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL;
315
316 if (irq->irq == KVM_INTERRUPT_SET_LEVEL)
317 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL;
318
319 kvmppc_booke_queue_irqprio(vcpu, prio);
9dd921cf
HB		 320}
321
4fe27d2a 322void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
4496f974
AG		 323{
324 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
c5335f17 325 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
4496f974
AG		 326}
327
f61c94bb
BB		 328static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu)
329{
330 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG);
331}
332
333static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
334{
335 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
336}
337
2f699a59
BB		 338void kvmppc_core_queue_debug(struct kvm_vcpu *vcpu)
339{
340 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DEBUG);
341}
342
343void kvmppc_core_dequeue_debug(struct kvm_vcpu *vcpu)
344{
345 clear_bit(BOOKE_IRQPRIO_DEBUG, &vcpu->arch.pending_exceptions);
346}
347
d30f6e48
SW		 348static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
349{
31579eea
BB		 350 kvmppc_set_srr0(vcpu, srr0);
351 kvmppc_set_srr1(vcpu, srr1);
d30f6e48
SW		 352}
353
354static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
355{
356 vcpu->arch.csrr0 = srr0;
357 vcpu->arch.csrr1 = srr1;
358}
359
360static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
361{
362 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
363 vcpu->arch.dsrr0 = srr0;
364 vcpu->arch.dsrr1 = srr1;
365 } else {
366 set_guest_csrr(vcpu, srr0, srr1);
367 }
368}
369
370static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
371{
372 vcpu->arch.mcsrr0 = srr0;
373 vcpu->arch.mcsrr1 = srr1;
374}
375
d4cf3892
HB		 376/* Deliver the interrupt of the corresponding priority, if possible. */
377static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
378 unsigned int priority)
bbf45ba5 379{
d4cf3892 380 int allowed = 0;
79300f8c 381 ulong msr_mask = 0;
1c810636 382 bool update_esr = false, update_dear = false, update_epr = false;
5c6cedf4
AG		 383 ulong crit_raw = vcpu->arch.shared->critical;
384 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
385 bool crit;
c5335f17 386 bool keep_irq = false;
d30f6e48 387 enum int_class int_class;
95e90b43 388 ulong new_msr = vcpu->arch.shared->msr;
5c6cedf4
AG		 389
390 /* Truncate crit indicators in 32 bit mode */
391 if (!(vcpu->arch.shared->msr & MSR_SF)) {
392 crit_raw &= 0xffffffff;
393 crit_r1 &= 0xffffffff;
394 }
395
396 /* Critical section when crit == r1 */
397 crit = (crit_raw == crit_r1);
398 /* ... and we're in supervisor mode */
399 crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
d4cf3892 400
c5335f17
AG		 401 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
402 priority = BOOKE_IRQPRIO_EXTERNAL;
403 keep_irq = true;
404 }
405
5df554ad 406 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
1c810636
AG		 407 update_epr = true;
408
d4cf3892 409 switch (priority) {
d4cf3892 410 case BOOKE_IRQPRIO_DTLB_MISS:
d4cf3892 411 case BOOKE_IRQPRIO_DATA_STORAGE:
011da899 412 case BOOKE_IRQPRIO_ALIGNMENT:
daf5e271
LY		 413 update_dear = true;
414 /* fall through */
d4cf3892 415 case BOOKE_IRQPRIO_INST_STORAGE:
daf5e271
LY		 416 case BOOKE_IRQPRIO_PROGRAM:
417 update_esr = true;
418 /* fall through */
419 case BOOKE_IRQPRIO_ITLB_MISS:
420 case BOOKE_IRQPRIO_SYSCALL:
d4cf3892 421 case BOOKE_IRQPRIO_FP_UNAVAIL:
95d80a29 422#ifdef CONFIG_SPE_POSSIBLE
bb3a8a17
HB		 423 case BOOKE_IRQPRIO_SPE_UNAVAIL:
424 case BOOKE_IRQPRIO_SPE_FP_DATA:
425 case BOOKE_IRQPRIO_SPE_FP_ROUND:
95d80a29
MC		 426#endif
427#ifdef CONFIG_ALTIVEC
428 case BOOKE_IRQPRIO_ALTIVEC_UNAVAIL:
429 case BOOKE_IRQPRIO_ALTIVEC_ASSIST:
430#endif
d4cf3892 431 case BOOKE_IRQPRIO_AP_UNAVAIL:
d4cf3892 432 allowed = 1;
79300f8c 433 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 434 int_class = INT_CLASS_NONCRIT;
bbf45ba5 435 break;
f61c94bb 436 case BOOKE_IRQPRIO_WATCHDOG:
d4cf3892 437 case BOOKE_IRQPRIO_CRITICAL:
4ab96919 438 case BOOKE_IRQPRIO_DBELL_CRIT:
666e7252 439 allowed = vcpu->arch.shared->msr & MSR_CE;
d30f6e48 440 allowed = allowed && !crit;
79300f8c 441 msr_mask = MSR_ME;
d30f6e48 442 int_class = INT_CLASS_CRIT;
bbf45ba5 443 break;
d4cf3892 444 case BOOKE_IRQPRIO_MACHINE_CHECK:
666e7252 445 allowed = vcpu->arch.shared->msr & MSR_ME;
d30f6e48 446 allowed = allowed && !crit;
d30f6e48 447 int_class = INT_CLASS_MC;
bbf45ba5 448 break;
d4cf3892
HB		 449 case BOOKE_IRQPRIO_DECREMENTER:
450 case BOOKE_IRQPRIO_FIT:
dfd4d47e
SW		 451 keep_irq = true;
452 /* fall through */
453 case BOOKE_IRQPRIO_EXTERNAL:
4ab96919 454 case BOOKE_IRQPRIO_DBELL:
666e7252 455 allowed = vcpu->arch.shared->msr & MSR_EE;
5c6cedf4 456 allowed = allowed && !crit;
79300f8c 457 msr_mask = MSR_CE | MSR_ME | MSR_DE;
d30f6e48 458 int_class = INT_CLASS_NONCRIT;
bbf45ba5 459 break;
d4cf3892 460 case BOOKE_IRQPRIO_DEBUG:
666e7252 461 allowed = vcpu->arch.shared->msr & MSR_DE;
d30f6e48 462 allowed = allowed && !crit;
79300f8c 463 msr_mask = MSR_ME;
9fee7563
BB		 464 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
465 int_class = INT_CLASS_DBG;
466 else
467 int_class = INT_CLASS_CRIT;
468
bbf45ba5 469 break;
bbf45ba5
HB		 470 }
471
d4cf3892 472 if (allowed) {
d30f6e48
SW		 473 switch (int_class) {
474 case INT_CLASS_NONCRIT:
475 set_guest_srr(vcpu, vcpu->arch.pc,
476 vcpu->arch.shared->msr);
477 break;
478 case INT_CLASS_CRIT:
479 set_guest_csrr(vcpu, vcpu->arch.pc,
480 vcpu->arch.shared->msr);
481 break;
482 case INT_CLASS_DBG:
483 set_guest_dsrr(vcpu, vcpu->arch.pc,
484 vcpu->arch.shared->msr);
485 break;
486 case INT_CLASS_MC:
487 set_guest_mcsrr(vcpu, vcpu->arch.pc,
488 vcpu->arch.shared->msr);
489 break;
490 }
491
d4cf3892 492 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
daf5e271 493 if (update_esr == true)
dc168549 494 kvmppc_set_esr(vcpu, vcpu->arch.queued_esr);
daf5e271 495 if (update_dear == true)
a5414d4b 496 kvmppc_set_dar(vcpu, vcpu->arch.queued_dear);
5df554ad
SW		 497 if (update_epr == true) {
498 if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
499 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
eb1e4f43
SW		 500 else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) {
501 BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC);
502 kvmppc_mpic_set_epr(vcpu);
503 }
5df554ad 504 }
95e90b43
MC		 505
506 new_msr &= msr_mask;
507#if defined(CONFIG_64BIT)
508 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
509 new_msr |= MSR_CM;
510#endif
511 kvmppc_set_msr(vcpu, new_msr);
bbf45ba5 512
c5335f17
AG		 513 if (!keep_irq)
514 clear_bit(priority, &vcpu->arch.pending_exceptions);
bbf45ba5
HB		 515 }
516
d30f6e48
SW		 517#ifdef CONFIG_KVM_BOOKE_HV
518 /*
519 * If an interrupt is pending but masked, raise a guest doorbell
520 * so that we are notified when the guest enables the relevant
521 * MSR bit.
522 */
523 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
524 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
525 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
526 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
527 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
528 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
529#endif
530
d4cf3892 531 return allowed;
bbf45ba5
HB		 532}
533
f61c94bb
BB		 534/*
535 * Return the number of jiffies until the next timeout. If the timeout is
536 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA
537 * because the larger value can break the timer APIs.
538 */
539static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu)
540{
541 u64 tb, wdt_tb, wdt_ticks = 0;
542 u64 nr_jiffies = 0;
543 u32 period = TCR_GET_WP(vcpu->arch.tcr);
544
545 wdt_tb = 1ULL << (63 - period);
546 tb = get_tb();
547 /*
548 * The watchdog timeout will hapeen when TB bit corresponding
549 * to watchdog will toggle from 0 to 1.
550 */
551 if (tb & wdt_tb)
552 wdt_ticks = wdt_tb;
553
554 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1));
555
556 /* Convert timebase ticks to jiffies */
557 nr_jiffies = wdt_ticks;
558
559 if (do_div(nr_jiffies, tb_ticks_per_jiffy))
560 nr_jiffies++;
561
562 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA);
563}
564
565static void arm_next_watchdog(struct kvm_vcpu *vcpu)
566{
567 unsigned long nr_jiffies;
568 unsigned long flags;
569
570 /*
571 * If TSR_ENW and TSR_WIS are not set then no need to exit to
572 * userspace, so clear the KVM_REQ_WATCHDOG request.
573 */
574 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS))
575 clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests);
576
577 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags);
578 nr_jiffies = watchdog_next_timeout(vcpu);
579 /*
580 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA
581 * then do not run the watchdog timer as this can break timer APIs.
582 */
583 if (nr_jiffies < NEXT_TIMER_MAX_DELTA)
584 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies);
585 else
586 del_timer(&vcpu->arch.wdt_timer);
587 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
588}
589
590void kvmppc_watchdog_func(unsigned long data)
591{
592 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
593 u32 tsr, new_tsr;
594 int final;
595
596 do {
597 new_tsr = tsr = vcpu->arch.tsr;
598 final = 0;
599
600 /* Time out event */
601 if (tsr & TSR_ENW) {
602 if (tsr & TSR_WIS)
603 final = 1;
604 else
605 new_tsr = tsr | TSR_WIS;
606 } else {
607 new_tsr = tsr | TSR_ENW;
608 }
609 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr);
610
611 if (new_tsr & TSR_WIS) {
612 smp_wmb();
613 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
614 kvm_vcpu_kick(vcpu);
615 }
616
617 /*
618 * If this is final watchdog expiry and some action is required
619 * then exit to userspace.
620 */
621 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) &&
622 vcpu->arch.watchdog_enabled) {
623 smp_wmb();
624 kvm_make_request(KVM_REQ_WATCHDOG, vcpu);
625 kvm_vcpu_kick(vcpu);
626 }
627
628 /*
629 * Stop running the watchdog timer after final expiration to
630 * prevent the host from being flooded with timers if the
631 * guest sets a short period.
632 * Timers will resume when TSR/TCR is updated next time.
633 */
634 if (!final)
635 arm_next_watchdog(vcpu);
636}
637
dfd4d47e
SW		 638static void update_timer_ints(struct kvm_vcpu *vcpu)
639{
640 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
641 kvmppc_core_queue_dec(vcpu);
642 else
643 kvmppc_core_dequeue_dec(vcpu);
f61c94bb
BB		 644
645 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS))
646 kvmppc_core_queue_watchdog(vcpu);
647 else
648 kvmppc_core_dequeue_watchdog(vcpu);
dfd4d47e
SW		 649}
650
c59a6a3e 651static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
bbf45ba5
HB		 652{
653 unsigned long *pending = &vcpu->arch.pending_exceptions;
bbf45ba5
HB		 654 unsigned int priority;
655
9ab80843 656 priority = __ffs(*pending);
8b3a00fc 657 while (priority < BOOKE_IRQPRIO_MAX) {
d4cf3892 658 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
bbf45ba5 659 break;
bbf45ba5
HB		 660
661 priority = find_next_bit(pending,
662 BITS_PER_BYTE * sizeof(*pending),
663 priority + 1);
664 }
90bba358
AG		 665
666 /* Tell the guest about our interrupt status */
29ac26ef 667 vcpu->arch.shared->int_pending = !!*pending;
bbf45ba5
HB		 668}
669
c59a6a3e 670/* Check pending exceptions and deliver one, if possible. */
a8e4ef84 671int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
c59a6a3e 672{
a8e4ef84 673 int r = 0;
c59a6a3e
SW		 674 WARN_ON_ONCE(!irqs_disabled());
675
676 kvmppc_core_check_exceptions(vcpu);
677
b8c649a9
AG		 678 if (vcpu->requests) {
679 /* Exception delivery raised request; start over */
680 return 1;
681 }
682
c59a6a3e
SW		 683 if (vcpu->arch.shared->msr & MSR_WE) {
684 local_irq_enable();
685 kvm_vcpu_block(vcpu);
966cd0f3 686 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6c85f52b 687 hard_irq_disable();
c59a6a3e
SW		 688
689 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
a8e4ef84 690 r = 1;
c59a6a3e 691 };
a8e4ef84
AG		 692
693 return r;
694}
695
7c973a2e 696int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
4ffc6356 697{
7c973a2e
AG		 698 int r = 1; /* Indicate we want to get back into the guest */
699
2d8185d4
AG		 700 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu))
701 update_timer_ints(vcpu);
862d31f7 702#if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
2d8185d4
AG		 703 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
704 kvmppc_core_flush_tlb(vcpu);
862d31f7 705#endif
7c973a2e 706
f61c94bb
BB		 707 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) {
708 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG;
709 r = 0;
710 }
711
1c810636
AG		 712 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) {
713 vcpu->run->epr.epr = 0;
714 vcpu->arch.epr_needed = true;
715 vcpu->run->exit_reason = KVM_EXIT_EPR;
716 r = 0;
717 }
718
7c973a2e 719 return r;
4ffc6356
AG		 720}
721
df6909e5
PM		 722int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
723{
7ee78855 724 int ret, s;
f5f97210 725 struct debug_reg debug;
df6909e5 726
af8f38b3
AG		 727 if (!vcpu->arch.sane) {
728 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
729 return -EINVAL;
730 }
731
7ee78855
AG		 732 s = kvmppc_prepare_to_enter(vcpu);
733 if (s <= 0) {
7ee78855 734 ret = s;
1d1ef222
SW		 735 goto out;
736 }
6c85f52b 737 /* interrupts now hard-disabled */
1d1ef222 738
8fae845f
SW		 739#ifdef CONFIG_PPC_FPU
740 /* Save userspace FPU state in stack */
741 enable_kernel_fp();
8fae845f
SW		 742
743 /*
744 * Since we can't trap on MSR_FP in GS-mode, we consider the guest
3efc7da6 745 * as always using the FPU.
8fae845f 746 */
8fae845f
SW		 747 kvmppc_load_guest_fp(vcpu);
748#endif
749
95d80a29
MC		 750#ifdef CONFIG_ALTIVEC
751 /* Save userspace AltiVec state in stack */
752 if (cpu_has_feature(CPU_FTR_ALTIVEC))
753 enable_kernel_altivec();
754 /*
755 * Since we can't trap on MSR_VEC in GS-mode, we consider the guest
756 * as always using the AltiVec.
757 */
758 kvmppc_load_guest_altivec(vcpu);
759#endif
760
ce11e48b 761 /* Switch to guest debug context */
348ba710 762 debug = vcpu->arch.dbg_reg;
f5f97210
SW		 763 switch_booke_debug_regs(&debug);
764 debug = current->thread.debug;
348ba710 765 current->thread.debug = vcpu->arch.dbg_reg;
ce11e48b 766
08c9a188 767 vcpu->arch.pgdir = current->mm->pgd;
5f1c248f 768 kvmppc_fix_ee_before_entry();
f8941fbe 769
df6909e5 770 ret = __kvmppc_vcpu_run(kvm_run, vcpu);
8fae845f 771
24afa37b
AG		 772 /* No need for kvm_guest_exit. It's done in handle_exit.
773 We also get here with interrupts enabled. */
774
ce11e48b 775 /* Switch back to user space debug context */
f5f97210
SW		 776 switch_booke_debug_regs(&debug);
777 current->thread.debug = debug;
ce11e48b 778
8fae845f
SW		 779#ifdef CONFIG_PPC_FPU
780 kvmppc_save_guest_fp(vcpu);
8fae845f
SW		 781#endif
782
95d80a29
MC		 783#ifdef CONFIG_ALTIVEC
784 kvmppc_save_guest_altivec(vcpu);
785#endif
786
1d1ef222 787out:
d69c6436 788 vcpu->mode = OUTSIDE_GUEST_MODE;
df6909e5
PM		 789 return ret;
790}
791
d30f6e48
SW		 792static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
793{
794 enum emulation_result er;
795
796 er = kvmppc_emulate_instruction(run, vcpu);
797 switch (er) {
798 case EMULATE_DONE:
799 /* don't overwrite subtypes, just account kvm_stats */
800 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
801 /* Future optimization: only reload non-volatiles if
802 * they were actually modified by emulation. */
803 return RESUME_GUEST_NV;
804
51f04726
MC		 805 case EMULATE_AGAIN:
806 return RESUME_GUEST;
807
d30f6e48 808 case EMULATE_FAIL:
d30f6e48
SW		 809 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
810 __func__, vcpu->arch.pc, vcpu->arch.last_inst);
811 /* For debugging, encode the failing instruction and
812 * report it to userspace. */
813 run->hw.hardware_exit_reason = ~0ULL << 32;
814 run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
d1ff5499 815 kvmppc_core_queue_program(vcpu, ESR_PIL);
d30f6e48
SW		 816 return RESUME_HOST;
817
9b4f5308
BB		 818 case EMULATE_EXIT_USER:
819 return RESUME_HOST;
820
d30f6e48
SW		 821 default:
822 BUG();
823 }
824}
825
ce11e48b
BB		 826static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu)
827{
348ba710 828 struct debug_reg *dbg_reg = &(vcpu->arch.dbg_reg);
ce11e48b
BB		 829 u32 dbsr = vcpu->arch.dbsr;
830
2f699a59
BB		 831 if (vcpu->guest_debug == 0) {
832 /*
833 * Debug resources belong to Guest.
834 * Imprecise debug event is not injected
835 */
836 if (dbsr & DBSR_IDE) {
837 dbsr &= ~DBSR_IDE;
838 if (!dbsr)
839 return RESUME_GUEST;
840 }
841
842 if (dbsr && (vcpu->arch.shared->msr & MSR_DE) &&
843 (vcpu->arch.dbg_reg.dbcr0 & DBCR0_IDM))
844 kvmppc_core_queue_debug(vcpu);
845
846 /* Inject a program interrupt if trap debug is not allowed */
847 if ((dbsr & DBSR_TIE) && !(vcpu->arch.shared->msr & MSR_DE))
848 kvmppc_core_queue_program(vcpu, ESR_PTR);
849
850 return RESUME_GUEST;
851 }
852
853 /*
854 * Debug resource owned by userspace.
855 * Clear guest dbsr (vcpu->arch.dbsr)
856 */
2190991e 857 vcpu->arch.dbsr = 0;
ce11e48b
BB		 858 run->debug.arch.status = 0;
859 run->debug.arch.address = vcpu->arch.pc;
860
861 if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) {
862 run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT;
863 } else {
864 if (dbsr & (DBSR_DAC1W | DBSR_DAC2W))
865 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE;
866 else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R))
867 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ;
868 if (dbsr & (DBSR_DAC1R | DBSR_DAC1W))
869 run->debug.arch.address = dbg_reg->dac1;
870 else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W))
871 run->debug.arch.address = dbg_reg->dac2;
872 }
873
874 return RESUME_HOST;
875}
876
4e642ccb 877static void kvmppc_fill_pt_regs(struct pt_regs *regs)
bbf45ba5 878{
4e642ccb 879 ulong r1, ip, msr, lr;
bbf45ba5 880
4e642ccb
AG		 881 asm("mr %0, 1" : "=r"(r1));
882 asm("mflr %0" : "=r"(lr));
883 asm("mfmsr %0" : "=r"(msr));
884 asm("bl 1f; 1: mflr %0" : "=r"(ip));
885
886 memset(regs, 0, sizeof(*regs));
887 regs->gpr[1] = r1;
888 regs->nip = ip;
889 regs->msr = msr;
890 regs->link = lr;
891}
892
6328e593
BB		 893/*
894 * For interrupts needed to be handled by host interrupt handlers,
895 * corresponding host handler are called from here in similar way
896 * (but not exact) as they are called from low level handler
897 * (such as from arch/powerpc/kernel/head_fsl_booke.S).
898 */
4e642ccb
AG		 899static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
900 unsigned int exit_nr)
901{
902 struct pt_regs regs;
73e75b41 903
d30f6e48
SW		 904 switch (exit_nr) {
905 case BOOKE_INTERRUPT_EXTERNAL:
4e642ccb
AG		 906 kvmppc_fill_pt_regs(&regs);
907 do_IRQ(&regs);
d30f6e48 908 break;
d30f6e48 909 case BOOKE_INTERRUPT_DECREMENTER:
4e642ccb
AG		 910 kvmppc_fill_pt_regs(&regs);
911 timer_interrupt(&regs);
d30f6e48 912 break;
5f17ce8b 913#if defined(CONFIG_PPC_DOORBELL)
d30f6e48 914 case BOOKE_INTERRUPT_DOORBELL:
4e642ccb
AG		 915 kvmppc_fill_pt_regs(&regs);
916 doorbell_exception(&regs);
d30f6e48
SW		 917 break;
918#endif
919 case BOOKE_INTERRUPT_MACHINE_CHECK:
920 /* FIXME */
921 break;
7cc1e8ee
AG		 922 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
923 kvmppc_fill_pt_regs(&regs);
924 performance_monitor_exception(&regs);
925 break;
6328e593
BB		 926 case BOOKE_INTERRUPT_WATCHDOG:
927 kvmppc_fill_pt_regs(&regs);
928#ifdef CONFIG_BOOKE_WDT
929 WatchdogException(&regs);
930#else
931 unknown_exception(&regs);
932#endif
933 break;
934 case BOOKE_INTERRUPT_CRITICAL:
935 unknown_exception(&regs);
936 break;
ce11e48b
BB		 937 case BOOKE_INTERRUPT_DEBUG:
938 /* Save DBSR before preemption is enabled */
939 vcpu->arch.dbsr = mfspr(SPRN_DBSR);
940 kvmppc_clear_dbsr();
941 break;
d30f6e48 942 }
4e642ccb
AG		 943}
944
f5250471
MC		 945static int kvmppc_resume_inst_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
946 enum emulation_result emulated, u32 last_inst)
947{
948 switch (emulated) {
949 case EMULATE_AGAIN:
950 return RESUME_GUEST;
951
952 case EMULATE_FAIL:
953 pr_debug("%s: load instruction from guest address %lx failed\n",
954 __func__, vcpu->arch.pc);
955 /* For debugging, encode the failing instruction and
956 * report it to userspace. */
957 run->hw.hardware_exit_reason = ~0ULL << 32;
958 run->hw.hardware_exit_reason |= last_inst;
959 kvmppc_core_queue_program(vcpu, ESR_PIL);
960 return RESUME_HOST;
961
962 default:
963 BUG();
964 }
965}
966
4e642ccb
AG		 967/**
968 * kvmppc_handle_exit
969 *
970 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
971 */
972int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
973 unsigned int exit_nr)
974{
975 int r = RESUME_HOST;
7ee78855 976 int s;
f1e89028 977 int idx;
f5250471
MC		 978 u32 last_inst = KVM_INST_FETCH_FAILED;
979 enum emulation_result emulated = EMULATE_DONE;
4e642ccb
AG		 980
981 /* update before a new last_exit_type is rewritten */
982 kvmppc_update_timing_stats(vcpu);
983
984 /* restart interrupts if they were meant for the host */
985 kvmppc_restart_interrupt(vcpu, exit_nr);
d30f6e48 986
f5250471
MC		 987 /*
988 * get last instruction before beeing preempted
989 * TODO: for e6500 check also BOOKE_INTERRUPT_LRAT_ERROR & ESR_DATA
990 */
991 switch (exit_nr) {
992 case BOOKE_INTERRUPT_DATA_STORAGE:
993 case BOOKE_INTERRUPT_DTLB_MISS:
994 case BOOKE_INTERRUPT_HV_PRIV:
995 emulated = kvmppc_get_last_inst(vcpu, false, &last_inst);
996 break;
997 default:
998 break;
999 }
1000
bbf45ba5
HB		 1001 local_irq_enable();
1002
97c95059 1003 trace_kvm_exit(exit_nr, vcpu);
706fb730 1004 kvm_guest_exit();
97c95059 1005
bbf45ba5
HB		 1006 run->exit_reason = KVM_EXIT_UNKNOWN;
1007 run->ready_for_interrupt_injection = 1;
1008
f5250471
MC		 1009 if (emulated != EMULATE_DONE) {
1010 r = kvmppc_resume_inst_load(run, vcpu, emulated, last_inst);
1011 goto out;
1012 }
1013
bbf45ba5
HB		 1014 switch (exit_nr) {
1015 case BOOKE_INTERRUPT_MACHINE_CHECK:
c35c9d84
AG		 1016 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
1017 kvmppc_dump_vcpu(vcpu);
1018 /* For debugging, send invalid exit reason to user space */
1019 run->hw.hardware_exit_reason = ~1ULL << 32;
1020 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR);
1021 r = RESUME_HOST;
bbf45ba5
HB		 1022 break;
1023
1024 case BOOKE_INTERRUPT_EXTERNAL:
7b701591 1025 kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
1b6766c7
HB		 1026 r = RESUME_GUEST;
1027 break;
1028
bbf45ba5 1029 case BOOKE_INTERRUPT_DECREMENTER:
7b701591 1030 kvmppc_account_exit(vcpu, DEC_EXITS);
bbf45ba5
HB		 1031 r = RESUME_GUEST;
1032 break;
1033
6328e593
BB		 1034 case BOOKE_INTERRUPT_WATCHDOG:
1035 r = RESUME_GUEST;
1036 break;
1037
d30f6e48
SW		 1038 case BOOKE_INTERRUPT_DOORBELL:
1039 kvmppc_account_exit(vcpu, DBELL_EXITS);
d30f6e48
SW		 1040 r = RESUME_GUEST;
1041 break;
1042
1043 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
1044 kvmppc_account_exit(vcpu, GDBELL_EXITS);
1045
1046 /*
1047 * We are here because there is a pending guest interrupt
1048 * which could not be delivered as MSR_CE or MSR_ME was not
1049 * set. Once we break from here we will retry delivery.
1050 */
1051 r = RESUME_GUEST;
1052 break;
1053
1054 case BOOKE_INTERRUPT_GUEST_DBELL:
1055 kvmppc_account_exit(vcpu, GDBELL_EXITS);
1056
1057 /*
1058 * We are here because there is a pending guest interrupt
1059 * which could not be delivered as MSR_EE was not set. Once
1060 * we break from here we will retry delivery.
1061 */
1062 r = RESUME_GUEST;
1063 break;
1064
95f2e921
AG		 1065 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
1066 r = RESUME_GUEST;
1067 break;
1068
d30f6e48
SW		 1069 case BOOKE_INTERRUPT_HV_PRIV:
1070 r = emulation_exit(run, vcpu);
1071 break;
1072
bbf45ba5 1073 case BOOKE_INTERRUPT_PROGRAM:
d30f6e48 1074 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
0268597c
AG		 1075 /*
1076 * Program traps generated by user-level software must
1077 * be handled by the guest kernel.
1078 *
1079 * In GS mode, hypervisor privileged instructions trap
1080 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are
1081 * actual program interrupts, handled by the guest.
1082 */
daf5e271 1083 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr);
bbf45ba5 1084 r = RESUME_GUEST;
7b701591 1085 kvmppc_account_exit(vcpu, USR_PR_INST);
bbf45ba5
HB		 1086 break;
1087 }
1088
d30f6e48 1089 r = emulation_exit(run, vcpu);
bbf45ba5
HB		 1090 break;
1091
de368dce 1092 case BOOKE_INTERRUPT_FP_UNAVAIL:
d4cf3892 1093 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
7b701591 1094 kvmppc_account_exit(vcpu, FP_UNAVAIL);
de368dce
CE		 1095 r = RESUME_GUEST;
1096 break;
1097
4cd35f67
SW		 1098#ifdef CONFIG_SPE
1099 case BOOKE_INTERRUPT_SPE_UNAVAIL: {
1100 if (vcpu->arch.shared->msr & MSR_SPE)
1101 kvmppc_vcpu_enable_spe(vcpu);
1102 else
1103 kvmppc_booke_queue_irqprio(vcpu,
1104 BOOKE_IRQPRIO_SPE_UNAVAIL);
bb3a8a17
HB		 1105 r = RESUME_GUEST;
1106 break;
4cd35f67 1107 }
bb3a8a17
HB		 1108
1109 case BOOKE_INTERRUPT_SPE_FP_DATA:
1110 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA);
1111 r = RESUME_GUEST;
1112 break;
1113
1114 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1115 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
1116 r = RESUME_GUEST;
1117 break;
95d80a29 1118#elif defined(CONFIG_SPE_POSSIBLE)
4cd35f67
SW		 1119 case BOOKE_INTERRUPT_SPE_UNAVAIL:
1120 /*
1121 * Guest wants SPE, but host kernel doesn't support it. Send
1122 * an "unimplemented operation" program check to the guest.
1123 */
1124 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV);
1125 r = RESUME_GUEST;
1126 break;
1127
1128 /*
1129 * These really should never happen without CONFIG_SPE,
1130 * as we should never enable the real MSR[SPE] in the guest.
1131 */
1132 case BOOKE_INTERRUPT_SPE_FP_DATA:
1133 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1134 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
1135 __func__, exit_nr, vcpu->arch.pc);
1136 run->hw.hardware_exit_reason = exit_nr;
1137 r = RESUME_HOST;
1138 break;
95d80a29
MC		 1139#endif /* CONFIG_SPE_POSSIBLE */
1140
1141/*
1142 * On cores with Vector category, KVM is loaded only if CONFIG_ALTIVEC,
1143 * see kvmppc_core_check_processor_compat().
1144 */
1145#ifdef CONFIG_ALTIVEC
1146 case BOOKE_INTERRUPT_ALTIVEC_UNAVAIL:
1147 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
1148 r = RESUME_GUEST;
1149 break;
1150
1151 case BOOKE_INTERRUPT_ALTIVEC_ASSIST:
1152 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_ASSIST);
1153 r = RESUME_GUEST;
1154 break;
4cd35f67 1155#endif
bb3a8a17 1156
bbf45ba5 1157 case BOOKE_INTERRUPT_DATA_STORAGE:
daf5e271
LY		 1158 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
1159 vcpu->arch.fault_esr);
7b701591 1160 kvmppc_account_exit(vcpu, DSI_EXITS);
bbf45ba5
HB		 1161 r = RESUME_GUEST;
1162 break;
1163
1164 case BOOKE_INTERRUPT_INST_STORAGE:
daf5e271 1165 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr);
7b701591 1166 kvmppc_account_exit(vcpu, ISI_EXITS);
bbf45ba5
HB		 1167 r = RESUME_GUEST;
1168 break;
1169
011da899
AG		 1170 case BOOKE_INTERRUPT_ALIGNMENT:
1171 kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear,
1172 vcpu->arch.fault_esr);
1173 r = RESUME_GUEST;
1174 break;
1175
d30f6e48
SW		 1176#ifdef CONFIG_KVM_BOOKE_HV
1177 case BOOKE_INTERRUPT_HV_SYSCALL:
1178 if (!(vcpu->arch.shared->msr & MSR_PR)) {
1179 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1180 } else {
1181 /*
1182 * hcall from guest userspace -- send privileged
1183 * instruction program check.
1184 */
1185 kvmppc_core_queue_program(vcpu, ESR_PPR);
1186 }
1187
1188 r = RESUME_GUEST;
1189 break;
1190#else
bbf45ba5 1191 case BOOKE_INTERRUPT_SYSCALL:
2a342ed5
AG		 1192 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1193 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
1194 /* KVM PV hypercalls */
1195 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1196 r = RESUME_GUEST;
1197 } else {
1198 /* Guest syscalls */
1199 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL);
1200 }
7b701591 1201 kvmppc_account_exit(vcpu, SYSCALL_EXITS);
bbf45ba5
HB		 1202 r = RESUME_GUEST;
1203 break;
d30f6e48 1204#endif
bbf45ba5
HB		 1205
1206 case BOOKE_INTERRUPT_DTLB_MISS: {
bbf45ba5 1207 unsigned long eaddr = vcpu->arch.fault_dear;
7924bd41 1208 int gtlb_index;
475e7cdd 1209 gpa_t gpaddr;
bbf45ba5
HB		 1210 gfn_t gfn;
1211
bf7ca4bd 1212#ifdef CONFIG_KVM_E500V2
a4cd8b23
SW		 1213 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1214 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1215 kvmppc_map_magic(vcpu);
1216 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1217 r = RESUME_GUEST;
1218
1219 break;
1220 }
1221#endif
1222
bbf45ba5 1223 /* Check the guest TLB. */
fa86b8dd 1224 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
7924bd41 1225 if (gtlb_index < 0) {
bbf45ba5 1226 /* The guest didn't have a mapping for it. */
daf5e271
LY		 1227 kvmppc_core_queue_dtlb_miss(vcpu,
1228 vcpu->arch.fault_dear,
1229 vcpu->arch.fault_esr);
b52a638c 1230 kvmppc_mmu_dtlb_miss(vcpu);
7b701591 1231 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1232 r = RESUME_GUEST;
1233 break;
1234 }
1235
f1e89028
SW		 1236 idx = srcu_read_lock(&vcpu->kvm->srcu);
1237
be8d1cae 1238 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
475e7cdd 1239 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1240
1241 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1242 /* The guest TLB had a mapping, but the shadow TLB
1243 * didn't, and it is RAM. This could be because:
1244 * a) the entry is mapping the host kernel, or
1245 * b) the guest used a large mapping which we're faking
1246 * Either way, we need to satisfy the fault without
1247 * invoking the guest. */
58a96214 1248 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
7b701591 1249 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
bbf45ba5
HB		 1250 r = RESUME_GUEST;
1251 } else {
1252 /* Guest has mapped and accessed a page which is not
1253 * actually RAM. */
475e7cdd 1254 vcpu->arch.paddr_accessed = gpaddr;
6020c0f6 1255 vcpu->arch.vaddr_accessed = eaddr;
bbf45ba5 1256 r = kvmppc_emulate_mmio(run, vcpu);
7b701591 1257 kvmppc_account_exit(vcpu, MMIO_EXITS);
bbf45ba5
HB		 1258 }
1259
f1e89028 1260 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB		 1261 break;
1262 }
1263
1264 case BOOKE_INTERRUPT_ITLB_MISS: {
bbf45ba5 1265 unsigned long eaddr = vcpu->arch.pc;
89168618 1266 gpa_t gpaddr;
bbf45ba5 1267 gfn_t gfn;
7924bd41 1268 int gtlb_index;
bbf45ba5
HB		 1269
1270 r = RESUME_GUEST;
1271
1272 /* Check the guest TLB. */
fa86b8dd 1273 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
7924bd41 1274 if (gtlb_index < 0) {
bbf45ba5 1275 /* The guest didn't have a mapping for it. */
d4cf3892 1276 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
b52a638c 1277 kvmppc_mmu_itlb_miss(vcpu);
7b701591 1278 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
bbf45ba5
HB		 1279 break;
1280 }
1281
7b701591 1282 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
bbf45ba5 1283
f1e89028
SW		 1284 idx = srcu_read_lock(&vcpu->kvm->srcu);
1285
be8d1cae 1286 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
89168618 1287 gfn = gpaddr >> PAGE_SHIFT;
bbf45ba5
HB		 1288
1289 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1290 /* The guest TLB had a mapping, but the shadow TLB
1291 * didn't. This could be because:
1292 * a) the entry is mapping the host kernel, or
1293 * b) the guest used a large mapping which we're faking
1294 * Either way, we need to satisfy the fault without
1295 * invoking the guest. */
58a96214 1296 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
bbf45ba5
HB		 1297 } else {
1298 /* Guest mapped and leaped at non-RAM! */
d4cf3892 1299 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
bbf45ba5
HB		 1300 }
1301
f1e89028 1302 srcu_read_unlock(&vcpu->kvm->srcu, idx);
bbf45ba5
HB		 1303 break;
1304 }
1305
6a0ab738 1306 case BOOKE_INTERRUPT_DEBUG: {
ce11e48b
BB		 1307 r = kvmppc_handle_debug(run, vcpu);
1308 if (r == RESUME_HOST)
1309 run->exit_reason = KVM_EXIT_DEBUG;
7b701591 1310 kvmppc_account_exit(vcpu, DEBUG_EXITS);
6a0ab738
HB		 1311 break;
1312 }
1313
bbf45ba5
HB		 1314 default:
1315 printk(KERN_EMERG "exit_nr %d\n", exit_nr);
1316 BUG();
1317 }
1318
f5250471 1319out:
a8e4ef84
AG		 1320 /*
1321 * To avoid clobbering exit_reason, only check for signals if we
1322 * aren't already exiting to userspace for some other reason.
1323 */
03660ba2 1324 if (!(r & RESUME_HOST)) {
7ee78855 1325 s = kvmppc_prepare_to_enter(vcpu);
6c85f52b 1326 if (s <= 0)
7ee78855 1327 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
6c85f52b
SW		 1328 else {
1329 /* interrupts now hard-disabled */
5f1c248f 1330 kvmppc_fix_ee_before_entry();
3efc7da6 1331 kvmppc_load_guest_fp(vcpu);
95d80a29 1332 kvmppc_load_guest_altivec(vcpu);
03660ba2 1333 }
bbf45ba5
HB		 1334 }
1335
1336 return r;
1337}
1338
d26f22c9
BB		 1339static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr)
1340{
1341 u32 old_tsr = vcpu->arch.tsr;
1342
1343 vcpu->arch.tsr = new_tsr;
1344
1345 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
1346 arm_next_watchdog(vcpu);
1347
1348 update_timer_ints(vcpu);
1349}
1350
bbf45ba5
HB		 1351/* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
1352int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1353{
082decf2 1354 int i;
af8f38b3 1355 int r;
082decf2 1356
bbf45ba5 1357 vcpu->arch.pc = 0;
b5904972 1358 vcpu->arch.shared->pir = vcpu->vcpu_id;
8e5b26b5 1359 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
d30f6e48 1360 kvmppc_set_msr(vcpu, 0);
bbf45ba5 1361
d30f6e48 1362#ifndef CONFIG_KVM_BOOKE_HV
ce11e48b 1363 vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS;
49dd2c49 1364 vcpu->arch.shadow_pid = 1;
d30f6e48
SW		 1365 vcpu->arch.shared->msr = 0;
1366#endif
49dd2c49 1367
082decf2
HB		 1368 /* Eye-catching numbers so we know if the guest takes an interrupt
1369 * before it's programmed its own IVPR/IVORs. */
bbf45ba5 1370 vcpu->arch.ivpr = 0x55550000;
082decf2
HB		 1371 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++)
1372 vcpu->arch.ivor[i] = 0x7700 | i * 4;
bbf45ba5 1373
73e75b41
HB		 1374 kvmppc_init_timing_stats(vcpu);
1375
af8f38b3
AG		 1376 r = kvmppc_core_vcpu_setup(vcpu);
1377 kvmppc_sanity_check(vcpu);
1378 return r;
bbf45ba5
HB		 1379}
1380
f61c94bb
BB		 1381int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
1382{
1383 /* setup watchdog timer once */
1384 spin_lock_init(&vcpu->arch.wdt_lock);
1385 setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
1386 (unsigned long)vcpu);
1387
2f699a59
BB		 1388 /*
1389 * Clear DBSR.MRR to avoid guest debug interrupt as
1390 * this is of host interest
1391 */
1392 mtspr(SPRN_DBSR, DBSR_MRR);
f61c94bb
BB		 1393 return 0;
1394}
1395
1396void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu)
1397{
1398 del_timer_sync(&vcpu->arch.wdt_timer);
1399}
1400
bbf45ba5
HB		 1401int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1402{
1403 int i;
1404
1405 regs->pc = vcpu->arch.pc;
992b5b29 1406 regs->cr = kvmppc_get_cr(vcpu);
bbf45ba5
HB		 1407 regs->ctr = vcpu->arch.ctr;
1408 regs->lr = vcpu->arch.lr;
992b5b29 1409 regs->xer = kvmppc_get_xer(vcpu);
666e7252 1410 regs->msr = vcpu->arch.shared->msr;
31579eea
BB		 1411 regs->srr0 = kvmppc_get_srr0(vcpu);
1412 regs->srr1 = kvmppc_get_srr1(vcpu);
bbf45ba5 1413 regs->pid = vcpu->arch.pid;
c1b8a01b
BB		 1414 regs->sprg0 = kvmppc_get_sprg0(vcpu);
1415 regs->sprg1 = kvmppc_get_sprg1(vcpu);
1416 regs->sprg2 = kvmppc_get_sprg2(vcpu);
1417 regs->sprg3 = kvmppc_get_sprg3(vcpu);
1418 regs->sprg4 = kvmppc_get_sprg4(vcpu);
1419 regs->sprg5 = kvmppc_get_sprg5(vcpu);
1420 regs->sprg6 = kvmppc_get_sprg6(vcpu);
1421 regs->sprg7 = kvmppc_get_sprg7(vcpu);
bbf45ba5
HB		 1422
1423 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
8e5b26b5 1424 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
bbf45ba5
HB		 1425
1426 return 0;
1427}
1428
1429int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1430{
1431 int i;
1432
1433 vcpu->arch.pc = regs->pc;
992b5b29 1434 kvmppc_set_cr(vcpu, regs->cr);
bbf45ba5
HB		 1435 vcpu->arch.ctr = regs->ctr;
1436 vcpu->arch.lr = regs->lr;
992b5b29 1437 kvmppc_set_xer(vcpu, regs->xer);
b8fd68ac 1438 kvmppc_set_msr(vcpu, regs->msr);
31579eea
BB		 1439 kvmppc_set_srr0(vcpu, regs->srr0);
1440 kvmppc_set_srr1(vcpu, regs->srr1);
5ce941ee 1441 kvmppc_set_pid(vcpu, regs->pid);
c1b8a01b
BB		 1442 kvmppc_set_sprg0(vcpu, regs->sprg0);
1443 kvmppc_set_sprg1(vcpu, regs->sprg1);
1444 kvmppc_set_sprg2(vcpu, regs->sprg2);
1445 kvmppc_set_sprg3(vcpu, regs->sprg3);
1446 kvmppc_set_sprg4(vcpu, regs->sprg4);
1447 kvmppc_set_sprg5(vcpu, regs->sprg5);
1448 kvmppc_set_sprg6(vcpu, regs->sprg6);
1449 kvmppc_set_sprg7(vcpu, regs->sprg7);
bbf45ba5 1450
8e5b26b5
AG		 1451 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1452 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
bbf45ba5
HB		 1453
1454 return 0;
1455}
1456
5ce941ee
SW		 1457static void get_sregs_base(struct kvm_vcpu *vcpu,
1458 struct kvm_sregs *sregs)
1459{
1460 u64 tb = get_tb();
1461
1462 sregs->u.e.features |= KVM_SREGS_E_BASE;
1463
1464 sregs->u.e.csrr0 = vcpu->arch.csrr0;
1465 sregs->u.e.csrr1 = vcpu->arch.csrr1;
1466 sregs->u.e.mcsr = vcpu->arch.mcsr;
dc168549 1467 sregs->u.e.esr = kvmppc_get_esr(vcpu);
a5414d4b 1468 sregs->u.e.dear = kvmppc_get_dar(vcpu);
5ce941ee
SW		 1469 sregs->u.e.tsr = vcpu->arch.tsr;
1470 sregs->u.e.tcr = vcpu->arch.tcr;
1471 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
1472 sregs->u.e.tb = tb;
1473 sregs->u.e.vrsave = vcpu->arch.vrsave;
1474}
1475
1476static int set_sregs_base(struct kvm_vcpu *vcpu,
1477 struct kvm_sregs *sregs)
1478{
1479 if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
1480 return 0;
1481
1482 vcpu->arch.csrr0 = sregs->u.e.csrr0;
1483 vcpu->arch.csrr1 = sregs->u.e.csrr1;
1484 vcpu->arch.mcsr = sregs->u.e.mcsr;
dc168549 1485 kvmppc_set_esr(vcpu, sregs->u.e.esr);
a5414d4b 1486 kvmppc_set_dar(vcpu, sregs->u.e.dear);
5ce941ee 1487 vcpu->arch.vrsave = sregs->u.e.vrsave;
dfd4d47e 1488 kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
5ce941ee 1489
dfd4d47e 1490 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
5ce941ee 1491 vcpu->arch.dec = sregs->u.e.dec;
dfd4d47e
SW		 1492 kvmppc_emulate_dec(vcpu);
1493 }
5ce941ee 1494
d26f22c9
BB		 1495 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR)
1496 kvmppc_set_tsr(vcpu, sregs->u.e.tsr);
5ce941ee
SW		 1497
1498 return 0;
1499}
1500
1501static void get_sregs_arch206(struct kvm_vcpu *vcpu,
1502 struct kvm_sregs *sregs)
1503{
1504 sregs->u.e.features |= KVM_SREGS_E_ARCH206;
1505
841741f2 1506 sregs->u.e.pir = vcpu->vcpu_id;
5ce941ee
SW		 1507 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
1508 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
1509 sregs->u.e.decar = vcpu->arch.decar;
1510 sregs->u.e.ivpr = vcpu->arch.ivpr;
1511}
1512
1513static int set_sregs_arch206(struct kvm_vcpu *vcpu,
1514 struct kvm_sregs *sregs)
1515{
1516 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
1517 return 0;
1518
841741f2 1519 if (sregs->u.e.pir != vcpu->vcpu_id)
5ce941ee
SW		 1520 return -EINVAL;
1521
1522 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
1523 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1;
1524 vcpu->arch.decar = sregs->u.e.decar;
1525 vcpu->arch.ivpr = sregs->u.e.ivpr;
1526
1527 return 0;
1528}
1529
3a167bea 1530int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
5ce941ee
SW		 1531{
1532 sregs->u.e.features |= KVM_SREGS_E_IVOR;
1533
1534 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
1535 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
1536 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
1537 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
1538 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
1539 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
1540 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
1541 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
1542 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
1543 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
1544 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
1545 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
1546 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
1547 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
1548 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
1549 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
3a167bea 1550 return 0;
5ce941ee
SW		 1551}
1552
1553int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1554{
1555 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
1556 return 0;
1557
1558 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0];
1559 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1];
1560 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2];
1561 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3];
1562 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4];
1563 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5];
1564 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6];
1565 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7];
1566 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8];
1567 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9];
1568 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10];
1569 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11];
1570 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12];
1571 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13];
1572 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14];
1573 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15];
1574
1575 return 0;
1576}
1577
bbf45ba5
HB		 1578int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1579 struct kvm_sregs *sregs)
1580{
5ce941ee
SW		 1581 sregs->pvr = vcpu->arch.pvr;
1582
1583 get_sregs_base(vcpu, sregs);
1584 get_sregs_arch206(vcpu, sregs);
cbbc58d4 1585 return vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs);
bbf45ba5
HB		 1586}
1587
1588int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1589 struct kvm_sregs *sregs)
1590{
5ce941ee
SW		 1591 int ret;
1592
1593 if (vcpu->arch.pvr != sregs->pvr)
1594 return -EINVAL;
1595
1596 ret = set_sregs_base(vcpu, sregs);
1597 if (ret < 0)
1598 return ret;
1599
1600 ret = set_sregs_arch206(vcpu, sregs);
1601 if (ret < 0)
1602 return ret;
1603
cbbc58d4 1604 return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs);
bbf45ba5
HB		 1605}
1606
8a41ea53
MC		 1607int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
1608 union kvmppc_one_reg *val)
31f3438e 1609{
35b299e2 1610 int r = 0;
35b299e2 1611
8a41ea53 1612 switch (id) {
6df8d3fc 1613 case KVM_REG_PPC_IAC1:
8a41ea53 1614 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1);
547465ef 1615 break;
6df8d3fc 1616 case KVM_REG_PPC_IAC2:
8a41ea53 1617 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac2);
547465ef
BB		 1618 break;
1619#if CONFIG_PPC_ADV_DEBUG_IACS > 2
6df8d3fc 1620 case KVM_REG_PPC_IAC3:
8a41ea53 1621 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac3);
547465ef 1622 break;
35b299e2 1623 case KVM_REG_PPC_IAC4:
8a41ea53 1624 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac4);
6df8d3fc 1625 break;
547465ef 1626#endif
6df8d3fc 1627 case KVM_REG_PPC_DAC1:
8a41ea53 1628 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac1);
547465ef 1629 break;
35b299e2 1630 case KVM_REG_PPC_DAC2:
8a41ea53 1631 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac2);
2c509672 1632 break;
324b3e63 1633 case KVM_REG_PPC_EPR: {
34f754b9 1634 u32 epr = kvmppc_get_epr(vcpu);
8a41ea53 1635 *val = get_reg_val(id, epr);
324b3e63
AG		 1636 break;
1637 }
352df1de
MC		 1638#if defined(CONFIG_64BIT)
1639 case KVM_REG_PPC_EPCR:
8a41ea53 1640 *val = get_reg_val(id, vcpu->arch.epcr);
352df1de
MC		 1641 break;
1642#endif
78accda4 1643 case KVM_REG_PPC_TCR:
8a41ea53 1644 *val = get_reg_val(id, vcpu->arch.tcr);
78accda4
BB		 1645 break;
1646 case KVM_REG_PPC_TSR:
8a41ea53 1647 *val = get_reg_val(id, vcpu->arch.tsr);
78accda4 1648 break;
35b299e2 1649 case KVM_REG_PPC_DEBUG_INST:
8a41ea53 1650 *val = get_reg_val(id, KVMPPC_INST_EHPRIV_DEBUG);
8c32a2ea 1651 break;
8b75cbbe 1652 case KVM_REG_PPC_VRSAVE:
8a41ea53 1653 *val = get_reg_val(id, vcpu->arch.vrsave);
8c32a2ea 1654 break;
6df8d3fc 1655 default:
8a41ea53 1656 r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val);
6df8d3fc
BB		 1657 break;
1658 }
35b299e2 1659
6df8d3fc 1660 return r;
31f3438e
PM		 1661}
1662
8a41ea53
MC		 1663int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
1664 union kvmppc_one_reg *val)
31f3438e 1665{
35b299e2 1666 int r = 0;
35b299e2 1667
8a41ea53 1668 switch (id) {
6df8d3fc 1669 case KVM_REG_PPC_IAC1:
8a41ea53 1670 vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val);
547465ef 1671 break;
6df8d3fc 1672 case KVM_REG_PPC_IAC2:
8a41ea53 1673 vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val);
547465ef
BB		 1674 break;
1675#if CONFIG_PPC_ADV_DEBUG_IACS > 2
6df8d3fc 1676 case KVM_REG_PPC_IAC3:
8a41ea53 1677 vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val);
547465ef 1678 break;
35b299e2 1679 case KVM_REG_PPC_IAC4:
8a41ea53 1680 vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val);
6df8d3fc 1681 break;
547465ef 1682#endif
6df8d3fc 1683 case KVM_REG_PPC_DAC1:
8a41ea53 1684 vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val);
547465ef 1685 break;
35b299e2 1686 case KVM_REG_PPC_DAC2:
8a41ea53 1687 vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val);
2c509672 1688 break;
324b3e63 1689 case KVM_REG_PPC_EPR: {
8a41ea53 1690 u32 new_epr = set_reg_val(id, *val);
35b299e2 1691 kvmppc_set_epr(vcpu, new_epr);
324b3e63
AG		 1692 break;
1693 }
352df1de
MC		 1694#if defined(CONFIG_64BIT)
1695 case KVM_REG_PPC_EPCR: {
8a41ea53 1696 u32 new_epcr = set_reg_val(id, *val);
35b299e2 1697 kvmppc_set_epcr(vcpu, new_epcr);
352df1de
MC		 1698 break;
1699 }
1700#endif
78accda4 1701 case KVM_REG_PPC_OR_TSR: {
8a41ea53 1702 u32 tsr_bits = set_reg_val(id, *val);
78accda4
BB		 1703 kvmppc_set_tsr_bits(vcpu, tsr_bits);
1704 break;
1705 }
1706 case KVM_REG_PPC_CLEAR_TSR: {
8a41ea53 1707 u32 tsr_bits = set_reg_val(id, *val);
78accda4
BB		 1708 kvmppc_clr_tsr_bits(vcpu, tsr_bits);
1709 break;
1710 }
1711 case KVM_REG_PPC_TSR: {
8a41ea53 1712 u32 tsr = set_reg_val(id, *val);
78accda4
BB		 1713 kvmppc_set_tsr(vcpu, tsr);
1714 break;
1715 }
1716 case KVM_REG_PPC_TCR: {
8a41ea53 1717 u32 tcr = set_reg_val(id, *val);
78accda4
BB		 1718 kvmppc_set_tcr(vcpu, tcr);
1719 break;
1720 }
8b75cbbe 1721 case KVM_REG_PPC_VRSAVE:
8a41ea53 1722 vcpu->arch.vrsave = set_reg_val(id, *val);
8b75cbbe 1723 break;
6df8d3fc 1724 default:
8a41ea53 1725 r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val);
6df8d3fc
BB		 1726 break;
1727 }
35b299e2 1728
6df8d3fc 1729 return r;
31f3438e
PM		 1730}
1731
bbf45ba5
HB		 1732int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1733{
1734 return -ENOTSUPP;
1735}
1736
1737int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1738{
1739 return -ENOTSUPP;
1740}
1741
bbf45ba5
HB		 1742int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1743 struct kvm_translation *tr)
1744{
98001d8d
AK		 1745 int r;
1746
98001d8d 1747 r = kvmppc_core_vcpu_translate(vcpu, tr);
98001d8d 1748 return r;
bbf45ba5 1749}
d9fbd03d 1750
4e755758
AG		 1751int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1752{
1753 return -ENOTSUPP;
1754}
1755
5587027c 1756void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
a66b48c3
PM		 1757 struct kvm_memory_slot *dont)
1758{
1759}
1760
5587027c 1761int kvmppc_core_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
a66b48c3
PM		 1762 unsigned long npages)
1763{
1764 return 0;
1765}
1766
f9e0554d 1767int kvmppc_core_prepare_memory_region(struct kvm *kvm,
a66b48c3 1768 struct kvm_memory_slot *memslot,
f9e0554d
PM		 1769 struct kvm_userspace_memory_region *mem)
1770{
1771 return 0;
1772}
1773
1774void kvmppc_core_commit_memory_region(struct kvm *kvm,
dfe49dbd 1775 struct kvm_userspace_memory_region *mem,
8482644a 1776 const struct kvm_memory_slot *old)
dfe49dbd
PM		 1777{
1778}
1779
1780void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
f9e0554d
PM		 1781{
1782}
1783
38f98824
MC		 1784void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
1785{
1786#if defined(CONFIG_64BIT)
1787 vcpu->arch.epcr = new_epcr;
1788#ifdef CONFIG_KVM_BOOKE_HV
1789 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
1790 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
1791 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
1792#endif
1793#endif
1794}
1795
dfd4d47e
SW		 1796void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
1797{
1798 vcpu->arch.tcr = new_tcr;
f61c94bb 1799 arm_next_watchdog(vcpu);
dfd4d47e
SW		 1800 update_timer_ints(vcpu);
1801}
1802
1803void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1804{
1805 set_bits(tsr_bits, &vcpu->arch.tsr);
1806 smp_wmb();
1807 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1808 kvm_vcpu_kick(vcpu);
1809}
1810
1811void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1812{
1813 clear_bits(tsr_bits, &vcpu->arch.tsr);
f61c94bb
BB		 1814
1815 /*
1816 * We may have stopped the watchdog due to
1817 * being stuck on final expiration.
1818 */
1819 if (tsr_bits & (TSR_ENW | TSR_WIS))
1820 arm_next_watchdog(vcpu);
1821
dfd4d47e
SW		 1822 update_timer_ints(vcpu);
1823}
1824
d02d4d15 1825void kvmppc_decrementer_func(struct kvm_vcpu *vcpu)
dfd4d47e 1826{
21bd000a
BB		 1827 if (vcpu->arch.tcr & TCR_ARE) {
1828 vcpu->arch.dec = vcpu->arch.decar;
1829 kvmppc_emulate_dec(vcpu);
1830 }
1831
dfd4d47e
SW		 1832 kvmppc_set_tsr_bits(vcpu, TSR_DIS);
1833}
1834
ce11e48b
BB		 1835static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg,
1836 uint64_t addr, int index)
1837{
1838 switch (index) {
1839 case 0:
1840 dbg_reg->dbcr0 |= DBCR0_IAC1;
1841 dbg_reg->iac1 = addr;
1842 break;
1843 case 1:
1844 dbg_reg->dbcr0 |= DBCR0_IAC2;
1845 dbg_reg->iac2 = addr;
1846 break;
1847#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1848 case 2:
1849 dbg_reg->dbcr0 |= DBCR0_IAC3;
1850 dbg_reg->iac3 = addr;
1851 break;
1852 case 3:
1853 dbg_reg->dbcr0 |= DBCR0_IAC4;
1854 dbg_reg->iac4 = addr;
1855 break;
1856#endif
1857 default:
1858 return -EINVAL;
1859 }
1860
1861 dbg_reg->dbcr0 |= DBCR0_IDM;
1862 return 0;
1863}
1864
1865static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr,
1866 int type, int index)
1867{
1868 switch (index) {
1869 case 0:
1870 if (type & KVMPPC_DEBUG_WATCH_READ)
1871 dbg_reg->dbcr0 |= DBCR0_DAC1R;
1872 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1873 dbg_reg->dbcr0 |= DBCR0_DAC1W;
1874 dbg_reg->dac1 = addr;
1875 break;
1876 case 1:
1877 if (type & KVMPPC_DEBUG_WATCH_READ)
1878 dbg_reg->dbcr0 |= DBCR0_DAC2R;
1879 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1880 dbg_reg->dbcr0 |= DBCR0_DAC2W;
1881 dbg_reg->dac2 = addr;
1882 break;
1883 default:
1884 return -EINVAL;
1885 }
1886
1887 dbg_reg->dbcr0 |= DBCR0_IDM;
1888 return 0;
1889}
1890void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set)
1891{
1892 /* XXX: Add similar MSR protection for BookE-PR */
1893#ifdef CONFIG_KVM_BOOKE_HV
1894 BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP));
1895 if (set) {
1896 if (prot_bitmap & MSR_UCLE)
1897 vcpu->arch.shadow_msrp |= MSRP_UCLEP;
1898 if (prot_bitmap & MSR_DE)
1899 vcpu->arch.shadow_msrp |= MSRP_DEP;
1900 if (prot_bitmap & MSR_PMM)
1901 vcpu->arch.shadow_msrp |= MSRP_PMMP;
1902 } else {
1903 if (prot_bitmap & MSR_UCLE)
1904 vcpu->arch.shadow_msrp &= ~MSRP_UCLEP;
1905 if (prot_bitmap & MSR_DE)
1906 vcpu->arch.shadow_msrp &= ~MSRP_DEP;
1907 if (prot_bitmap & MSR_PMM)
1908 vcpu->arch.shadow_msrp &= ~MSRP_PMMP;
1909 }
1910#endif
1911}
1912
7d15c06f
AG		 1913int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, enum xlate_instdata xlid,
1914 enum xlate_readwrite xlrw, struct kvmppc_pte *pte)
1915{
1916 int gtlb_index;
1917 gpa_t gpaddr;
1918
1919#ifdef CONFIG_KVM_E500V2
1920 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1921 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1922 pte->eaddr = eaddr;
1923 pte->raddr = (vcpu->arch.magic_page_pa & PAGE_MASK) |
1924 (eaddr & ~PAGE_MASK);
1925 pte->vpage = eaddr >> PAGE_SHIFT;
1926 pte->may_read = true;
1927 pte->may_write = true;
1928 pte->may_execute = true;
1929
1930 return 0;
1931 }
1932#endif
1933
1934 /* Check the guest TLB. */
1935 switch (xlid) {
1936 case XLATE_INST:
1937 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
1938 break;
1939 case XLATE_DATA:
1940 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
1941 break;
1942 default:
1943 BUG();
1944 }
1945
1946 /* Do we have a TLB entry at all? */
1947 if (gtlb_index < 0)
1948 return -ENOENT;
1949
1950 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1951
1952 pte->eaddr = eaddr;
1953 pte->raddr = (gpaddr & PAGE_MASK) | (eaddr & ~PAGE_MASK);
1954 pte->vpage = eaddr >> PAGE_SHIFT;
1955
1956 /* XXX read permissions from the guest TLB */
1957 pte->may_read = true;
1958 pte->may_write = true;
1959 pte->may_execute = true;
1960
1961 return 0;
1962}
1963
ce11e48b
BB		 1964int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
1965 struct kvm_guest_debug *dbg)
1966{
1967 struct debug_reg *dbg_reg;
1968 int n, b = 0, w = 0;
1969
1970 if (!(dbg->control & KVM_GUESTDBG_ENABLE)) {
348ba710 1971 vcpu->arch.dbg_reg.dbcr0 = 0;
ce11e48b
BB		 1972 vcpu->guest_debug = 0;
1973 kvm_guest_protect_msr(vcpu, MSR_DE, false);
1974 return 0;
1975 }
1976
1977 kvm_guest_protect_msr(vcpu, MSR_DE, true);
1978 vcpu->guest_debug = dbg->control;
348ba710 1979 vcpu->arch.dbg_reg.dbcr0 = 0;
ce11e48b
BB		 1980
1981 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
348ba710 1982 vcpu->arch.dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
ce11e48b
BB		 1983
1984 /* Code below handles only HW breakpoints */
348ba710 1985 dbg_reg = &(vcpu->arch.dbg_reg);
ce11e48b
BB		 1986
1987#ifdef CONFIG_KVM_BOOKE_HV
1988 /*
1989 * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1
1990 * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0
1991 */
1992 dbg_reg->dbcr1 = 0;
1993 dbg_reg->dbcr2 = 0;
1994#else
1995 /*
1996 * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1
1997 * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR
1998 * is set.
1999 */
2000 dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US |
2001 DBCR1_IAC4US;
2002 dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
2003#endif
2004
2005 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2006 return 0;
2007
2008 for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) {
2009 uint64_t addr = dbg->arch.bp[n].addr;
2010 uint32_t type = dbg->arch.bp[n].type;
2011
2012 if (type == KVMPPC_DEBUG_NONE)
2013 continue;
2014
2015 if (type & !(KVMPPC_DEBUG_WATCH_READ |
2016 KVMPPC_DEBUG_WATCH_WRITE |
2017 KVMPPC_DEBUG_BREAKPOINT))
2018 return -EINVAL;
2019
2020 if (type & KVMPPC_DEBUG_BREAKPOINT) {
2021 /* Setting H/W breakpoint */
2022 if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++))
2023 return -EINVAL;
2024 } else {
2025 /* Setting H/W watchpoint */
2026 if (kvmppc_booke_add_watchpoint(dbg_reg, addr,
2027 type, w++))
2028 return -EINVAL;
2029 }
2030 }
2031
2032 return 0;
2033}
2034
94fa9d99
SW		 2035void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2036{
a47d72f3 2037 vcpu->cpu = smp_processor_id();
d30f6e48 2038 current->thread.kvm_vcpu = vcpu;
94fa9d99
SW		 2039}
2040
2041void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
2042{
d30f6e48 2043 current->thread.kvm_vcpu = NULL;
a47d72f3 2044 vcpu->cpu = -1;
ce11e48b
BB		 2045
2046 /* Clear pending debug event in DBSR */
2047 kvmppc_clear_dbsr();
94fa9d99
SW		 2048}
2049
3a167bea
AK		 2050void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
2051{
cbbc58d4 2052 vcpu->kvm->arch.kvm_ops->mmu_destroy(vcpu);
3a167bea
AK		 2053}
2054
2055int kvmppc_core_init_vm(struct kvm *kvm)
2056{
cbbc58d4 2057 return kvm->arch.kvm_ops->init_vm(kvm);
3a167bea
AK		 2058}
2059
2060struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
2061{
cbbc58d4 2062 return kvm->arch.kvm_ops->vcpu_create(kvm, id);
3a167bea
AK		 2063}
2064
2065void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
2066{
cbbc58d4 2067 vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu);
3a167bea
AK		 2068}
2069
2070void kvmppc_core_destroy_vm(struct kvm *kvm)
2071{
cbbc58d4 2072 kvm->arch.kvm_ops->destroy_vm(kvm);
3a167bea
AK		 2073}
2074
2075void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2076{
cbbc58d4 2077 vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu);
3a167bea
AK		 2078}
2079
2080void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
2081{
cbbc58d4 2082 vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu);
94fa9d99
SW		 2083}
2084
2986b8c7 2085int __init kvmppc_booke_init(void)
d9fbd03d 2086{
d30f6e48 2087#ifndef CONFIG_KVM_BOOKE_HV
d9fbd03d 2088 unsigned long ivor[16];
1d542d9c 2089 unsigned long *handler = kvmppc_booke_handler_addr;
d9fbd03d 2090 unsigned long max_ivor = 0;
1d542d9c 2091 unsigned long handler_len;
d9fbd03d
HB		 2092 int i;
2093
2094 /* We install our own exception handlers by hijacking IVPR. IVPR must
2095 * be 16-bit aligned, so we need a 64KB allocation. */
2096 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO,
2097 VCPU_SIZE_ORDER);
2098 if (!kvmppc_booke_handlers)
2099 return -ENOMEM;
2100
2101 /* XXX make sure our handlers are smaller than Linux's */
2102
2103 /* Copy our interrupt handlers to match host IVORs. That way we don't
2104 * have to swap the IVORs on every guest/host transition. */
2105 ivor[0] = mfspr(SPRN_IVOR0);
2106 ivor[1] = mfspr(SPRN_IVOR1);
2107 ivor[2] = mfspr(SPRN_IVOR2);
2108 ivor[3] = mfspr(SPRN_IVOR3);
2109 ivor[4] = mfspr(SPRN_IVOR4);
2110 ivor[5] = mfspr(SPRN_IVOR5);
2111 ivor[6] = mfspr(SPRN_IVOR6);
2112 ivor[7] = mfspr(SPRN_IVOR7);
2113 ivor[8] = mfspr(SPRN_IVOR8);
2114 ivor[9] = mfspr(SPRN_IVOR9);
2115 ivor[10] = mfspr(SPRN_IVOR10);
2116 ivor[11] = mfspr(SPRN_IVOR11);
2117 ivor[12] = mfspr(SPRN_IVOR12);
2118 ivor[13] = mfspr(SPRN_IVOR13);
2119 ivor[14] = mfspr(SPRN_IVOR14);
2120 ivor[15] = mfspr(SPRN_IVOR15);
2121
2122 for (i = 0; i < 16; i++) {
2123 if (ivor[i] > max_ivor)
1d542d9c 2124 max_ivor = i;
d9fbd03d 2125
1d542d9c 2126 handler_len = handler[i + 1] - handler[i];
d9fbd03d 2127 memcpy((void *)kvmppc_booke_handlers + ivor[i],
1d542d9c 2128 (void *)handler[i], handler_len);
d9fbd03d 2129 }
1d542d9c
BB		 2130
2131 handler_len = handler[max_ivor + 1] - handler[max_ivor];
2132 flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
2133 ivor[max_ivor] + handler_len);
d30f6e48 2134#endif /* !BOOKE_HV */
db93f574 2135 return 0;
d9fbd03d
HB		 2136}
2137
db93f574 2138void __exit kvmppc_booke_exit(void)
d9fbd03d
HB		 2139{
2140 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER);
2141 kvm_exit();
2142}
Linux 6.x block layer and io_uring tree(s)