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bbf45ba5 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2007 | |
4cd35f67 | 16 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
bbf45ba5 HB |
17 | * |
18 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
19 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
d30f6e48 SW |
20 | * Scott Wood <scottwood@freescale.com> |
21 | * Varun Sethi <varun.sethi@freescale.com> | |
bbf45ba5 HB |
22 | */ |
23 | ||
24 | #include <linux/errno.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 27 | #include <linux/gfp.h> |
bbf45ba5 HB |
28 | #include <linux/module.h> |
29 | #include <linux/vmalloc.h> | |
30 | #include <linux/fs.h> | |
7924bd41 | 31 | |
bbf45ba5 HB |
32 | #include <asm/cputable.h> |
33 | #include <asm/uaccess.h> | |
34 | #include <asm/kvm_ppc.h> | |
d9fbd03d | 35 | #include <asm/cacheflush.h> |
d30f6e48 SW |
36 | #include <asm/dbell.h> |
37 | #include <asm/hw_irq.h> | |
38 | #include <asm/irq.h> | |
bbf45ba5 | 39 | |
d30f6e48 | 40 | #include "timing.h" |
75f74f0d | 41 | #include "booke.h" |
bbf45ba5 | 42 | |
d9fbd03d HB |
43 | unsigned long kvmppc_booke_handlers; |
44 | ||
bbf45ba5 HB |
45 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
46 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
47 | ||
48 | struct kvm_stats_debugfs_item debugfs_entries[] = { | |
bbf45ba5 HB |
49 | { "mmio", VCPU_STAT(mmio_exits) }, |
50 | { "dcr", VCPU_STAT(dcr_exits) }, | |
51 | { "sig", VCPU_STAT(signal_exits) }, | |
bbf45ba5 HB |
52 | { "itlb_r", VCPU_STAT(itlb_real_miss_exits) }, |
53 | { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) }, | |
54 | { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) }, | |
55 | { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) }, | |
56 | { "sysc", VCPU_STAT(syscall_exits) }, | |
57 | { "isi", VCPU_STAT(isi_exits) }, | |
58 | { "dsi", VCPU_STAT(dsi_exits) }, | |
59 | { "inst_emu", VCPU_STAT(emulated_inst_exits) }, | |
60 | { "dec", VCPU_STAT(dec_exits) }, | |
61 | { "ext_intr", VCPU_STAT(ext_intr_exits) }, | |
45c5eb67 | 62 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
d30f6e48 SW |
63 | { "doorbell", VCPU_STAT(dbell_exits) }, |
64 | { "guest doorbell", VCPU_STAT(gdbell_exits) }, | |
bbf45ba5 HB |
65 | { NULL } |
66 | }; | |
67 | ||
bbf45ba5 HB |
68 | /* TODO: use vcpu_printf() */ |
69 | void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu) | |
70 | { | |
71 | int i; | |
72 | ||
666e7252 | 73 | printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr); |
5cf8ca22 | 74 | printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr); |
de7906c3 AG |
75 | printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0, |
76 | vcpu->arch.shared->srr1); | |
bbf45ba5 HB |
77 | |
78 | printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions); | |
79 | ||
80 | for (i = 0; i < 32; i += 4) { | |
5cf8ca22 | 81 | printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i, |
8e5b26b5 AG |
82 | kvmppc_get_gpr(vcpu, i), |
83 | kvmppc_get_gpr(vcpu, i+1), | |
84 | kvmppc_get_gpr(vcpu, i+2), | |
85 | kvmppc_get_gpr(vcpu, i+3)); | |
bbf45ba5 HB |
86 | } |
87 | } | |
88 | ||
4cd35f67 SW |
89 | #ifdef CONFIG_SPE |
90 | void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu) | |
91 | { | |
92 | preempt_disable(); | |
93 | enable_kernel_spe(); | |
94 | kvmppc_save_guest_spe(vcpu); | |
95 | vcpu->arch.shadow_msr &= ~MSR_SPE; | |
96 | preempt_enable(); | |
97 | } | |
98 | ||
99 | static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu) | |
100 | { | |
101 | preempt_disable(); | |
102 | enable_kernel_spe(); | |
103 | kvmppc_load_guest_spe(vcpu); | |
104 | vcpu->arch.shadow_msr |= MSR_SPE; | |
105 | preempt_enable(); | |
106 | } | |
107 | ||
108 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
109 | { | |
110 | if (vcpu->arch.shared->msr & MSR_SPE) { | |
111 | if (!(vcpu->arch.shadow_msr & MSR_SPE)) | |
112 | kvmppc_vcpu_enable_spe(vcpu); | |
113 | } else if (vcpu->arch.shadow_msr & MSR_SPE) { | |
114 | kvmppc_vcpu_disable_spe(vcpu); | |
115 | } | |
116 | } | |
117 | #else | |
118 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
119 | { | |
120 | } | |
121 | #endif | |
122 | ||
dd9ebf1f LY |
123 | /* |
124 | * Helper function for "full" MSR writes. No need to call this if only | |
125 | * EE/CE/ME/DE/RI are changing. | |
126 | */ | |
4cd35f67 SW |
127 | void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr) |
128 | { | |
dd9ebf1f | 129 | u32 old_msr = vcpu->arch.shared->msr; |
4cd35f67 | 130 | |
d30f6e48 SW |
131 | #ifdef CONFIG_KVM_BOOKE_HV |
132 | new_msr |= MSR_GS; | |
133 | #endif | |
134 | ||
4cd35f67 SW |
135 | vcpu->arch.shared->msr = new_msr; |
136 | ||
dd9ebf1f | 137 | kvmppc_mmu_msr_notify(vcpu, old_msr); |
4cd35f67 SW |
138 | kvmppc_vcpu_sync_spe(vcpu); |
139 | } | |
140 | ||
d4cf3892 HB |
141 | static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, |
142 | unsigned int priority) | |
9dd921cf | 143 | { |
9dd921cf HB |
144 | set_bit(priority, &vcpu->arch.pending_exceptions); |
145 | } | |
146 | ||
daf5e271 LY |
147 | static void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, |
148 | ulong dear_flags, ulong esr_flags) | |
9dd921cf | 149 | { |
daf5e271 LY |
150 | vcpu->arch.queued_dear = dear_flags; |
151 | vcpu->arch.queued_esr = esr_flags; | |
152 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS); | |
153 | } | |
154 | ||
155 | static void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, | |
156 | ulong dear_flags, ulong esr_flags) | |
157 | { | |
158 | vcpu->arch.queued_dear = dear_flags; | |
159 | vcpu->arch.queued_esr = esr_flags; | |
160 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE); | |
161 | } | |
162 | ||
163 | static void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, | |
164 | ulong esr_flags) | |
165 | { | |
166 | vcpu->arch.queued_esr = esr_flags; | |
167 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE); | |
168 | } | |
169 | ||
170 | void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags) | |
171 | { | |
172 | vcpu->arch.queued_esr = esr_flags; | |
d4cf3892 | 173 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM); |
9dd921cf HB |
174 | } |
175 | ||
176 | void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu) | |
177 | { | |
d4cf3892 | 178 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER); |
9dd921cf HB |
179 | } |
180 | ||
181 | int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu) | |
182 | { | |
d4cf3892 | 183 | return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); |
9dd921cf HB |
184 | } |
185 | ||
7706664d AG |
186 | void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu) |
187 | { | |
188 | clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); | |
189 | } | |
190 | ||
9dd921cf HB |
191 | void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, |
192 | struct kvm_interrupt *irq) | |
193 | { | |
c5335f17 AG |
194 | unsigned int prio = BOOKE_IRQPRIO_EXTERNAL; |
195 | ||
196 | if (irq->irq == KVM_INTERRUPT_SET_LEVEL) | |
197 | prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL; | |
198 | ||
199 | kvmppc_booke_queue_irqprio(vcpu, prio); | |
9dd921cf HB |
200 | } |
201 | ||
4496f974 AG |
202 | void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu, |
203 | struct kvm_interrupt *irq) | |
204 | { | |
205 | clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions); | |
c5335f17 | 206 | clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions); |
4496f974 AG |
207 | } |
208 | ||
d30f6e48 SW |
209 | static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) |
210 | { | |
211 | #ifdef CONFIG_KVM_BOOKE_HV | |
212 | mtspr(SPRN_GSRR0, srr0); | |
213 | mtspr(SPRN_GSRR1, srr1); | |
214 | #else | |
215 | vcpu->arch.shared->srr0 = srr0; | |
216 | vcpu->arch.shared->srr1 = srr1; | |
217 | #endif | |
218 | } | |
219 | ||
220 | static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
221 | { | |
222 | vcpu->arch.csrr0 = srr0; | |
223 | vcpu->arch.csrr1 = srr1; | |
224 | } | |
225 | ||
226 | static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
227 | { | |
228 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) { | |
229 | vcpu->arch.dsrr0 = srr0; | |
230 | vcpu->arch.dsrr1 = srr1; | |
231 | } else { | |
232 | set_guest_csrr(vcpu, srr0, srr1); | |
233 | } | |
234 | } | |
235 | ||
236 | static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1) | |
237 | { | |
238 | vcpu->arch.mcsrr0 = srr0; | |
239 | vcpu->arch.mcsrr1 = srr1; | |
240 | } | |
241 | ||
242 | static unsigned long get_guest_dear(struct kvm_vcpu *vcpu) | |
243 | { | |
244 | #ifdef CONFIG_KVM_BOOKE_HV | |
245 | return mfspr(SPRN_GDEAR); | |
246 | #else | |
247 | return vcpu->arch.shared->dar; | |
248 | #endif | |
249 | } | |
250 | ||
251 | static void set_guest_dear(struct kvm_vcpu *vcpu, unsigned long dear) | |
252 | { | |
253 | #ifdef CONFIG_KVM_BOOKE_HV | |
254 | mtspr(SPRN_GDEAR, dear); | |
255 | #else | |
256 | vcpu->arch.shared->dar = dear; | |
257 | #endif | |
258 | } | |
259 | ||
260 | static unsigned long get_guest_esr(struct kvm_vcpu *vcpu) | |
261 | { | |
262 | #ifdef CONFIG_KVM_BOOKE_HV | |
263 | return mfspr(SPRN_GESR); | |
264 | #else | |
265 | return vcpu->arch.shared->esr; | |
266 | #endif | |
267 | } | |
268 | ||
269 | static void set_guest_esr(struct kvm_vcpu *vcpu, u32 esr) | |
270 | { | |
271 | #ifdef CONFIG_KVM_BOOKE_HV | |
272 | mtspr(SPRN_GESR, esr); | |
273 | #else | |
274 | vcpu->arch.shared->esr = esr; | |
275 | #endif | |
276 | } | |
277 | ||
d4cf3892 HB |
278 | /* Deliver the interrupt of the corresponding priority, if possible. */ |
279 | static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, | |
280 | unsigned int priority) | |
bbf45ba5 | 281 | { |
d4cf3892 | 282 | int allowed = 0; |
79300f8c | 283 | ulong msr_mask = 0; |
daf5e271 | 284 | bool update_esr = false, update_dear = false; |
5c6cedf4 AG |
285 | ulong crit_raw = vcpu->arch.shared->critical; |
286 | ulong crit_r1 = kvmppc_get_gpr(vcpu, 1); | |
287 | bool crit; | |
c5335f17 | 288 | bool keep_irq = false; |
d30f6e48 | 289 | enum int_class int_class; |
5c6cedf4 AG |
290 | |
291 | /* Truncate crit indicators in 32 bit mode */ | |
292 | if (!(vcpu->arch.shared->msr & MSR_SF)) { | |
293 | crit_raw &= 0xffffffff; | |
294 | crit_r1 &= 0xffffffff; | |
295 | } | |
296 | ||
297 | /* Critical section when crit == r1 */ | |
298 | crit = (crit_raw == crit_r1); | |
299 | /* ... and we're in supervisor mode */ | |
300 | crit = crit && !(vcpu->arch.shared->msr & MSR_PR); | |
d4cf3892 | 301 | |
c5335f17 AG |
302 | if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) { |
303 | priority = BOOKE_IRQPRIO_EXTERNAL; | |
304 | keep_irq = true; | |
305 | } | |
306 | ||
d4cf3892 | 307 | switch (priority) { |
d4cf3892 | 308 | case BOOKE_IRQPRIO_DTLB_MISS: |
d4cf3892 | 309 | case BOOKE_IRQPRIO_DATA_STORAGE: |
daf5e271 LY |
310 | update_dear = true; |
311 | /* fall through */ | |
d4cf3892 | 312 | case BOOKE_IRQPRIO_INST_STORAGE: |
daf5e271 LY |
313 | case BOOKE_IRQPRIO_PROGRAM: |
314 | update_esr = true; | |
315 | /* fall through */ | |
316 | case BOOKE_IRQPRIO_ITLB_MISS: | |
317 | case BOOKE_IRQPRIO_SYSCALL: | |
d4cf3892 | 318 | case BOOKE_IRQPRIO_FP_UNAVAIL: |
bb3a8a17 HB |
319 | case BOOKE_IRQPRIO_SPE_UNAVAIL: |
320 | case BOOKE_IRQPRIO_SPE_FP_DATA: | |
321 | case BOOKE_IRQPRIO_SPE_FP_ROUND: | |
d4cf3892 HB |
322 | case BOOKE_IRQPRIO_AP_UNAVAIL: |
323 | case BOOKE_IRQPRIO_ALIGNMENT: | |
324 | allowed = 1; | |
79300f8c | 325 | msr_mask = MSR_CE | MSR_ME | MSR_DE; |
d30f6e48 | 326 | int_class = INT_CLASS_NONCRIT; |
bbf45ba5 | 327 | break; |
d4cf3892 | 328 | case BOOKE_IRQPRIO_CRITICAL: |
4ab96919 | 329 | case BOOKE_IRQPRIO_DBELL_CRIT: |
666e7252 | 330 | allowed = vcpu->arch.shared->msr & MSR_CE; |
d30f6e48 | 331 | allowed = allowed && !crit; |
79300f8c | 332 | msr_mask = MSR_ME; |
d30f6e48 | 333 | int_class = INT_CLASS_CRIT; |
bbf45ba5 | 334 | break; |
d4cf3892 | 335 | case BOOKE_IRQPRIO_MACHINE_CHECK: |
666e7252 | 336 | allowed = vcpu->arch.shared->msr & MSR_ME; |
d30f6e48 | 337 | allowed = allowed && !crit; |
d30f6e48 | 338 | int_class = INT_CLASS_MC; |
bbf45ba5 | 339 | break; |
d4cf3892 HB |
340 | case BOOKE_IRQPRIO_DECREMENTER: |
341 | case BOOKE_IRQPRIO_FIT: | |
dfd4d47e SW |
342 | keep_irq = true; |
343 | /* fall through */ | |
344 | case BOOKE_IRQPRIO_EXTERNAL: | |
4ab96919 | 345 | case BOOKE_IRQPRIO_DBELL: |
666e7252 | 346 | allowed = vcpu->arch.shared->msr & MSR_EE; |
5c6cedf4 | 347 | allowed = allowed && !crit; |
79300f8c | 348 | msr_mask = MSR_CE | MSR_ME | MSR_DE; |
d30f6e48 | 349 | int_class = INT_CLASS_NONCRIT; |
bbf45ba5 | 350 | break; |
d4cf3892 | 351 | case BOOKE_IRQPRIO_DEBUG: |
666e7252 | 352 | allowed = vcpu->arch.shared->msr & MSR_DE; |
d30f6e48 | 353 | allowed = allowed && !crit; |
79300f8c | 354 | msr_mask = MSR_ME; |
d30f6e48 | 355 | int_class = INT_CLASS_CRIT; |
bbf45ba5 | 356 | break; |
bbf45ba5 HB |
357 | } |
358 | ||
d4cf3892 | 359 | if (allowed) { |
d30f6e48 SW |
360 | switch (int_class) { |
361 | case INT_CLASS_NONCRIT: | |
362 | set_guest_srr(vcpu, vcpu->arch.pc, | |
363 | vcpu->arch.shared->msr); | |
364 | break; | |
365 | case INT_CLASS_CRIT: | |
366 | set_guest_csrr(vcpu, vcpu->arch.pc, | |
367 | vcpu->arch.shared->msr); | |
368 | break; | |
369 | case INT_CLASS_DBG: | |
370 | set_guest_dsrr(vcpu, vcpu->arch.pc, | |
371 | vcpu->arch.shared->msr); | |
372 | break; | |
373 | case INT_CLASS_MC: | |
374 | set_guest_mcsrr(vcpu, vcpu->arch.pc, | |
375 | vcpu->arch.shared->msr); | |
376 | break; | |
377 | } | |
378 | ||
d4cf3892 | 379 | vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority]; |
daf5e271 | 380 | if (update_esr == true) |
d30f6e48 | 381 | set_guest_esr(vcpu, vcpu->arch.queued_esr); |
daf5e271 | 382 | if (update_dear == true) |
d30f6e48 | 383 | set_guest_dear(vcpu, vcpu->arch.queued_dear); |
666e7252 | 384 | kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask); |
bbf45ba5 | 385 | |
c5335f17 AG |
386 | if (!keep_irq) |
387 | clear_bit(priority, &vcpu->arch.pending_exceptions); | |
bbf45ba5 HB |
388 | } |
389 | ||
d30f6e48 SW |
390 | #ifdef CONFIG_KVM_BOOKE_HV |
391 | /* | |
392 | * If an interrupt is pending but masked, raise a guest doorbell | |
393 | * so that we are notified when the guest enables the relevant | |
394 | * MSR bit. | |
395 | */ | |
396 | if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE) | |
397 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT); | |
398 | if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE) | |
399 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT); | |
400 | if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK) | |
401 | kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC); | |
402 | #endif | |
403 | ||
d4cf3892 | 404 | return allowed; |
bbf45ba5 HB |
405 | } |
406 | ||
dfd4d47e SW |
407 | static void update_timer_ints(struct kvm_vcpu *vcpu) |
408 | { | |
409 | if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS)) | |
410 | kvmppc_core_queue_dec(vcpu); | |
411 | else | |
412 | kvmppc_core_dequeue_dec(vcpu); | |
413 | } | |
414 | ||
c59a6a3e | 415 | static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu) |
bbf45ba5 HB |
416 | { |
417 | unsigned long *pending = &vcpu->arch.pending_exceptions; | |
bbf45ba5 HB |
418 | unsigned int priority; |
419 | ||
dfd4d47e SW |
420 | if (vcpu->requests) { |
421 | if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu)) { | |
422 | smp_mb(); | |
423 | update_timer_ints(vcpu); | |
424 | } | |
425 | } | |
426 | ||
9ab80843 | 427 | priority = __ffs(*pending); |
8b3a00fc | 428 | while (priority < BOOKE_IRQPRIO_MAX) { |
d4cf3892 | 429 | if (kvmppc_booke_irqprio_deliver(vcpu, priority)) |
bbf45ba5 | 430 | break; |
bbf45ba5 HB |
431 | |
432 | priority = find_next_bit(pending, | |
433 | BITS_PER_BYTE * sizeof(*pending), | |
434 | priority + 1); | |
435 | } | |
90bba358 AG |
436 | |
437 | /* Tell the guest about our interrupt status */ | |
29ac26ef | 438 | vcpu->arch.shared->int_pending = !!*pending; |
bbf45ba5 HB |
439 | } |
440 | ||
c59a6a3e | 441 | /* Check pending exceptions and deliver one, if possible. */ |
a8e4ef84 | 442 | int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu) |
c59a6a3e | 443 | { |
a8e4ef84 | 444 | int r = 0; |
c59a6a3e SW |
445 | WARN_ON_ONCE(!irqs_disabled()); |
446 | ||
447 | kvmppc_core_check_exceptions(vcpu); | |
448 | ||
449 | if (vcpu->arch.shared->msr & MSR_WE) { | |
450 | local_irq_enable(); | |
451 | kvm_vcpu_block(vcpu); | |
452 | local_irq_disable(); | |
453 | ||
454 | kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS); | |
a8e4ef84 | 455 | r = 1; |
c59a6a3e | 456 | }; |
a8e4ef84 AG |
457 | |
458 | return r; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Common checks before entering the guest world. Call with interrupts | |
463 | * disabled. | |
464 | * | |
465 | * returns !0 if a signal is pending and check_signal is true | |
466 | */ | |
467 | static int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu, bool check_signal) | |
468 | { | |
469 | int r = 0; | |
470 | ||
471 | WARN_ON_ONCE(!irqs_disabled()); | |
472 | while (true) { | |
473 | if (need_resched()) { | |
474 | local_irq_enable(); | |
475 | cond_resched(); | |
476 | local_irq_disable(); | |
477 | continue; | |
478 | } | |
479 | ||
480 | if (check_signal && signal_pending(current)) { | |
481 | r = 1; | |
482 | break; | |
483 | } | |
484 | ||
485 | if (kvmppc_core_prepare_to_enter(vcpu)) { | |
486 | /* interrupts got enabled in between, so we | |
487 | are back at square 1 */ | |
488 | continue; | |
489 | } | |
490 | ||
491 | break; | |
492 | } | |
493 | ||
494 | return r; | |
c59a6a3e SW |
495 | } |
496 | ||
df6909e5 PM |
497 | int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
498 | { | |
499 | int ret; | |
8fae845f SW |
500 | #ifdef CONFIG_PPC_FPU |
501 | unsigned int fpscr; | |
502 | int fpexc_mode; | |
503 | u64 fpr[32]; | |
504 | #endif | |
df6909e5 | 505 | |
af8f38b3 AG |
506 | if (!vcpu->arch.sane) { |
507 | kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
df6909e5 | 511 | local_irq_disable(); |
a8e4ef84 | 512 | if (kvmppc_prepare_to_enter(vcpu, true)) { |
1d1ef222 SW |
513 | kvm_run->exit_reason = KVM_EXIT_INTR; |
514 | ret = -EINTR; | |
515 | goto out; | |
516 | } | |
517 | ||
df6909e5 | 518 | kvm_guest_enter(); |
8fae845f SW |
519 | |
520 | #ifdef CONFIG_PPC_FPU | |
521 | /* Save userspace FPU state in stack */ | |
522 | enable_kernel_fp(); | |
523 | memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr)); | |
524 | fpscr = current->thread.fpscr.val; | |
525 | fpexc_mode = current->thread.fpexc_mode; | |
526 | ||
527 | /* Restore guest FPU state to thread */ | |
528 | memcpy(current->thread.fpr, vcpu->arch.fpr, sizeof(vcpu->arch.fpr)); | |
529 | current->thread.fpscr.val = vcpu->arch.fpscr; | |
530 | ||
531 | /* | |
532 | * Since we can't trap on MSR_FP in GS-mode, we consider the guest | |
533 | * as always using the FPU. Kernel usage of FP (via | |
534 | * enable_kernel_fp()) in this thread must not occur while | |
535 | * vcpu->fpu_active is set. | |
536 | */ | |
537 | vcpu->fpu_active = 1; | |
538 | ||
539 | kvmppc_load_guest_fp(vcpu); | |
540 | #endif | |
541 | ||
df6909e5 | 542 | ret = __kvmppc_vcpu_run(kvm_run, vcpu); |
8fae845f SW |
543 | |
544 | #ifdef CONFIG_PPC_FPU | |
545 | kvmppc_save_guest_fp(vcpu); | |
546 | ||
547 | vcpu->fpu_active = 0; | |
548 | ||
549 | /* Save guest FPU state from thread */ | |
550 | memcpy(vcpu->arch.fpr, current->thread.fpr, sizeof(vcpu->arch.fpr)); | |
551 | vcpu->arch.fpscr = current->thread.fpscr.val; | |
552 | ||
553 | /* Restore userspace FPU state from stack */ | |
554 | memcpy(current->thread.fpr, fpr, sizeof(current->thread.fpr)); | |
555 | current->thread.fpscr.val = fpscr; | |
556 | current->thread.fpexc_mode = fpexc_mode; | |
557 | #endif | |
558 | ||
df6909e5 | 559 | kvm_guest_exit(); |
df6909e5 | 560 | |
1d1ef222 SW |
561 | out: |
562 | local_irq_enable(); | |
df6909e5 PM |
563 | return ret; |
564 | } | |
565 | ||
d30f6e48 SW |
566 | static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) |
567 | { | |
568 | enum emulation_result er; | |
569 | ||
570 | er = kvmppc_emulate_instruction(run, vcpu); | |
571 | switch (er) { | |
572 | case EMULATE_DONE: | |
573 | /* don't overwrite subtypes, just account kvm_stats */ | |
574 | kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS); | |
575 | /* Future optimization: only reload non-volatiles if | |
576 | * they were actually modified by emulation. */ | |
577 | return RESUME_GUEST_NV; | |
578 | ||
579 | case EMULATE_DO_DCR: | |
580 | run->exit_reason = KVM_EXIT_DCR; | |
581 | return RESUME_HOST; | |
582 | ||
583 | case EMULATE_FAIL: | |
d30f6e48 SW |
584 | printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", |
585 | __func__, vcpu->arch.pc, vcpu->arch.last_inst); | |
586 | /* For debugging, encode the failing instruction and | |
587 | * report it to userspace. */ | |
588 | run->hw.hardware_exit_reason = ~0ULL << 32; | |
589 | run->hw.hardware_exit_reason |= vcpu->arch.last_inst; | |
d1ff5499 | 590 | kvmppc_core_queue_program(vcpu, ESR_PIL); |
d30f6e48 SW |
591 | return RESUME_HOST; |
592 | ||
593 | default: | |
594 | BUG(); | |
595 | } | |
596 | } | |
597 | ||
bbf45ba5 HB |
598 | /** |
599 | * kvmppc_handle_exit | |
600 | * | |
601 | * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) | |
602 | */ | |
603 | int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
604 | unsigned int exit_nr) | |
605 | { | |
bbf45ba5 HB |
606 | int r = RESUME_HOST; |
607 | ||
73e75b41 HB |
608 | /* update before a new last_exit_type is rewritten */ |
609 | kvmppc_update_timing_stats(vcpu); | |
610 | ||
d30f6e48 SW |
611 | switch (exit_nr) { |
612 | case BOOKE_INTERRUPT_EXTERNAL: | |
613 | do_IRQ(current->thread.regs); | |
614 | break; | |
615 | ||
616 | case BOOKE_INTERRUPT_DECREMENTER: | |
617 | timer_interrupt(current->thread.regs); | |
618 | break; | |
619 | ||
620 | #if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3E_64) | |
621 | case BOOKE_INTERRUPT_DOORBELL: | |
622 | doorbell_exception(current->thread.regs); | |
623 | break; | |
624 | #endif | |
625 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
626 | /* FIXME */ | |
627 | break; | |
628 | } | |
629 | ||
bbf45ba5 HB |
630 | local_irq_enable(); |
631 | ||
632 | run->exit_reason = KVM_EXIT_UNKNOWN; | |
633 | run->ready_for_interrupt_injection = 1; | |
634 | ||
635 | switch (exit_nr) { | |
636 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
c35c9d84 AG |
637 | printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR)); |
638 | kvmppc_dump_vcpu(vcpu); | |
639 | /* For debugging, send invalid exit reason to user space */ | |
640 | run->hw.hardware_exit_reason = ~1ULL << 32; | |
641 | run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR); | |
642 | r = RESUME_HOST; | |
bbf45ba5 HB |
643 | break; |
644 | ||
645 | case BOOKE_INTERRUPT_EXTERNAL: | |
7b701591 | 646 | kvmppc_account_exit(vcpu, EXT_INTR_EXITS); |
1b6766c7 HB |
647 | r = RESUME_GUEST; |
648 | break; | |
649 | ||
bbf45ba5 | 650 | case BOOKE_INTERRUPT_DECREMENTER: |
7b701591 | 651 | kvmppc_account_exit(vcpu, DEC_EXITS); |
bbf45ba5 HB |
652 | r = RESUME_GUEST; |
653 | break; | |
654 | ||
d30f6e48 SW |
655 | case BOOKE_INTERRUPT_DOORBELL: |
656 | kvmppc_account_exit(vcpu, DBELL_EXITS); | |
d30f6e48 SW |
657 | r = RESUME_GUEST; |
658 | break; | |
659 | ||
660 | case BOOKE_INTERRUPT_GUEST_DBELL_CRIT: | |
661 | kvmppc_account_exit(vcpu, GDBELL_EXITS); | |
662 | ||
663 | /* | |
664 | * We are here because there is a pending guest interrupt | |
665 | * which could not be delivered as MSR_CE or MSR_ME was not | |
666 | * set. Once we break from here we will retry delivery. | |
667 | */ | |
668 | r = RESUME_GUEST; | |
669 | break; | |
670 | ||
671 | case BOOKE_INTERRUPT_GUEST_DBELL: | |
672 | kvmppc_account_exit(vcpu, GDBELL_EXITS); | |
673 | ||
674 | /* | |
675 | * We are here because there is a pending guest interrupt | |
676 | * which could not be delivered as MSR_EE was not set. Once | |
677 | * we break from here we will retry delivery. | |
678 | */ | |
679 | r = RESUME_GUEST; | |
680 | break; | |
681 | ||
682 | case BOOKE_INTERRUPT_HV_PRIV: | |
683 | r = emulation_exit(run, vcpu); | |
684 | break; | |
685 | ||
bbf45ba5 | 686 | case BOOKE_INTERRUPT_PROGRAM: |
d30f6e48 | 687 | if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) { |
bbf45ba5 HB |
688 | /* Program traps generated by user-level software must be handled |
689 | * by the guest kernel. */ | |
daf5e271 | 690 | kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr); |
bbf45ba5 | 691 | r = RESUME_GUEST; |
7b701591 | 692 | kvmppc_account_exit(vcpu, USR_PR_INST); |
bbf45ba5 HB |
693 | break; |
694 | } | |
695 | ||
d30f6e48 | 696 | r = emulation_exit(run, vcpu); |
bbf45ba5 HB |
697 | break; |
698 | ||
de368dce | 699 | case BOOKE_INTERRUPT_FP_UNAVAIL: |
d4cf3892 | 700 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); |
7b701591 | 701 | kvmppc_account_exit(vcpu, FP_UNAVAIL); |
de368dce CE |
702 | r = RESUME_GUEST; |
703 | break; | |
704 | ||
4cd35f67 SW |
705 | #ifdef CONFIG_SPE |
706 | case BOOKE_INTERRUPT_SPE_UNAVAIL: { | |
707 | if (vcpu->arch.shared->msr & MSR_SPE) | |
708 | kvmppc_vcpu_enable_spe(vcpu); | |
709 | else | |
710 | kvmppc_booke_queue_irqprio(vcpu, | |
711 | BOOKE_IRQPRIO_SPE_UNAVAIL); | |
bb3a8a17 HB |
712 | r = RESUME_GUEST; |
713 | break; | |
4cd35f67 | 714 | } |
bb3a8a17 HB |
715 | |
716 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
717 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA); | |
718 | r = RESUME_GUEST; | |
719 | break; | |
720 | ||
721 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
722 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND); | |
723 | r = RESUME_GUEST; | |
724 | break; | |
4cd35f67 SW |
725 | #else |
726 | case BOOKE_INTERRUPT_SPE_UNAVAIL: | |
727 | /* | |
728 | * Guest wants SPE, but host kernel doesn't support it. Send | |
729 | * an "unimplemented operation" program check to the guest. | |
730 | */ | |
731 | kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV); | |
732 | r = RESUME_GUEST; | |
733 | break; | |
734 | ||
735 | /* | |
736 | * These really should never happen without CONFIG_SPE, | |
737 | * as we should never enable the real MSR[SPE] in the guest. | |
738 | */ | |
739 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
740 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
741 | printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n", | |
742 | __func__, exit_nr, vcpu->arch.pc); | |
743 | run->hw.hardware_exit_reason = exit_nr; | |
744 | r = RESUME_HOST; | |
745 | break; | |
746 | #endif | |
bb3a8a17 | 747 | |
bbf45ba5 | 748 | case BOOKE_INTERRUPT_DATA_STORAGE: |
daf5e271 LY |
749 | kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear, |
750 | vcpu->arch.fault_esr); | |
7b701591 | 751 | kvmppc_account_exit(vcpu, DSI_EXITS); |
bbf45ba5 HB |
752 | r = RESUME_GUEST; |
753 | break; | |
754 | ||
755 | case BOOKE_INTERRUPT_INST_STORAGE: | |
daf5e271 | 756 | kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr); |
7b701591 | 757 | kvmppc_account_exit(vcpu, ISI_EXITS); |
bbf45ba5 HB |
758 | r = RESUME_GUEST; |
759 | break; | |
760 | ||
d30f6e48 SW |
761 | #ifdef CONFIG_KVM_BOOKE_HV |
762 | case BOOKE_INTERRUPT_HV_SYSCALL: | |
763 | if (!(vcpu->arch.shared->msr & MSR_PR)) { | |
764 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
765 | } else { | |
766 | /* | |
767 | * hcall from guest userspace -- send privileged | |
768 | * instruction program check. | |
769 | */ | |
770 | kvmppc_core_queue_program(vcpu, ESR_PPR); | |
771 | } | |
772 | ||
773 | r = RESUME_GUEST; | |
774 | break; | |
775 | #else | |
bbf45ba5 | 776 | case BOOKE_INTERRUPT_SYSCALL: |
2a342ed5 AG |
777 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
778 | (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { | |
779 | /* KVM PV hypercalls */ | |
780 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
781 | r = RESUME_GUEST; | |
782 | } else { | |
783 | /* Guest syscalls */ | |
784 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL); | |
785 | } | |
7b701591 | 786 | kvmppc_account_exit(vcpu, SYSCALL_EXITS); |
bbf45ba5 HB |
787 | r = RESUME_GUEST; |
788 | break; | |
d30f6e48 | 789 | #endif |
bbf45ba5 HB |
790 | |
791 | case BOOKE_INTERRUPT_DTLB_MISS: { | |
bbf45ba5 | 792 | unsigned long eaddr = vcpu->arch.fault_dear; |
7924bd41 | 793 | int gtlb_index; |
475e7cdd | 794 | gpa_t gpaddr; |
bbf45ba5 HB |
795 | gfn_t gfn; |
796 | ||
bf7ca4bd | 797 | #ifdef CONFIG_KVM_E500V2 |
a4cd8b23 SW |
798 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
799 | (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { | |
800 | kvmppc_map_magic(vcpu); | |
801 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); | |
802 | r = RESUME_GUEST; | |
803 | ||
804 | break; | |
805 | } | |
806 | #endif | |
807 | ||
bbf45ba5 | 808 | /* Check the guest TLB. */ |
fa86b8dd | 809 | gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); |
7924bd41 | 810 | if (gtlb_index < 0) { |
bbf45ba5 | 811 | /* The guest didn't have a mapping for it. */ |
daf5e271 LY |
812 | kvmppc_core_queue_dtlb_miss(vcpu, |
813 | vcpu->arch.fault_dear, | |
814 | vcpu->arch.fault_esr); | |
b52a638c | 815 | kvmppc_mmu_dtlb_miss(vcpu); |
7b701591 | 816 | kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
817 | r = RESUME_GUEST; |
818 | break; | |
819 | } | |
820 | ||
be8d1cae | 821 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
475e7cdd | 822 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
823 | |
824 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
825 | /* The guest TLB had a mapping, but the shadow TLB | |
826 | * didn't, and it is RAM. This could be because: | |
827 | * a) the entry is mapping the host kernel, or | |
828 | * b) the guest used a large mapping which we're faking | |
829 | * Either way, we need to satisfy the fault without | |
830 | * invoking the guest. */ | |
58a96214 | 831 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
7b701591 | 832 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); |
bbf45ba5 HB |
833 | r = RESUME_GUEST; |
834 | } else { | |
835 | /* Guest has mapped and accessed a page which is not | |
836 | * actually RAM. */ | |
475e7cdd | 837 | vcpu->arch.paddr_accessed = gpaddr; |
bbf45ba5 | 838 | r = kvmppc_emulate_mmio(run, vcpu); |
7b701591 | 839 | kvmppc_account_exit(vcpu, MMIO_EXITS); |
bbf45ba5 HB |
840 | } |
841 | ||
842 | break; | |
843 | } | |
844 | ||
845 | case BOOKE_INTERRUPT_ITLB_MISS: { | |
bbf45ba5 | 846 | unsigned long eaddr = vcpu->arch.pc; |
89168618 | 847 | gpa_t gpaddr; |
bbf45ba5 | 848 | gfn_t gfn; |
7924bd41 | 849 | int gtlb_index; |
bbf45ba5 HB |
850 | |
851 | r = RESUME_GUEST; | |
852 | ||
853 | /* Check the guest TLB. */ | |
fa86b8dd | 854 | gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); |
7924bd41 | 855 | if (gtlb_index < 0) { |
bbf45ba5 | 856 | /* The guest didn't have a mapping for it. */ |
d4cf3892 | 857 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); |
b52a638c | 858 | kvmppc_mmu_itlb_miss(vcpu); |
7b701591 | 859 | kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
860 | break; |
861 | } | |
862 | ||
7b701591 | 863 | kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); |
bbf45ba5 | 864 | |
be8d1cae | 865 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
89168618 | 866 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
867 | |
868 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
869 | /* The guest TLB had a mapping, but the shadow TLB | |
870 | * didn't. This could be because: | |
871 | * a) the entry is mapping the host kernel, or | |
872 | * b) the guest used a large mapping which we're faking | |
873 | * Either way, we need to satisfy the fault without | |
874 | * invoking the guest. */ | |
58a96214 | 875 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
bbf45ba5 HB |
876 | } else { |
877 | /* Guest mapped and leaped at non-RAM! */ | |
d4cf3892 | 878 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); |
bbf45ba5 HB |
879 | } |
880 | ||
881 | break; | |
882 | } | |
883 | ||
6a0ab738 HB |
884 | case BOOKE_INTERRUPT_DEBUG: { |
885 | u32 dbsr; | |
886 | ||
887 | vcpu->arch.pc = mfspr(SPRN_CSRR0); | |
888 | ||
889 | /* clear IAC events in DBSR register */ | |
890 | dbsr = mfspr(SPRN_DBSR); | |
891 | dbsr &= DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4; | |
892 | mtspr(SPRN_DBSR, dbsr); | |
893 | ||
894 | run->exit_reason = KVM_EXIT_DEBUG; | |
7b701591 | 895 | kvmppc_account_exit(vcpu, DEBUG_EXITS); |
6a0ab738 HB |
896 | r = RESUME_HOST; |
897 | break; | |
898 | } | |
899 | ||
bbf45ba5 HB |
900 | default: |
901 | printk(KERN_EMERG "exit_nr %d\n", exit_nr); | |
902 | BUG(); | |
903 | } | |
904 | ||
a8e4ef84 AG |
905 | /* |
906 | * To avoid clobbering exit_reason, only check for signals if we | |
907 | * aren't already exiting to userspace for some other reason. | |
908 | */ | |
bbf45ba5 | 909 | local_irq_disable(); |
a8e4ef84 AG |
910 | if (kvmppc_prepare_to_enter(vcpu, !(r & RESUME_HOST))) { |
911 | run->exit_reason = KVM_EXIT_INTR; | |
912 | r = (-EINTR << 2) | RESUME_HOST | (r & RESUME_FLAG_NV); | |
913 | kvmppc_account_exit(vcpu, SIGNAL_EXITS); | |
bbf45ba5 HB |
914 | } |
915 | ||
916 | return r; | |
917 | } | |
918 | ||
919 | /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */ | |
920 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
921 | { | |
082decf2 | 922 | int i; |
af8f38b3 | 923 | int r; |
082decf2 | 924 | |
bbf45ba5 | 925 | vcpu->arch.pc = 0; |
b5904972 | 926 | vcpu->arch.shared->pir = vcpu->vcpu_id; |
8e5b26b5 | 927 | kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */ |
d30f6e48 | 928 | kvmppc_set_msr(vcpu, 0); |
bbf45ba5 | 929 | |
d30f6e48 SW |
930 | #ifndef CONFIG_KVM_BOOKE_HV |
931 | vcpu->arch.shadow_msr = MSR_USER | MSR_DE | MSR_IS | MSR_DS; | |
49dd2c49 | 932 | vcpu->arch.shadow_pid = 1; |
d30f6e48 SW |
933 | vcpu->arch.shared->msr = 0; |
934 | #endif | |
49dd2c49 | 935 | |
082decf2 HB |
936 | /* Eye-catching numbers so we know if the guest takes an interrupt |
937 | * before it's programmed its own IVPR/IVORs. */ | |
bbf45ba5 | 938 | vcpu->arch.ivpr = 0x55550000; |
082decf2 HB |
939 | for (i = 0; i < BOOKE_IRQPRIO_MAX; i++) |
940 | vcpu->arch.ivor[i] = 0x7700 | i * 4; | |
bbf45ba5 | 941 | |
73e75b41 HB |
942 | kvmppc_init_timing_stats(vcpu); |
943 | ||
af8f38b3 AG |
944 | r = kvmppc_core_vcpu_setup(vcpu); |
945 | kvmppc_sanity_check(vcpu); | |
946 | return r; | |
bbf45ba5 HB |
947 | } |
948 | ||
949 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
950 | { | |
951 | int i; | |
952 | ||
953 | regs->pc = vcpu->arch.pc; | |
992b5b29 | 954 | regs->cr = kvmppc_get_cr(vcpu); |
bbf45ba5 HB |
955 | regs->ctr = vcpu->arch.ctr; |
956 | regs->lr = vcpu->arch.lr; | |
992b5b29 | 957 | regs->xer = kvmppc_get_xer(vcpu); |
666e7252 | 958 | regs->msr = vcpu->arch.shared->msr; |
de7906c3 AG |
959 | regs->srr0 = vcpu->arch.shared->srr0; |
960 | regs->srr1 = vcpu->arch.shared->srr1; | |
bbf45ba5 | 961 | regs->pid = vcpu->arch.pid; |
a73a9599 AG |
962 | regs->sprg0 = vcpu->arch.shared->sprg0; |
963 | regs->sprg1 = vcpu->arch.shared->sprg1; | |
964 | regs->sprg2 = vcpu->arch.shared->sprg2; | |
965 | regs->sprg3 = vcpu->arch.shared->sprg3; | |
b5904972 SW |
966 | regs->sprg4 = vcpu->arch.shared->sprg4; |
967 | regs->sprg5 = vcpu->arch.shared->sprg5; | |
968 | regs->sprg6 = vcpu->arch.shared->sprg6; | |
969 | regs->sprg7 = vcpu->arch.shared->sprg7; | |
bbf45ba5 HB |
970 | |
971 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) | |
8e5b26b5 | 972 | regs->gpr[i] = kvmppc_get_gpr(vcpu, i); |
bbf45ba5 HB |
973 | |
974 | return 0; | |
975 | } | |
976 | ||
977 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
978 | { | |
979 | int i; | |
980 | ||
981 | vcpu->arch.pc = regs->pc; | |
992b5b29 | 982 | kvmppc_set_cr(vcpu, regs->cr); |
bbf45ba5 HB |
983 | vcpu->arch.ctr = regs->ctr; |
984 | vcpu->arch.lr = regs->lr; | |
992b5b29 | 985 | kvmppc_set_xer(vcpu, regs->xer); |
b8fd68ac | 986 | kvmppc_set_msr(vcpu, regs->msr); |
de7906c3 AG |
987 | vcpu->arch.shared->srr0 = regs->srr0; |
988 | vcpu->arch.shared->srr1 = regs->srr1; | |
5ce941ee | 989 | kvmppc_set_pid(vcpu, regs->pid); |
a73a9599 AG |
990 | vcpu->arch.shared->sprg0 = regs->sprg0; |
991 | vcpu->arch.shared->sprg1 = regs->sprg1; | |
992 | vcpu->arch.shared->sprg2 = regs->sprg2; | |
993 | vcpu->arch.shared->sprg3 = regs->sprg3; | |
b5904972 SW |
994 | vcpu->arch.shared->sprg4 = regs->sprg4; |
995 | vcpu->arch.shared->sprg5 = regs->sprg5; | |
996 | vcpu->arch.shared->sprg6 = regs->sprg6; | |
997 | vcpu->arch.shared->sprg7 = regs->sprg7; | |
bbf45ba5 | 998 | |
8e5b26b5 AG |
999 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) |
1000 | kvmppc_set_gpr(vcpu, i, regs->gpr[i]); | |
bbf45ba5 HB |
1001 | |
1002 | return 0; | |
1003 | } | |
1004 | ||
5ce941ee SW |
1005 | static void get_sregs_base(struct kvm_vcpu *vcpu, |
1006 | struct kvm_sregs *sregs) | |
1007 | { | |
1008 | u64 tb = get_tb(); | |
1009 | ||
1010 | sregs->u.e.features |= KVM_SREGS_E_BASE; | |
1011 | ||
1012 | sregs->u.e.csrr0 = vcpu->arch.csrr0; | |
1013 | sregs->u.e.csrr1 = vcpu->arch.csrr1; | |
1014 | sregs->u.e.mcsr = vcpu->arch.mcsr; | |
d30f6e48 SW |
1015 | sregs->u.e.esr = get_guest_esr(vcpu); |
1016 | sregs->u.e.dear = get_guest_dear(vcpu); | |
5ce941ee SW |
1017 | sregs->u.e.tsr = vcpu->arch.tsr; |
1018 | sregs->u.e.tcr = vcpu->arch.tcr; | |
1019 | sregs->u.e.dec = kvmppc_get_dec(vcpu, tb); | |
1020 | sregs->u.e.tb = tb; | |
1021 | sregs->u.e.vrsave = vcpu->arch.vrsave; | |
1022 | } | |
1023 | ||
1024 | static int set_sregs_base(struct kvm_vcpu *vcpu, | |
1025 | struct kvm_sregs *sregs) | |
1026 | { | |
1027 | if (!(sregs->u.e.features & KVM_SREGS_E_BASE)) | |
1028 | return 0; | |
1029 | ||
1030 | vcpu->arch.csrr0 = sregs->u.e.csrr0; | |
1031 | vcpu->arch.csrr1 = sregs->u.e.csrr1; | |
1032 | vcpu->arch.mcsr = sregs->u.e.mcsr; | |
d30f6e48 SW |
1033 | set_guest_esr(vcpu, sregs->u.e.esr); |
1034 | set_guest_dear(vcpu, sregs->u.e.dear); | |
5ce941ee | 1035 | vcpu->arch.vrsave = sregs->u.e.vrsave; |
dfd4d47e | 1036 | kvmppc_set_tcr(vcpu, sregs->u.e.tcr); |
5ce941ee | 1037 | |
dfd4d47e | 1038 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) { |
5ce941ee | 1039 | vcpu->arch.dec = sregs->u.e.dec; |
dfd4d47e SW |
1040 | kvmppc_emulate_dec(vcpu); |
1041 | } | |
5ce941ee SW |
1042 | |
1043 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) { | |
dfd4d47e SW |
1044 | vcpu->arch.tsr = sregs->u.e.tsr; |
1045 | update_timer_ints(vcpu); | |
5ce941ee SW |
1046 | } |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | static void get_sregs_arch206(struct kvm_vcpu *vcpu, | |
1052 | struct kvm_sregs *sregs) | |
1053 | { | |
1054 | sregs->u.e.features |= KVM_SREGS_E_ARCH206; | |
1055 | ||
841741f2 | 1056 | sregs->u.e.pir = vcpu->vcpu_id; |
5ce941ee SW |
1057 | sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0; |
1058 | sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1; | |
1059 | sregs->u.e.decar = vcpu->arch.decar; | |
1060 | sregs->u.e.ivpr = vcpu->arch.ivpr; | |
1061 | } | |
1062 | ||
1063 | static int set_sregs_arch206(struct kvm_vcpu *vcpu, | |
1064 | struct kvm_sregs *sregs) | |
1065 | { | |
1066 | if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206)) | |
1067 | return 0; | |
1068 | ||
841741f2 | 1069 | if (sregs->u.e.pir != vcpu->vcpu_id) |
5ce941ee SW |
1070 | return -EINVAL; |
1071 | ||
1072 | vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0; | |
1073 | vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1; | |
1074 | vcpu->arch.decar = sregs->u.e.decar; | |
1075 | vcpu->arch.ivpr = sregs->u.e.ivpr; | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
1080 | void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
1081 | { | |
1082 | sregs->u.e.features |= KVM_SREGS_E_IVOR; | |
1083 | ||
1084 | sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; | |
1085 | sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; | |
1086 | sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; | |
1087 | sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; | |
1088 | sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; | |
1089 | sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; | |
1090 | sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; | |
1091 | sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; | |
1092 | sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; | |
1093 | sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; | |
1094 | sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; | |
1095 | sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; | |
1096 | sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; | |
1097 | sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; | |
1098 | sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; | |
1099 | sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; | |
1100 | } | |
1101 | ||
1102 | int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
1103 | { | |
1104 | if (!(sregs->u.e.features & KVM_SREGS_E_IVOR)) | |
1105 | return 0; | |
1106 | ||
1107 | vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0]; | |
1108 | vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1]; | |
1109 | vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2]; | |
1110 | vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3]; | |
1111 | vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4]; | |
1112 | vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5]; | |
1113 | vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6]; | |
1114 | vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7]; | |
1115 | vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8]; | |
1116 | vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9]; | |
1117 | vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10]; | |
1118 | vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11]; | |
1119 | vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12]; | |
1120 | vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13]; | |
1121 | vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14]; | |
1122 | vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15]; | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
bbf45ba5 HB |
1127 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
1128 | struct kvm_sregs *sregs) | |
1129 | { | |
5ce941ee SW |
1130 | sregs->pvr = vcpu->arch.pvr; |
1131 | ||
1132 | get_sregs_base(vcpu, sregs); | |
1133 | get_sregs_arch206(vcpu, sregs); | |
1134 | kvmppc_core_get_sregs(vcpu, sregs); | |
1135 | return 0; | |
bbf45ba5 HB |
1136 | } |
1137 | ||
1138 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
1139 | struct kvm_sregs *sregs) | |
1140 | { | |
5ce941ee SW |
1141 | int ret; |
1142 | ||
1143 | if (vcpu->arch.pvr != sregs->pvr) | |
1144 | return -EINVAL; | |
1145 | ||
1146 | ret = set_sregs_base(vcpu, sregs); | |
1147 | if (ret < 0) | |
1148 | return ret; | |
1149 | ||
1150 | ret = set_sregs_arch206(vcpu, sregs); | |
1151 | if (ret < 0) | |
1152 | return ret; | |
1153 | ||
1154 | return kvmppc_core_set_sregs(vcpu, sregs); | |
bbf45ba5 HB |
1155 | } |
1156 | ||
31f3438e PM |
1157 | int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) |
1158 | { | |
1159 | return -EINVAL; | |
1160 | } | |
1161 | ||
1162 | int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) | |
1163 | { | |
1164 | return -EINVAL; | |
1165 | } | |
1166 | ||
bbf45ba5 HB |
1167 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
1168 | { | |
1169 | return -ENOTSUPP; | |
1170 | } | |
1171 | ||
1172 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
1173 | { | |
1174 | return -ENOTSUPP; | |
1175 | } | |
1176 | ||
bbf45ba5 HB |
1177 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, |
1178 | struct kvm_translation *tr) | |
1179 | { | |
98001d8d AK |
1180 | int r; |
1181 | ||
98001d8d | 1182 | r = kvmppc_core_vcpu_translate(vcpu, tr); |
98001d8d | 1183 | return r; |
bbf45ba5 | 1184 | } |
d9fbd03d | 1185 | |
4e755758 AG |
1186 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
1187 | { | |
1188 | return -ENOTSUPP; | |
1189 | } | |
1190 | ||
f9e0554d PM |
1191 | int kvmppc_core_prepare_memory_region(struct kvm *kvm, |
1192 | struct kvm_userspace_memory_region *mem) | |
1193 | { | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | void kvmppc_core_commit_memory_region(struct kvm *kvm, | |
1198 | struct kvm_userspace_memory_region *mem) | |
1199 | { | |
1200 | } | |
1201 | ||
dfd4d47e SW |
1202 | void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr) |
1203 | { | |
1204 | vcpu->arch.tcr = new_tcr; | |
1205 | update_timer_ints(vcpu); | |
1206 | } | |
1207 | ||
1208 | void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) | |
1209 | { | |
1210 | set_bits(tsr_bits, &vcpu->arch.tsr); | |
1211 | smp_wmb(); | |
1212 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1213 | kvm_vcpu_kick(vcpu); | |
1214 | } | |
1215 | ||
1216 | void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits) | |
1217 | { | |
1218 | clear_bits(tsr_bits, &vcpu->arch.tsr); | |
1219 | update_timer_ints(vcpu); | |
1220 | } | |
1221 | ||
1222 | void kvmppc_decrementer_func(unsigned long data) | |
1223 | { | |
1224 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; | |
1225 | ||
1226 | kvmppc_set_tsr_bits(vcpu, TSR_DIS); | |
1227 | } | |
1228 | ||
94fa9d99 SW |
1229 | void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1230 | { | |
d30f6e48 | 1231 | current->thread.kvm_vcpu = vcpu; |
94fa9d99 SW |
1232 | } |
1233 | ||
1234 | void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu) | |
1235 | { | |
d30f6e48 | 1236 | current->thread.kvm_vcpu = NULL; |
94fa9d99 SW |
1237 | } |
1238 | ||
2986b8c7 | 1239 | int __init kvmppc_booke_init(void) |
d9fbd03d | 1240 | { |
d30f6e48 | 1241 | #ifndef CONFIG_KVM_BOOKE_HV |
d9fbd03d HB |
1242 | unsigned long ivor[16]; |
1243 | unsigned long max_ivor = 0; | |
1244 | int i; | |
1245 | ||
1246 | /* We install our own exception handlers by hijacking IVPR. IVPR must | |
1247 | * be 16-bit aligned, so we need a 64KB allocation. */ | |
1248 | kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
1249 | VCPU_SIZE_ORDER); | |
1250 | if (!kvmppc_booke_handlers) | |
1251 | return -ENOMEM; | |
1252 | ||
1253 | /* XXX make sure our handlers are smaller than Linux's */ | |
1254 | ||
1255 | /* Copy our interrupt handlers to match host IVORs. That way we don't | |
1256 | * have to swap the IVORs on every guest/host transition. */ | |
1257 | ivor[0] = mfspr(SPRN_IVOR0); | |
1258 | ivor[1] = mfspr(SPRN_IVOR1); | |
1259 | ivor[2] = mfspr(SPRN_IVOR2); | |
1260 | ivor[3] = mfspr(SPRN_IVOR3); | |
1261 | ivor[4] = mfspr(SPRN_IVOR4); | |
1262 | ivor[5] = mfspr(SPRN_IVOR5); | |
1263 | ivor[6] = mfspr(SPRN_IVOR6); | |
1264 | ivor[7] = mfspr(SPRN_IVOR7); | |
1265 | ivor[8] = mfspr(SPRN_IVOR8); | |
1266 | ivor[9] = mfspr(SPRN_IVOR9); | |
1267 | ivor[10] = mfspr(SPRN_IVOR10); | |
1268 | ivor[11] = mfspr(SPRN_IVOR11); | |
1269 | ivor[12] = mfspr(SPRN_IVOR12); | |
1270 | ivor[13] = mfspr(SPRN_IVOR13); | |
1271 | ivor[14] = mfspr(SPRN_IVOR14); | |
1272 | ivor[15] = mfspr(SPRN_IVOR15); | |
1273 | ||
1274 | for (i = 0; i < 16; i++) { | |
1275 | if (ivor[i] > max_ivor) | |
1276 | max_ivor = ivor[i]; | |
1277 | ||
1278 | memcpy((void *)kvmppc_booke_handlers + ivor[i], | |
1279 | kvmppc_handlers_start + i * kvmppc_handler_len, | |
1280 | kvmppc_handler_len); | |
1281 | } | |
1282 | flush_icache_range(kvmppc_booke_handlers, | |
1283 | kvmppc_booke_handlers + max_ivor + kvmppc_handler_len); | |
d30f6e48 | 1284 | #endif /* !BOOKE_HV */ |
db93f574 | 1285 | return 0; |
d9fbd03d HB |
1286 | } |
1287 | ||
db93f574 | 1288 | void __exit kvmppc_booke_exit(void) |
d9fbd03d HB |
1289 | { |
1290 | free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER); | |
1291 | kvm_exit(); | |
1292 | } |