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bbf45ba5 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2007 | |
4cd35f67 | 16 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
bbf45ba5 HB |
17 | * |
18 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
19 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
20 | */ | |
21 | ||
22 | #include <linux/errno.h> | |
23 | #include <linux/err.h> | |
24 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 25 | #include <linux/gfp.h> |
bbf45ba5 HB |
26 | #include <linux/module.h> |
27 | #include <linux/vmalloc.h> | |
28 | #include <linux/fs.h> | |
7924bd41 | 29 | |
bbf45ba5 HB |
30 | #include <asm/cputable.h> |
31 | #include <asm/uaccess.h> | |
32 | #include <asm/kvm_ppc.h> | |
73e75b41 | 33 | #include "timing.h" |
d9fbd03d | 34 | #include <asm/cacheflush.h> |
bbf45ba5 | 35 | |
75f74f0d | 36 | #include "booke.h" |
bbf45ba5 | 37 | |
d9fbd03d HB |
38 | unsigned long kvmppc_booke_handlers; |
39 | ||
bbf45ba5 HB |
40 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
41 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
42 | ||
43 | struct kvm_stats_debugfs_item debugfs_entries[] = { | |
bbf45ba5 HB |
44 | { "mmio", VCPU_STAT(mmio_exits) }, |
45 | { "dcr", VCPU_STAT(dcr_exits) }, | |
46 | { "sig", VCPU_STAT(signal_exits) }, | |
bbf45ba5 HB |
47 | { "itlb_r", VCPU_STAT(itlb_real_miss_exits) }, |
48 | { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) }, | |
49 | { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) }, | |
50 | { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) }, | |
51 | { "sysc", VCPU_STAT(syscall_exits) }, | |
52 | { "isi", VCPU_STAT(isi_exits) }, | |
53 | { "dsi", VCPU_STAT(dsi_exits) }, | |
54 | { "inst_emu", VCPU_STAT(emulated_inst_exits) }, | |
55 | { "dec", VCPU_STAT(dec_exits) }, | |
56 | { "ext_intr", VCPU_STAT(ext_intr_exits) }, | |
45c5eb67 | 57 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
bbf45ba5 HB |
58 | { NULL } |
59 | }; | |
60 | ||
bbf45ba5 HB |
61 | /* TODO: use vcpu_printf() */ |
62 | void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu) | |
63 | { | |
64 | int i; | |
65 | ||
666e7252 | 66 | printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr); |
5cf8ca22 | 67 | printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr); |
de7906c3 AG |
68 | printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0, |
69 | vcpu->arch.shared->srr1); | |
bbf45ba5 HB |
70 | |
71 | printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions); | |
72 | ||
73 | for (i = 0; i < 32; i += 4) { | |
5cf8ca22 | 74 | printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i, |
8e5b26b5 AG |
75 | kvmppc_get_gpr(vcpu, i), |
76 | kvmppc_get_gpr(vcpu, i+1), | |
77 | kvmppc_get_gpr(vcpu, i+2), | |
78 | kvmppc_get_gpr(vcpu, i+3)); | |
bbf45ba5 HB |
79 | } |
80 | } | |
81 | ||
4cd35f67 SW |
82 | #ifdef CONFIG_SPE |
83 | void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu) | |
84 | { | |
85 | preempt_disable(); | |
86 | enable_kernel_spe(); | |
87 | kvmppc_save_guest_spe(vcpu); | |
88 | vcpu->arch.shadow_msr &= ~MSR_SPE; | |
89 | preempt_enable(); | |
90 | } | |
91 | ||
92 | static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu) | |
93 | { | |
94 | preempt_disable(); | |
95 | enable_kernel_spe(); | |
96 | kvmppc_load_guest_spe(vcpu); | |
97 | vcpu->arch.shadow_msr |= MSR_SPE; | |
98 | preempt_enable(); | |
99 | } | |
100 | ||
101 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
102 | { | |
103 | if (vcpu->arch.shared->msr & MSR_SPE) { | |
104 | if (!(vcpu->arch.shadow_msr & MSR_SPE)) | |
105 | kvmppc_vcpu_enable_spe(vcpu); | |
106 | } else if (vcpu->arch.shadow_msr & MSR_SPE) { | |
107 | kvmppc_vcpu_disable_spe(vcpu); | |
108 | } | |
109 | } | |
110 | #else | |
111 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
112 | { | |
113 | } | |
114 | #endif | |
115 | ||
dd9ebf1f LY |
116 | /* |
117 | * Helper function for "full" MSR writes. No need to call this if only | |
118 | * EE/CE/ME/DE/RI are changing. | |
119 | */ | |
4cd35f67 SW |
120 | void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr) |
121 | { | |
dd9ebf1f | 122 | u32 old_msr = vcpu->arch.shared->msr; |
4cd35f67 SW |
123 | |
124 | vcpu->arch.shared->msr = new_msr; | |
125 | ||
dd9ebf1f | 126 | kvmppc_mmu_msr_notify(vcpu, old_msr); |
4cd35f67 SW |
127 | kvmppc_vcpu_sync_spe(vcpu); |
128 | } | |
129 | ||
d4cf3892 HB |
130 | static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, |
131 | unsigned int priority) | |
9dd921cf | 132 | { |
9dd921cf HB |
133 | set_bit(priority, &vcpu->arch.pending_exceptions); |
134 | } | |
135 | ||
daf5e271 LY |
136 | static void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, |
137 | ulong dear_flags, ulong esr_flags) | |
9dd921cf | 138 | { |
daf5e271 LY |
139 | vcpu->arch.queued_dear = dear_flags; |
140 | vcpu->arch.queued_esr = esr_flags; | |
141 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS); | |
142 | } | |
143 | ||
144 | static void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, | |
145 | ulong dear_flags, ulong esr_flags) | |
146 | { | |
147 | vcpu->arch.queued_dear = dear_flags; | |
148 | vcpu->arch.queued_esr = esr_flags; | |
149 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE); | |
150 | } | |
151 | ||
152 | static void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, | |
153 | ulong esr_flags) | |
154 | { | |
155 | vcpu->arch.queued_esr = esr_flags; | |
156 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE); | |
157 | } | |
158 | ||
159 | void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags) | |
160 | { | |
161 | vcpu->arch.queued_esr = esr_flags; | |
d4cf3892 | 162 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM); |
9dd921cf HB |
163 | } |
164 | ||
165 | void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu) | |
166 | { | |
d4cf3892 | 167 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER); |
9dd921cf HB |
168 | } |
169 | ||
170 | int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu) | |
171 | { | |
d4cf3892 | 172 | return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); |
9dd921cf HB |
173 | } |
174 | ||
7706664d AG |
175 | void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu) |
176 | { | |
177 | clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); | |
178 | } | |
179 | ||
9dd921cf HB |
180 | void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, |
181 | struct kvm_interrupt *irq) | |
182 | { | |
c5335f17 AG |
183 | unsigned int prio = BOOKE_IRQPRIO_EXTERNAL; |
184 | ||
185 | if (irq->irq == KVM_INTERRUPT_SET_LEVEL) | |
186 | prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL; | |
187 | ||
188 | kvmppc_booke_queue_irqprio(vcpu, prio); | |
9dd921cf HB |
189 | } |
190 | ||
4496f974 AG |
191 | void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu, |
192 | struct kvm_interrupt *irq) | |
193 | { | |
194 | clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions); | |
c5335f17 | 195 | clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions); |
4496f974 AG |
196 | } |
197 | ||
d4cf3892 HB |
198 | /* Deliver the interrupt of the corresponding priority, if possible. */ |
199 | static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, | |
200 | unsigned int priority) | |
bbf45ba5 | 201 | { |
d4cf3892 | 202 | int allowed = 0; |
6045be5d | 203 | ulong uninitialized_var(msr_mask); |
daf5e271 | 204 | bool update_esr = false, update_dear = false; |
5c6cedf4 AG |
205 | ulong crit_raw = vcpu->arch.shared->critical; |
206 | ulong crit_r1 = kvmppc_get_gpr(vcpu, 1); | |
207 | bool crit; | |
c5335f17 | 208 | bool keep_irq = false; |
5c6cedf4 AG |
209 | |
210 | /* Truncate crit indicators in 32 bit mode */ | |
211 | if (!(vcpu->arch.shared->msr & MSR_SF)) { | |
212 | crit_raw &= 0xffffffff; | |
213 | crit_r1 &= 0xffffffff; | |
214 | } | |
215 | ||
216 | /* Critical section when crit == r1 */ | |
217 | crit = (crit_raw == crit_r1); | |
218 | /* ... and we're in supervisor mode */ | |
219 | crit = crit && !(vcpu->arch.shared->msr & MSR_PR); | |
d4cf3892 | 220 | |
c5335f17 AG |
221 | if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) { |
222 | priority = BOOKE_IRQPRIO_EXTERNAL; | |
223 | keep_irq = true; | |
224 | } | |
225 | ||
d4cf3892 | 226 | switch (priority) { |
d4cf3892 | 227 | case BOOKE_IRQPRIO_DTLB_MISS: |
d4cf3892 | 228 | case BOOKE_IRQPRIO_DATA_STORAGE: |
daf5e271 LY |
229 | update_dear = true; |
230 | /* fall through */ | |
d4cf3892 | 231 | case BOOKE_IRQPRIO_INST_STORAGE: |
daf5e271 LY |
232 | case BOOKE_IRQPRIO_PROGRAM: |
233 | update_esr = true; | |
234 | /* fall through */ | |
235 | case BOOKE_IRQPRIO_ITLB_MISS: | |
236 | case BOOKE_IRQPRIO_SYSCALL: | |
d4cf3892 | 237 | case BOOKE_IRQPRIO_FP_UNAVAIL: |
bb3a8a17 HB |
238 | case BOOKE_IRQPRIO_SPE_UNAVAIL: |
239 | case BOOKE_IRQPRIO_SPE_FP_DATA: | |
240 | case BOOKE_IRQPRIO_SPE_FP_ROUND: | |
d4cf3892 HB |
241 | case BOOKE_IRQPRIO_AP_UNAVAIL: |
242 | case BOOKE_IRQPRIO_ALIGNMENT: | |
243 | allowed = 1; | |
244 | msr_mask = MSR_CE|MSR_ME|MSR_DE; | |
bbf45ba5 | 245 | break; |
d4cf3892 HB |
246 | case BOOKE_IRQPRIO_CRITICAL: |
247 | case BOOKE_IRQPRIO_WATCHDOG: | |
666e7252 | 248 | allowed = vcpu->arch.shared->msr & MSR_CE; |
d4cf3892 | 249 | msr_mask = MSR_ME; |
bbf45ba5 | 250 | break; |
d4cf3892 | 251 | case BOOKE_IRQPRIO_MACHINE_CHECK: |
666e7252 | 252 | allowed = vcpu->arch.shared->msr & MSR_ME; |
d4cf3892 | 253 | msr_mask = 0; |
bbf45ba5 | 254 | break; |
d4cf3892 HB |
255 | case BOOKE_IRQPRIO_EXTERNAL: |
256 | case BOOKE_IRQPRIO_DECREMENTER: | |
257 | case BOOKE_IRQPRIO_FIT: | |
666e7252 | 258 | allowed = vcpu->arch.shared->msr & MSR_EE; |
5c6cedf4 | 259 | allowed = allowed && !crit; |
d4cf3892 | 260 | msr_mask = MSR_CE|MSR_ME|MSR_DE; |
bbf45ba5 | 261 | break; |
d4cf3892 | 262 | case BOOKE_IRQPRIO_DEBUG: |
666e7252 | 263 | allowed = vcpu->arch.shared->msr & MSR_DE; |
d4cf3892 | 264 | msr_mask = MSR_ME; |
bbf45ba5 | 265 | break; |
bbf45ba5 HB |
266 | } |
267 | ||
d4cf3892 | 268 | if (allowed) { |
de7906c3 AG |
269 | vcpu->arch.shared->srr0 = vcpu->arch.pc; |
270 | vcpu->arch.shared->srr1 = vcpu->arch.shared->msr; | |
d4cf3892 | 271 | vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority]; |
daf5e271 | 272 | if (update_esr == true) |
b5904972 | 273 | vcpu->arch.shared->esr = vcpu->arch.queued_esr; |
daf5e271 | 274 | if (update_dear == true) |
5e030186 | 275 | vcpu->arch.shared->dar = vcpu->arch.queued_dear; |
666e7252 | 276 | kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask); |
bbf45ba5 | 277 | |
c5335f17 AG |
278 | if (!keep_irq) |
279 | clear_bit(priority, &vcpu->arch.pending_exceptions); | |
bbf45ba5 HB |
280 | } |
281 | ||
d4cf3892 | 282 | return allowed; |
bbf45ba5 HB |
283 | } |
284 | ||
c59a6a3e | 285 | static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu) |
bbf45ba5 HB |
286 | { |
287 | unsigned long *pending = &vcpu->arch.pending_exceptions; | |
bbf45ba5 HB |
288 | unsigned int priority; |
289 | ||
9ab80843 | 290 | priority = __ffs(*pending); |
bdc89f13 | 291 | while (priority <= BOOKE_IRQPRIO_MAX) { |
d4cf3892 | 292 | if (kvmppc_booke_irqprio_deliver(vcpu, priority)) |
bbf45ba5 | 293 | break; |
bbf45ba5 HB |
294 | |
295 | priority = find_next_bit(pending, | |
296 | BITS_PER_BYTE * sizeof(*pending), | |
297 | priority + 1); | |
298 | } | |
90bba358 AG |
299 | |
300 | /* Tell the guest about our interrupt status */ | |
29ac26ef | 301 | vcpu->arch.shared->int_pending = !!*pending; |
bbf45ba5 HB |
302 | } |
303 | ||
c59a6a3e SW |
304 | /* Check pending exceptions and deliver one, if possible. */ |
305 | void kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu) | |
306 | { | |
307 | WARN_ON_ONCE(!irqs_disabled()); | |
308 | ||
309 | kvmppc_core_check_exceptions(vcpu); | |
310 | ||
311 | if (vcpu->arch.shared->msr & MSR_WE) { | |
312 | local_irq_enable(); | |
313 | kvm_vcpu_block(vcpu); | |
314 | local_irq_disable(); | |
315 | ||
316 | kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS); | |
317 | kvmppc_core_check_exceptions(vcpu); | |
318 | }; | |
319 | } | |
320 | ||
df6909e5 PM |
321 | int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
322 | { | |
323 | int ret; | |
324 | ||
af8f38b3 AG |
325 | if (!vcpu->arch.sane) { |
326 | kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
327 | return -EINVAL; | |
328 | } | |
329 | ||
df6909e5 | 330 | local_irq_disable(); |
1d1ef222 | 331 | |
25051b5a SW |
332 | kvmppc_core_prepare_to_enter(vcpu); |
333 | ||
1d1ef222 SW |
334 | if (signal_pending(current)) { |
335 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
336 | ret = -EINTR; | |
337 | goto out; | |
338 | } | |
339 | ||
df6909e5 PM |
340 | kvm_guest_enter(); |
341 | ret = __kvmppc_vcpu_run(kvm_run, vcpu); | |
342 | kvm_guest_exit(); | |
df6909e5 | 343 | |
1d1ef222 SW |
344 | out: |
345 | local_irq_enable(); | |
df6909e5 PM |
346 | return ret; |
347 | } | |
348 | ||
bbf45ba5 HB |
349 | /** |
350 | * kvmppc_handle_exit | |
351 | * | |
352 | * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) | |
353 | */ | |
354 | int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
355 | unsigned int exit_nr) | |
356 | { | |
357 | enum emulation_result er; | |
358 | int r = RESUME_HOST; | |
359 | ||
73e75b41 HB |
360 | /* update before a new last_exit_type is rewritten */ |
361 | kvmppc_update_timing_stats(vcpu); | |
362 | ||
bbf45ba5 HB |
363 | local_irq_enable(); |
364 | ||
365 | run->exit_reason = KVM_EXIT_UNKNOWN; | |
366 | run->ready_for_interrupt_injection = 1; | |
367 | ||
368 | switch (exit_nr) { | |
369 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
370 | printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR)); | |
371 | kvmppc_dump_vcpu(vcpu); | |
372 | r = RESUME_HOST; | |
373 | break; | |
374 | ||
375 | case BOOKE_INTERRUPT_EXTERNAL: | |
7b701591 | 376 | kvmppc_account_exit(vcpu, EXT_INTR_EXITS); |
1b6766c7 HB |
377 | if (need_resched()) |
378 | cond_resched(); | |
379 | r = RESUME_GUEST; | |
380 | break; | |
381 | ||
bbf45ba5 HB |
382 | case BOOKE_INTERRUPT_DECREMENTER: |
383 | /* Since we switched IVPR back to the host's value, the host | |
384 | * handled this interrupt the moment we enabled interrupts. | |
385 | * Now we just offer it a chance to reschedule the guest. */ | |
7b701591 | 386 | kvmppc_account_exit(vcpu, DEC_EXITS); |
bbf45ba5 HB |
387 | if (need_resched()) |
388 | cond_resched(); | |
bbf45ba5 HB |
389 | r = RESUME_GUEST; |
390 | break; | |
391 | ||
392 | case BOOKE_INTERRUPT_PROGRAM: | |
666e7252 | 393 | if (vcpu->arch.shared->msr & MSR_PR) { |
bbf45ba5 HB |
394 | /* Program traps generated by user-level software must be handled |
395 | * by the guest kernel. */ | |
daf5e271 | 396 | kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr); |
bbf45ba5 | 397 | r = RESUME_GUEST; |
7b701591 | 398 | kvmppc_account_exit(vcpu, USR_PR_INST); |
bbf45ba5 HB |
399 | break; |
400 | } | |
401 | ||
402 | er = kvmppc_emulate_instruction(run, vcpu); | |
403 | switch (er) { | |
404 | case EMULATE_DONE: | |
73e75b41 | 405 | /* don't overwrite subtypes, just account kvm_stats */ |
7b701591 | 406 | kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS); |
bbf45ba5 HB |
407 | /* Future optimization: only reload non-volatiles if |
408 | * they were actually modified by emulation. */ | |
bbf45ba5 HB |
409 | r = RESUME_GUEST_NV; |
410 | break; | |
411 | case EMULATE_DO_DCR: | |
412 | run->exit_reason = KVM_EXIT_DCR; | |
413 | r = RESUME_HOST; | |
414 | break; | |
415 | case EMULATE_FAIL: | |
416 | /* XXX Deliver Program interrupt to guest. */ | |
5cf8ca22 | 417 | printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", |
bbf45ba5 HB |
418 | __func__, vcpu->arch.pc, vcpu->arch.last_inst); |
419 | /* For debugging, encode the failing instruction and | |
420 | * report it to userspace. */ | |
421 | run->hw.hardware_exit_reason = ~0ULL << 32; | |
422 | run->hw.hardware_exit_reason |= vcpu->arch.last_inst; | |
423 | r = RESUME_HOST; | |
424 | break; | |
425 | default: | |
426 | BUG(); | |
427 | } | |
428 | break; | |
429 | ||
de368dce | 430 | case BOOKE_INTERRUPT_FP_UNAVAIL: |
d4cf3892 | 431 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); |
7b701591 | 432 | kvmppc_account_exit(vcpu, FP_UNAVAIL); |
de368dce CE |
433 | r = RESUME_GUEST; |
434 | break; | |
435 | ||
4cd35f67 SW |
436 | #ifdef CONFIG_SPE |
437 | case BOOKE_INTERRUPT_SPE_UNAVAIL: { | |
438 | if (vcpu->arch.shared->msr & MSR_SPE) | |
439 | kvmppc_vcpu_enable_spe(vcpu); | |
440 | else | |
441 | kvmppc_booke_queue_irqprio(vcpu, | |
442 | BOOKE_IRQPRIO_SPE_UNAVAIL); | |
bb3a8a17 HB |
443 | r = RESUME_GUEST; |
444 | break; | |
4cd35f67 | 445 | } |
bb3a8a17 HB |
446 | |
447 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
448 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA); | |
449 | r = RESUME_GUEST; | |
450 | break; | |
451 | ||
452 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
453 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND); | |
454 | r = RESUME_GUEST; | |
455 | break; | |
4cd35f67 SW |
456 | #else |
457 | case BOOKE_INTERRUPT_SPE_UNAVAIL: | |
458 | /* | |
459 | * Guest wants SPE, but host kernel doesn't support it. Send | |
460 | * an "unimplemented operation" program check to the guest. | |
461 | */ | |
462 | kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV); | |
463 | r = RESUME_GUEST; | |
464 | break; | |
465 | ||
466 | /* | |
467 | * These really should never happen without CONFIG_SPE, | |
468 | * as we should never enable the real MSR[SPE] in the guest. | |
469 | */ | |
470 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
471 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
472 | printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n", | |
473 | __func__, exit_nr, vcpu->arch.pc); | |
474 | run->hw.hardware_exit_reason = exit_nr; | |
475 | r = RESUME_HOST; | |
476 | break; | |
477 | #endif | |
bb3a8a17 | 478 | |
bbf45ba5 | 479 | case BOOKE_INTERRUPT_DATA_STORAGE: |
daf5e271 LY |
480 | kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear, |
481 | vcpu->arch.fault_esr); | |
7b701591 | 482 | kvmppc_account_exit(vcpu, DSI_EXITS); |
bbf45ba5 HB |
483 | r = RESUME_GUEST; |
484 | break; | |
485 | ||
486 | case BOOKE_INTERRUPT_INST_STORAGE: | |
daf5e271 | 487 | kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr); |
7b701591 | 488 | kvmppc_account_exit(vcpu, ISI_EXITS); |
bbf45ba5 HB |
489 | r = RESUME_GUEST; |
490 | break; | |
491 | ||
492 | case BOOKE_INTERRUPT_SYSCALL: | |
2a342ed5 AG |
493 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
494 | (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { | |
495 | /* KVM PV hypercalls */ | |
496 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
497 | r = RESUME_GUEST; | |
498 | } else { | |
499 | /* Guest syscalls */ | |
500 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL); | |
501 | } | |
7b701591 | 502 | kvmppc_account_exit(vcpu, SYSCALL_EXITS); |
bbf45ba5 HB |
503 | r = RESUME_GUEST; |
504 | break; | |
505 | ||
506 | case BOOKE_INTERRUPT_DTLB_MISS: { | |
bbf45ba5 | 507 | unsigned long eaddr = vcpu->arch.fault_dear; |
7924bd41 | 508 | int gtlb_index; |
475e7cdd | 509 | gpa_t gpaddr; |
bbf45ba5 HB |
510 | gfn_t gfn; |
511 | ||
a4cd8b23 SW |
512 | #ifdef CONFIG_KVM_E500 |
513 | if (!(vcpu->arch.shared->msr & MSR_PR) && | |
514 | (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { | |
515 | kvmppc_map_magic(vcpu); | |
516 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); | |
517 | r = RESUME_GUEST; | |
518 | ||
519 | break; | |
520 | } | |
521 | #endif | |
522 | ||
bbf45ba5 | 523 | /* Check the guest TLB. */ |
fa86b8dd | 524 | gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); |
7924bd41 | 525 | if (gtlb_index < 0) { |
bbf45ba5 | 526 | /* The guest didn't have a mapping for it. */ |
daf5e271 LY |
527 | kvmppc_core_queue_dtlb_miss(vcpu, |
528 | vcpu->arch.fault_dear, | |
529 | vcpu->arch.fault_esr); | |
b52a638c | 530 | kvmppc_mmu_dtlb_miss(vcpu); |
7b701591 | 531 | kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
532 | r = RESUME_GUEST; |
533 | break; | |
534 | } | |
535 | ||
be8d1cae | 536 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
475e7cdd | 537 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
538 | |
539 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
540 | /* The guest TLB had a mapping, but the shadow TLB | |
541 | * didn't, and it is RAM. This could be because: | |
542 | * a) the entry is mapping the host kernel, or | |
543 | * b) the guest used a large mapping which we're faking | |
544 | * Either way, we need to satisfy the fault without | |
545 | * invoking the guest. */ | |
58a96214 | 546 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
7b701591 | 547 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); |
bbf45ba5 HB |
548 | r = RESUME_GUEST; |
549 | } else { | |
550 | /* Guest has mapped and accessed a page which is not | |
551 | * actually RAM. */ | |
475e7cdd | 552 | vcpu->arch.paddr_accessed = gpaddr; |
bbf45ba5 | 553 | r = kvmppc_emulate_mmio(run, vcpu); |
7b701591 | 554 | kvmppc_account_exit(vcpu, MMIO_EXITS); |
bbf45ba5 HB |
555 | } |
556 | ||
557 | break; | |
558 | } | |
559 | ||
560 | case BOOKE_INTERRUPT_ITLB_MISS: { | |
bbf45ba5 | 561 | unsigned long eaddr = vcpu->arch.pc; |
89168618 | 562 | gpa_t gpaddr; |
bbf45ba5 | 563 | gfn_t gfn; |
7924bd41 | 564 | int gtlb_index; |
bbf45ba5 HB |
565 | |
566 | r = RESUME_GUEST; | |
567 | ||
568 | /* Check the guest TLB. */ | |
fa86b8dd | 569 | gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); |
7924bd41 | 570 | if (gtlb_index < 0) { |
bbf45ba5 | 571 | /* The guest didn't have a mapping for it. */ |
d4cf3892 | 572 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); |
b52a638c | 573 | kvmppc_mmu_itlb_miss(vcpu); |
7b701591 | 574 | kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
575 | break; |
576 | } | |
577 | ||
7b701591 | 578 | kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); |
bbf45ba5 | 579 | |
be8d1cae | 580 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
89168618 | 581 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
582 | |
583 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
584 | /* The guest TLB had a mapping, but the shadow TLB | |
585 | * didn't. This could be because: | |
586 | * a) the entry is mapping the host kernel, or | |
587 | * b) the guest used a large mapping which we're faking | |
588 | * Either way, we need to satisfy the fault without | |
589 | * invoking the guest. */ | |
58a96214 | 590 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
bbf45ba5 HB |
591 | } else { |
592 | /* Guest mapped and leaped at non-RAM! */ | |
d4cf3892 | 593 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); |
bbf45ba5 HB |
594 | } |
595 | ||
596 | break; | |
597 | } | |
598 | ||
6a0ab738 HB |
599 | case BOOKE_INTERRUPT_DEBUG: { |
600 | u32 dbsr; | |
601 | ||
602 | vcpu->arch.pc = mfspr(SPRN_CSRR0); | |
603 | ||
604 | /* clear IAC events in DBSR register */ | |
605 | dbsr = mfspr(SPRN_DBSR); | |
606 | dbsr &= DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4; | |
607 | mtspr(SPRN_DBSR, dbsr); | |
608 | ||
609 | run->exit_reason = KVM_EXIT_DEBUG; | |
7b701591 | 610 | kvmppc_account_exit(vcpu, DEBUG_EXITS); |
6a0ab738 HB |
611 | r = RESUME_HOST; |
612 | break; | |
613 | } | |
614 | ||
bbf45ba5 HB |
615 | default: |
616 | printk(KERN_EMERG "exit_nr %d\n", exit_nr); | |
617 | BUG(); | |
618 | } | |
619 | ||
620 | local_irq_disable(); | |
621 | ||
7e28e60e | 622 | kvmppc_core_prepare_to_enter(vcpu); |
bbf45ba5 | 623 | |
bbf45ba5 HB |
624 | if (!(r & RESUME_HOST)) { |
625 | /* To avoid clobbering exit_reason, only check for signals if | |
626 | * we aren't already exiting to userspace for some other | |
627 | * reason. */ | |
628 | if (signal_pending(current)) { | |
629 | run->exit_reason = KVM_EXIT_INTR; | |
630 | r = (-EINTR << 2) | RESUME_HOST | (r & RESUME_FLAG_NV); | |
7b701591 | 631 | kvmppc_account_exit(vcpu, SIGNAL_EXITS); |
bbf45ba5 HB |
632 | } |
633 | } | |
634 | ||
635 | return r; | |
636 | } | |
637 | ||
638 | /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */ | |
639 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
640 | { | |
082decf2 | 641 | int i; |
af8f38b3 | 642 | int r; |
082decf2 | 643 | |
bbf45ba5 | 644 | vcpu->arch.pc = 0; |
666e7252 | 645 | vcpu->arch.shared->msr = 0; |
ecee273f | 646 | vcpu->arch.shadow_msr = MSR_USER | MSR_DE | MSR_IS | MSR_DS; |
b5904972 | 647 | vcpu->arch.shared->pir = vcpu->vcpu_id; |
8e5b26b5 | 648 | kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */ |
bbf45ba5 | 649 | |
49dd2c49 HB |
650 | vcpu->arch.shadow_pid = 1; |
651 | ||
082decf2 HB |
652 | /* Eye-catching numbers so we know if the guest takes an interrupt |
653 | * before it's programmed its own IVPR/IVORs. */ | |
bbf45ba5 | 654 | vcpu->arch.ivpr = 0x55550000; |
082decf2 HB |
655 | for (i = 0; i < BOOKE_IRQPRIO_MAX; i++) |
656 | vcpu->arch.ivor[i] = 0x7700 | i * 4; | |
bbf45ba5 | 657 | |
73e75b41 HB |
658 | kvmppc_init_timing_stats(vcpu); |
659 | ||
af8f38b3 AG |
660 | r = kvmppc_core_vcpu_setup(vcpu); |
661 | kvmppc_sanity_check(vcpu); | |
662 | return r; | |
bbf45ba5 HB |
663 | } |
664 | ||
665 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
666 | { | |
667 | int i; | |
668 | ||
669 | regs->pc = vcpu->arch.pc; | |
992b5b29 | 670 | regs->cr = kvmppc_get_cr(vcpu); |
bbf45ba5 HB |
671 | regs->ctr = vcpu->arch.ctr; |
672 | regs->lr = vcpu->arch.lr; | |
992b5b29 | 673 | regs->xer = kvmppc_get_xer(vcpu); |
666e7252 | 674 | regs->msr = vcpu->arch.shared->msr; |
de7906c3 AG |
675 | regs->srr0 = vcpu->arch.shared->srr0; |
676 | regs->srr1 = vcpu->arch.shared->srr1; | |
bbf45ba5 | 677 | regs->pid = vcpu->arch.pid; |
a73a9599 AG |
678 | regs->sprg0 = vcpu->arch.shared->sprg0; |
679 | regs->sprg1 = vcpu->arch.shared->sprg1; | |
680 | regs->sprg2 = vcpu->arch.shared->sprg2; | |
681 | regs->sprg3 = vcpu->arch.shared->sprg3; | |
b5904972 SW |
682 | regs->sprg4 = vcpu->arch.shared->sprg4; |
683 | regs->sprg5 = vcpu->arch.shared->sprg5; | |
684 | regs->sprg6 = vcpu->arch.shared->sprg6; | |
685 | regs->sprg7 = vcpu->arch.shared->sprg7; | |
bbf45ba5 HB |
686 | |
687 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) | |
8e5b26b5 | 688 | regs->gpr[i] = kvmppc_get_gpr(vcpu, i); |
bbf45ba5 HB |
689 | |
690 | return 0; | |
691 | } | |
692 | ||
693 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
694 | { | |
695 | int i; | |
696 | ||
697 | vcpu->arch.pc = regs->pc; | |
992b5b29 | 698 | kvmppc_set_cr(vcpu, regs->cr); |
bbf45ba5 HB |
699 | vcpu->arch.ctr = regs->ctr; |
700 | vcpu->arch.lr = regs->lr; | |
992b5b29 | 701 | kvmppc_set_xer(vcpu, regs->xer); |
b8fd68ac | 702 | kvmppc_set_msr(vcpu, regs->msr); |
de7906c3 AG |
703 | vcpu->arch.shared->srr0 = regs->srr0; |
704 | vcpu->arch.shared->srr1 = regs->srr1; | |
5ce941ee | 705 | kvmppc_set_pid(vcpu, regs->pid); |
a73a9599 AG |
706 | vcpu->arch.shared->sprg0 = regs->sprg0; |
707 | vcpu->arch.shared->sprg1 = regs->sprg1; | |
708 | vcpu->arch.shared->sprg2 = regs->sprg2; | |
709 | vcpu->arch.shared->sprg3 = regs->sprg3; | |
b5904972 SW |
710 | vcpu->arch.shared->sprg4 = regs->sprg4; |
711 | vcpu->arch.shared->sprg5 = regs->sprg5; | |
712 | vcpu->arch.shared->sprg6 = regs->sprg6; | |
713 | vcpu->arch.shared->sprg7 = regs->sprg7; | |
bbf45ba5 | 714 | |
8e5b26b5 AG |
715 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) |
716 | kvmppc_set_gpr(vcpu, i, regs->gpr[i]); | |
bbf45ba5 HB |
717 | |
718 | return 0; | |
719 | } | |
720 | ||
5ce941ee SW |
721 | static void get_sregs_base(struct kvm_vcpu *vcpu, |
722 | struct kvm_sregs *sregs) | |
723 | { | |
724 | u64 tb = get_tb(); | |
725 | ||
726 | sregs->u.e.features |= KVM_SREGS_E_BASE; | |
727 | ||
728 | sregs->u.e.csrr0 = vcpu->arch.csrr0; | |
729 | sregs->u.e.csrr1 = vcpu->arch.csrr1; | |
730 | sregs->u.e.mcsr = vcpu->arch.mcsr; | |
b5904972 | 731 | sregs->u.e.esr = vcpu->arch.shared->esr; |
5ce941ee SW |
732 | sregs->u.e.dear = vcpu->arch.shared->dar; |
733 | sregs->u.e.tsr = vcpu->arch.tsr; | |
734 | sregs->u.e.tcr = vcpu->arch.tcr; | |
735 | sregs->u.e.dec = kvmppc_get_dec(vcpu, tb); | |
736 | sregs->u.e.tb = tb; | |
737 | sregs->u.e.vrsave = vcpu->arch.vrsave; | |
738 | } | |
739 | ||
740 | static int set_sregs_base(struct kvm_vcpu *vcpu, | |
741 | struct kvm_sregs *sregs) | |
742 | { | |
743 | if (!(sregs->u.e.features & KVM_SREGS_E_BASE)) | |
744 | return 0; | |
745 | ||
746 | vcpu->arch.csrr0 = sregs->u.e.csrr0; | |
747 | vcpu->arch.csrr1 = sregs->u.e.csrr1; | |
748 | vcpu->arch.mcsr = sregs->u.e.mcsr; | |
b5904972 | 749 | vcpu->arch.shared->esr = sregs->u.e.esr; |
5ce941ee SW |
750 | vcpu->arch.shared->dar = sregs->u.e.dear; |
751 | vcpu->arch.vrsave = sregs->u.e.vrsave; | |
752 | vcpu->arch.tcr = sregs->u.e.tcr; | |
753 | ||
754 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) | |
755 | vcpu->arch.dec = sregs->u.e.dec; | |
756 | ||
757 | kvmppc_emulate_dec(vcpu); | |
758 | ||
759 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) { | |
760 | /* | |
761 | * FIXME: existing KVM timer handling is incomplete. | |
762 | * TSR cannot be read by the guest, and its value in | |
763 | * vcpu->arch is always zero. For now, just handle | |
764 | * the case where the caller is trying to inject a | |
765 | * decrementer interrupt. | |
766 | */ | |
767 | ||
768 | if ((sregs->u.e.tsr & TSR_DIS) && | |
769 | (vcpu->arch.tcr & TCR_DIE)) | |
770 | kvmppc_core_queue_dec(vcpu); | |
771 | } | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static void get_sregs_arch206(struct kvm_vcpu *vcpu, | |
777 | struct kvm_sregs *sregs) | |
778 | { | |
779 | sregs->u.e.features |= KVM_SREGS_E_ARCH206; | |
780 | ||
841741f2 | 781 | sregs->u.e.pir = vcpu->vcpu_id; |
5ce941ee SW |
782 | sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0; |
783 | sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1; | |
784 | sregs->u.e.decar = vcpu->arch.decar; | |
785 | sregs->u.e.ivpr = vcpu->arch.ivpr; | |
786 | } | |
787 | ||
788 | static int set_sregs_arch206(struct kvm_vcpu *vcpu, | |
789 | struct kvm_sregs *sregs) | |
790 | { | |
791 | if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206)) | |
792 | return 0; | |
793 | ||
841741f2 | 794 | if (sregs->u.e.pir != vcpu->vcpu_id) |
5ce941ee SW |
795 | return -EINVAL; |
796 | ||
797 | vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0; | |
798 | vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1; | |
799 | vcpu->arch.decar = sregs->u.e.decar; | |
800 | vcpu->arch.ivpr = sregs->u.e.ivpr; | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
806 | { | |
807 | sregs->u.e.features |= KVM_SREGS_E_IVOR; | |
808 | ||
809 | sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; | |
810 | sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; | |
811 | sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; | |
812 | sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; | |
813 | sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; | |
814 | sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; | |
815 | sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; | |
816 | sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; | |
817 | sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; | |
818 | sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; | |
819 | sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; | |
820 | sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; | |
821 | sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; | |
822 | sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; | |
823 | sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; | |
824 | sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; | |
825 | } | |
826 | ||
827 | int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
828 | { | |
829 | if (!(sregs->u.e.features & KVM_SREGS_E_IVOR)) | |
830 | return 0; | |
831 | ||
832 | vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0]; | |
833 | vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1]; | |
834 | vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2]; | |
835 | vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3]; | |
836 | vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4]; | |
837 | vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5]; | |
838 | vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6]; | |
839 | vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7]; | |
840 | vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8]; | |
841 | vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9]; | |
842 | vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10]; | |
843 | vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11]; | |
844 | vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12]; | |
845 | vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13]; | |
846 | vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14]; | |
847 | vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15]; | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
bbf45ba5 HB |
852 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
853 | struct kvm_sregs *sregs) | |
854 | { | |
5ce941ee SW |
855 | sregs->pvr = vcpu->arch.pvr; |
856 | ||
857 | get_sregs_base(vcpu, sregs); | |
858 | get_sregs_arch206(vcpu, sregs); | |
859 | kvmppc_core_get_sregs(vcpu, sregs); | |
860 | return 0; | |
bbf45ba5 HB |
861 | } |
862 | ||
863 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
864 | struct kvm_sregs *sregs) | |
865 | { | |
5ce941ee SW |
866 | int ret; |
867 | ||
868 | if (vcpu->arch.pvr != sregs->pvr) | |
869 | return -EINVAL; | |
870 | ||
871 | ret = set_sregs_base(vcpu, sregs); | |
872 | if (ret < 0) | |
873 | return ret; | |
874 | ||
875 | ret = set_sregs_arch206(vcpu, sregs); | |
876 | if (ret < 0) | |
877 | return ret; | |
878 | ||
879 | return kvmppc_core_set_sregs(vcpu, sregs); | |
bbf45ba5 HB |
880 | } |
881 | ||
882 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
883 | { | |
884 | return -ENOTSUPP; | |
885 | } | |
886 | ||
887 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
888 | { | |
889 | return -ENOTSUPP; | |
890 | } | |
891 | ||
bbf45ba5 HB |
892 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, |
893 | struct kvm_translation *tr) | |
894 | { | |
98001d8d AK |
895 | int r; |
896 | ||
98001d8d | 897 | r = kvmppc_core_vcpu_translate(vcpu, tr); |
98001d8d | 898 | return r; |
bbf45ba5 | 899 | } |
d9fbd03d | 900 | |
4e755758 AG |
901 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
902 | { | |
903 | return -ENOTSUPP; | |
904 | } | |
905 | ||
f9e0554d PM |
906 | int kvmppc_core_prepare_memory_region(struct kvm *kvm, |
907 | struct kvm_userspace_memory_region *mem) | |
908 | { | |
909 | return 0; | |
910 | } | |
911 | ||
912 | void kvmppc_core_commit_memory_region(struct kvm *kvm, | |
913 | struct kvm_userspace_memory_region *mem) | |
914 | { | |
915 | } | |
916 | ||
917 | int kvmppc_core_init_vm(struct kvm *kvm) | |
918 | { | |
919 | return 0; | |
920 | } | |
921 | ||
922 | void kvmppc_core_destroy_vm(struct kvm *kvm) | |
923 | { | |
924 | } | |
925 | ||
2986b8c7 | 926 | int __init kvmppc_booke_init(void) |
d9fbd03d HB |
927 | { |
928 | unsigned long ivor[16]; | |
929 | unsigned long max_ivor = 0; | |
930 | int i; | |
931 | ||
932 | /* We install our own exception handlers by hijacking IVPR. IVPR must | |
933 | * be 16-bit aligned, so we need a 64KB allocation. */ | |
934 | kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
935 | VCPU_SIZE_ORDER); | |
936 | if (!kvmppc_booke_handlers) | |
937 | return -ENOMEM; | |
938 | ||
939 | /* XXX make sure our handlers are smaller than Linux's */ | |
940 | ||
941 | /* Copy our interrupt handlers to match host IVORs. That way we don't | |
942 | * have to swap the IVORs on every guest/host transition. */ | |
943 | ivor[0] = mfspr(SPRN_IVOR0); | |
944 | ivor[1] = mfspr(SPRN_IVOR1); | |
945 | ivor[2] = mfspr(SPRN_IVOR2); | |
946 | ivor[3] = mfspr(SPRN_IVOR3); | |
947 | ivor[4] = mfspr(SPRN_IVOR4); | |
948 | ivor[5] = mfspr(SPRN_IVOR5); | |
949 | ivor[6] = mfspr(SPRN_IVOR6); | |
950 | ivor[7] = mfspr(SPRN_IVOR7); | |
951 | ivor[8] = mfspr(SPRN_IVOR8); | |
952 | ivor[9] = mfspr(SPRN_IVOR9); | |
953 | ivor[10] = mfspr(SPRN_IVOR10); | |
954 | ivor[11] = mfspr(SPRN_IVOR11); | |
955 | ivor[12] = mfspr(SPRN_IVOR12); | |
956 | ivor[13] = mfspr(SPRN_IVOR13); | |
957 | ivor[14] = mfspr(SPRN_IVOR14); | |
958 | ivor[15] = mfspr(SPRN_IVOR15); | |
959 | ||
960 | for (i = 0; i < 16; i++) { | |
961 | if (ivor[i] > max_ivor) | |
962 | max_ivor = ivor[i]; | |
963 | ||
964 | memcpy((void *)kvmppc_booke_handlers + ivor[i], | |
965 | kvmppc_handlers_start + i * kvmppc_handler_len, | |
966 | kvmppc_handler_len); | |
967 | } | |
968 | flush_icache_range(kvmppc_booke_handlers, | |
969 | kvmppc_booke_handlers + max_ivor + kvmppc_handler_len); | |
970 | ||
db93f574 | 971 | return 0; |
d9fbd03d HB |
972 | } |
973 | ||
db93f574 | 974 | void __exit kvmppc_booke_exit(void) |
d9fbd03d HB |
975 | { |
976 | free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER); | |
977 | kvm_exit(); | |
978 | } |