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bbf45ba5 HB |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright IBM Corp. 2007 | |
4cd35f67 | 16 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
bbf45ba5 HB |
17 | * |
18 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
19 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
20 | */ | |
21 | ||
22 | #include <linux/errno.h> | |
23 | #include <linux/err.h> | |
24 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 25 | #include <linux/gfp.h> |
bbf45ba5 HB |
26 | #include <linux/module.h> |
27 | #include <linux/vmalloc.h> | |
28 | #include <linux/fs.h> | |
7924bd41 | 29 | |
bbf45ba5 HB |
30 | #include <asm/cputable.h> |
31 | #include <asm/uaccess.h> | |
32 | #include <asm/kvm_ppc.h> | |
73e75b41 | 33 | #include "timing.h" |
d9fbd03d | 34 | #include <asm/cacheflush.h> |
bbf45ba5 | 35 | |
75f74f0d | 36 | #include "booke.h" |
bbf45ba5 | 37 | |
d9fbd03d HB |
38 | unsigned long kvmppc_booke_handlers; |
39 | ||
bbf45ba5 HB |
40 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
41 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
42 | ||
43 | struct kvm_stats_debugfs_item debugfs_entries[] = { | |
bbf45ba5 HB |
44 | { "mmio", VCPU_STAT(mmio_exits) }, |
45 | { "dcr", VCPU_STAT(dcr_exits) }, | |
46 | { "sig", VCPU_STAT(signal_exits) }, | |
bbf45ba5 HB |
47 | { "itlb_r", VCPU_STAT(itlb_real_miss_exits) }, |
48 | { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) }, | |
49 | { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) }, | |
50 | { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) }, | |
51 | { "sysc", VCPU_STAT(syscall_exits) }, | |
52 | { "isi", VCPU_STAT(isi_exits) }, | |
53 | { "dsi", VCPU_STAT(dsi_exits) }, | |
54 | { "inst_emu", VCPU_STAT(emulated_inst_exits) }, | |
55 | { "dec", VCPU_STAT(dec_exits) }, | |
56 | { "ext_intr", VCPU_STAT(ext_intr_exits) }, | |
45c5eb67 | 57 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
bbf45ba5 HB |
58 | { NULL } |
59 | }; | |
60 | ||
bbf45ba5 HB |
61 | /* TODO: use vcpu_printf() */ |
62 | void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu) | |
63 | { | |
64 | int i; | |
65 | ||
666e7252 | 66 | printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr); |
5cf8ca22 | 67 | printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr); |
de7906c3 AG |
68 | printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0, |
69 | vcpu->arch.shared->srr1); | |
bbf45ba5 HB |
70 | |
71 | printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions); | |
72 | ||
73 | for (i = 0; i < 32; i += 4) { | |
5cf8ca22 | 74 | printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i, |
8e5b26b5 AG |
75 | kvmppc_get_gpr(vcpu, i), |
76 | kvmppc_get_gpr(vcpu, i+1), | |
77 | kvmppc_get_gpr(vcpu, i+2), | |
78 | kvmppc_get_gpr(vcpu, i+3)); | |
bbf45ba5 HB |
79 | } |
80 | } | |
81 | ||
4cd35f67 SW |
82 | #ifdef CONFIG_SPE |
83 | void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu) | |
84 | { | |
85 | preempt_disable(); | |
86 | enable_kernel_spe(); | |
87 | kvmppc_save_guest_spe(vcpu); | |
88 | vcpu->arch.shadow_msr &= ~MSR_SPE; | |
89 | preempt_enable(); | |
90 | } | |
91 | ||
92 | static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu) | |
93 | { | |
94 | preempt_disable(); | |
95 | enable_kernel_spe(); | |
96 | kvmppc_load_guest_spe(vcpu); | |
97 | vcpu->arch.shadow_msr |= MSR_SPE; | |
98 | preempt_enable(); | |
99 | } | |
100 | ||
101 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
102 | { | |
103 | if (vcpu->arch.shared->msr & MSR_SPE) { | |
104 | if (!(vcpu->arch.shadow_msr & MSR_SPE)) | |
105 | kvmppc_vcpu_enable_spe(vcpu); | |
106 | } else if (vcpu->arch.shadow_msr & MSR_SPE) { | |
107 | kvmppc_vcpu_disable_spe(vcpu); | |
108 | } | |
109 | } | |
110 | #else | |
111 | static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu) | |
112 | { | |
113 | } | |
114 | #endif | |
115 | ||
116 | /* Helper function for "full" MSR writes. No need to call this if only EE is | |
117 | * changing. */ | |
118 | void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr) | |
119 | { | |
120 | if ((new_msr & MSR_PR) != (vcpu->arch.shared->msr & MSR_PR)) | |
121 | kvmppc_mmu_priv_switch(vcpu, new_msr & MSR_PR); | |
122 | ||
123 | vcpu->arch.shared->msr = new_msr; | |
124 | ||
125 | if (vcpu->arch.shared->msr & MSR_WE) { | |
126 | kvm_vcpu_block(vcpu); | |
127 | kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS); | |
128 | }; | |
129 | ||
130 | kvmppc_vcpu_sync_spe(vcpu); | |
131 | } | |
132 | ||
d4cf3892 HB |
133 | static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu, |
134 | unsigned int priority) | |
9dd921cf | 135 | { |
9dd921cf HB |
136 | set_bit(priority, &vcpu->arch.pending_exceptions); |
137 | } | |
138 | ||
daf5e271 LY |
139 | static void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, |
140 | ulong dear_flags, ulong esr_flags) | |
9dd921cf | 141 | { |
daf5e271 LY |
142 | vcpu->arch.queued_dear = dear_flags; |
143 | vcpu->arch.queued_esr = esr_flags; | |
144 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS); | |
145 | } | |
146 | ||
147 | static void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, | |
148 | ulong dear_flags, ulong esr_flags) | |
149 | { | |
150 | vcpu->arch.queued_dear = dear_flags; | |
151 | vcpu->arch.queued_esr = esr_flags; | |
152 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE); | |
153 | } | |
154 | ||
155 | static void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, | |
156 | ulong esr_flags) | |
157 | { | |
158 | vcpu->arch.queued_esr = esr_flags; | |
159 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE); | |
160 | } | |
161 | ||
162 | void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags) | |
163 | { | |
164 | vcpu->arch.queued_esr = esr_flags; | |
d4cf3892 | 165 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM); |
9dd921cf HB |
166 | } |
167 | ||
168 | void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu) | |
169 | { | |
d4cf3892 | 170 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER); |
9dd921cf HB |
171 | } |
172 | ||
173 | int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu) | |
174 | { | |
d4cf3892 | 175 | return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); |
9dd921cf HB |
176 | } |
177 | ||
7706664d AG |
178 | void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu) |
179 | { | |
180 | clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions); | |
181 | } | |
182 | ||
9dd921cf HB |
183 | void kvmppc_core_queue_external(struct kvm_vcpu *vcpu, |
184 | struct kvm_interrupt *irq) | |
185 | { | |
c5335f17 AG |
186 | unsigned int prio = BOOKE_IRQPRIO_EXTERNAL; |
187 | ||
188 | if (irq->irq == KVM_INTERRUPT_SET_LEVEL) | |
189 | prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL; | |
190 | ||
191 | kvmppc_booke_queue_irqprio(vcpu, prio); | |
9dd921cf HB |
192 | } |
193 | ||
4496f974 AG |
194 | void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu, |
195 | struct kvm_interrupt *irq) | |
196 | { | |
197 | clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions); | |
c5335f17 | 198 | clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions); |
4496f974 AG |
199 | } |
200 | ||
d4cf3892 HB |
201 | /* Deliver the interrupt of the corresponding priority, if possible. */ |
202 | static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu, | |
203 | unsigned int priority) | |
bbf45ba5 | 204 | { |
d4cf3892 | 205 | int allowed = 0; |
6045be5d | 206 | ulong uninitialized_var(msr_mask); |
daf5e271 | 207 | bool update_esr = false, update_dear = false; |
5c6cedf4 AG |
208 | ulong crit_raw = vcpu->arch.shared->critical; |
209 | ulong crit_r1 = kvmppc_get_gpr(vcpu, 1); | |
210 | bool crit; | |
c5335f17 | 211 | bool keep_irq = false; |
5c6cedf4 AG |
212 | |
213 | /* Truncate crit indicators in 32 bit mode */ | |
214 | if (!(vcpu->arch.shared->msr & MSR_SF)) { | |
215 | crit_raw &= 0xffffffff; | |
216 | crit_r1 &= 0xffffffff; | |
217 | } | |
218 | ||
219 | /* Critical section when crit == r1 */ | |
220 | crit = (crit_raw == crit_r1); | |
221 | /* ... and we're in supervisor mode */ | |
222 | crit = crit && !(vcpu->arch.shared->msr & MSR_PR); | |
d4cf3892 | 223 | |
c5335f17 AG |
224 | if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) { |
225 | priority = BOOKE_IRQPRIO_EXTERNAL; | |
226 | keep_irq = true; | |
227 | } | |
228 | ||
d4cf3892 | 229 | switch (priority) { |
d4cf3892 | 230 | case BOOKE_IRQPRIO_DTLB_MISS: |
d4cf3892 | 231 | case BOOKE_IRQPRIO_DATA_STORAGE: |
daf5e271 LY |
232 | update_dear = true; |
233 | /* fall through */ | |
d4cf3892 | 234 | case BOOKE_IRQPRIO_INST_STORAGE: |
daf5e271 LY |
235 | case BOOKE_IRQPRIO_PROGRAM: |
236 | update_esr = true; | |
237 | /* fall through */ | |
238 | case BOOKE_IRQPRIO_ITLB_MISS: | |
239 | case BOOKE_IRQPRIO_SYSCALL: | |
d4cf3892 | 240 | case BOOKE_IRQPRIO_FP_UNAVAIL: |
bb3a8a17 HB |
241 | case BOOKE_IRQPRIO_SPE_UNAVAIL: |
242 | case BOOKE_IRQPRIO_SPE_FP_DATA: | |
243 | case BOOKE_IRQPRIO_SPE_FP_ROUND: | |
d4cf3892 HB |
244 | case BOOKE_IRQPRIO_AP_UNAVAIL: |
245 | case BOOKE_IRQPRIO_ALIGNMENT: | |
246 | allowed = 1; | |
247 | msr_mask = MSR_CE|MSR_ME|MSR_DE; | |
bbf45ba5 | 248 | break; |
d4cf3892 HB |
249 | case BOOKE_IRQPRIO_CRITICAL: |
250 | case BOOKE_IRQPRIO_WATCHDOG: | |
666e7252 | 251 | allowed = vcpu->arch.shared->msr & MSR_CE; |
d4cf3892 | 252 | msr_mask = MSR_ME; |
bbf45ba5 | 253 | break; |
d4cf3892 | 254 | case BOOKE_IRQPRIO_MACHINE_CHECK: |
666e7252 | 255 | allowed = vcpu->arch.shared->msr & MSR_ME; |
d4cf3892 | 256 | msr_mask = 0; |
bbf45ba5 | 257 | break; |
d4cf3892 HB |
258 | case BOOKE_IRQPRIO_EXTERNAL: |
259 | case BOOKE_IRQPRIO_DECREMENTER: | |
260 | case BOOKE_IRQPRIO_FIT: | |
666e7252 | 261 | allowed = vcpu->arch.shared->msr & MSR_EE; |
5c6cedf4 | 262 | allowed = allowed && !crit; |
d4cf3892 | 263 | msr_mask = MSR_CE|MSR_ME|MSR_DE; |
bbf45ba5 | 264 | break; |
d4cf3892 | 265 | case BOOKE_IRQPRIO_DEBUG: |
666e7252 | 266 | allowed = vcpu->arch.shared->msr & MSR_DE; |
d4cf3892 | 267 | msr_mask = MSR_ME; |
bbf45ba5 | 268 | break; |
bbf45ba5 HB |
269 | } |
270 | ||
d4cf3892 | 271 | if (allowed) { |
de7906c3 AG |
272 | vcpu->arch.shared->srr0 = vcpu->arch.pc; |
273 | vcpu->arch.shared->srr1 = vcpu->arch.shared->msr; | |
d4cf3892 | 274 | vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority]; |
daf5e271 LY |
275 | if (update_esr == true) |
276 | vcpu->arch.esr = vcpu->arch.queued_esr; | |
277 | if (update_dear == true) | |
5e030186 | 278 | vcpu->arch.shared->dar = vcpu->arch.queued_dear; |
666e7252 | 279 | kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask); |
bbf45ba5 | 280 | |
c5335f17 AG |
281 | if (!keep_irq) |
282 | clear_bit(priority, &vcpu->arch.pending_exceptions); | |
bbf45ba5 HB |
283 | } |
284 | ||
d4cf3892 | 285 | return allowed; |
bbf45ba5 HB |
286 | } |
287 | ||
288 | /* Check pending exceptions and deliver one, if possible. */ | |
9dd921cf | 289 | void kvmppc_core_deliver_interrupts(struct kvm_vcpu *vcpu) |
bbf45ba5 HB |
290 | { |
291 | unsigned long *pending = &vcpu->arch.pending_exceptions; | |
90bba358 | 292 | unsigned long old_pending = vcpu->arch.pending_exceptions; |
bbf45ba5 HB |
293 | unsigned int priority; |
294 | ||
9ab80843 | 295 | priority = __ffs(*pending); |
bdc89f13 | 296 | while (priority <= BOOKE_IRQPRIO_MAX) { |
d4cf3892 | 297 | if (kvmppc_booke_irqprio_deliver(vcpu, priority)) |
bbf45ba5 | 298 | break; |
bbf45ba5 HB |
299 | |
300 | priority = find_next_bit(pending, | |
301 | BITS_PER_BYTE * sizeof(*pending), | |
302 | priority + 1); | |
303 | } | |
90bba358 AG |
304 | |
305 | /* Tell the guest about our interrupt status */ | |
306 | if (*pending) | |
307 | vcpu->arch.shared->int_pending = 1; | |
308 | else if (old_pending) | |
309 | vcpu->arch.shared->int_pending = 0; | |
bbf45ba5 HB |
310 | } |
311 | ||
bbf45ba5 HB |
312 | /** |
313 | * kvmppc_handle_exit | |
314 | * | |
315 | * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) | |
316 | */ | |
317 | int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu, | |
318 | unsigned int exit_nr) | |
319 | { | |
320 | enum emulation_result er; | |
321 | int r = RESUME_HOST; | |
322 | ||
73e75b41 HB |
323 | /* update before a new last_exit_type is rewritten */ |
324 | kvmppc_update_timing_stats(vcpu); | |
325 | ||
bbf45ba5 HB |
326 | local_irq_enable(); |
327 | ||
328 | run->exit_reason = KVM_EXIT_UNKNOWN; | |
329 | run->ready_for_interrupt_injection = 1; | |
330 | ||
331 | switch (exit_nr) { | |
332 | case BOOKE_INTERRUPT_MACHINE_CHECK: | |
333 | printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR)); | |
334 | kvmppc_dump_vcpu(vcpu); | |
335 | r = RESUME_HOST; | |
336 | break; | |
337 | ||
338 | case BOOKE_INTERRUPT_EXTERNAL: | |
7b701591 | 339 | kvmppc_account_exit(vcpu, EXT_INTR_EXITS); |
1b6766c7 HB |
340 | if (need_resched()) |
341 | cond_resched(); | |
342 | r = RESUME_GUEST; | |
343 | break; | |
344 | ||
bbf45ba5 HB |
345 | case BOOKE_INTERRUPT_DECREMENTER: |
346 | /* Since we switched IVPR back to the host's value, the host | |
347 | * handled this interrupt the moment we enabled interrupts. | |
348 | * Now we just offer it a chance to reschedule the guest. */ | |
7b701591 | 349 | kvmppc_account_exit(vcpu, DEC_EXITS); |
bbf45ba5 HB |
350 | if (need_resched()) |
351 | cond_resched(); | |
bbf45ba5 HB |
352 | r = RESUME_GUEST; |
353 | break; | |
354 | ||
355 | case BOOKE_INTERRUPT_PROGRAM: | |
666e7252 | 356 | if (vcpu->arch.shared->msr & MSR_PR) { |
bbf45ba5 HB |
357 | /* Program traps generated by user-level software must be handled |
358 | * by the guest kernel. */ | |
daf5e271 | 359 | kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr); |
bbf45ba5 | 360 | r = RESUME_GUEST; |
7b701591 | 361 | kvmppc_account_exit(vcpu, USR_PR_INST); |
bbf45ba5 HB |
362 | break; |
363 | } | |
364 | ||
365 | er = kvmppc_emulate_instruction(run, vcpu); | |
366 | switch (er) { | |
367 | case EMULATE_DONE: | |
73e75b41 | 368 | /* don't overwrite subtypes, just account kvm_stats */ |
7b701591 | 369 | kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS); |
bbf45ba5 HB |
370 | /* Future optimization: only reload non-volatiles if |
371 | * they were actually modified by emulation. */ | |
bbf45ba5 HB |
372 | r = RESUME_GUEST_NV; |
373 | break; | |
374 | case EMULATE_DO_DCR: | |
375 | run->exit_reason = KVM_EXIT_DCR; | |
376 | r = RESUME_HOST; | |
377 | break; | |
378 | case EMULATE_FAIL: | |
379 | /* XXX Deliver Program interrupt to guest. */ | |
5cf8ca22 | 380 | printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n", |
bbf45ba5 HB |
381 | __func__, vcpu->arch.pc, vcpu->arch.last_inst); |
382 | /* For debugging, encode the failing instruction and | |
383 | * report it to userspace. */ | |
384 | run->hw.hardware_exit_reason = ~0ULL << 32; | |
385 | run->hw.hardware_exit_reason |= vcpu->arch.last_inst; | |
386 | r = RESUME_HOST; | |
387 | break; | |
388 | default: | |
389 | BUG(); | |
390 | } | |
391 | break; | |
392 | ||
de368dce | 393 | case BOOKE_INTERRUPT_FP_UNAVAIL: |
d4cf3892 | 394 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL); |
7b701591 | 395 | kvmppc_account_exit(vcpu, FP_UNAVAIL); |
de368dce CE |
396 | r = RESUME_GUEST; |
397 | break; | |
398 | ||
4cd35f67 SW |
399 | #ifdef CONFIG_SPE |
400 | case BOOKE_INTERRUPT_SPE_UNAVAIL: { | |
401 | if (vcpu->arch.shared->msr & MSR_SPE) | |
402 | kvmppc_vcpu_enable_spe(vcpu); | |
403 | else | |
404 | kvmppc_booke_queue_irqprio(vcpu, | |
405 | BOOKE_IRQPRIO_SPE_UNAVAIL); | |
bb3a8a17 HB |
406 | r = RESUME_GUEST; |
407 | break; | |
4cd35f67 | 408 | } |
bb3a8a17 HB |
409 | |
410 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
411 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA); | |
412 | r = RESUME_GUEST; | |
413 | break; | |
414 | ||
415 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
416 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND); | |
417 | r = RESUME_GUEST; | |
418 | break; | |
4cd35f67 SW |
419 | #else |
420 | case BOOKE_INTERRUPT_SPE_UNAVAIL: | |
421 | /* | |
422 | * Guest wants SPE, but host kernel doesn't support it. Send | |
423 | * an "unimplemented operation" program check to the guest. | |
424 | */ | |
425 | kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV); | |
426 | r = RESUME_GUEST; | |
427 | break; | |
428 | ||
429 | /* | |
430 | * These really should never happen without CONFIG_SPE, | |
431 | * as we should never enable the real MSR[SPE] in the guest. | |
432 | */ | |
433 | case BOOKE_INTERRUPT_SPE_FP_DATA: | |
434 | case BOOKE_INTERRUPT_SPE_FP_ROUND: | |
435 | printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n", | |
436 | __func__, exit_nr, vcpu->arch.pc); | |
437 | run->hw.hardware_exit_reason = exit_nr; | |
438 | r = RESUME_HOST; | |
439 | break; | |
440 | #endif | |
bb3a8a17 | 441 | |
bbf45ba5 | 442 | case BOOKE_INTERRUPT_DATA_STORAGE: |
daf5e271 LY |
443 | kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear, |
444 | vcpu->arch.fault_esr); | |
7b701591 | 445 | kvmppc_account_exit(vcpu, DSI_EXITS); |
bbf45ba5 HB |
446 | r = RESUME_GUEST; |
447 | break; | |
448 | ||
449 | case BOOKE_INTERRUPT_INST_STORAGE: | |
daf5e271 | 450 | kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr); |
7b701591 | 451 | kvmppc_account_exit(vcpu, ISI_EXITS); |
bbf45ba5 HB |
452 | r = RESUME_GUEST; |
453 | break; | |
454 | ||
455 | case BOOKE_INTERRUPT_SYSCALL: | |
2a342ed5 AG |
456 | if (!(vcpu->arch.shared->msr & MSR_PR) && |
457 | (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { | |
458 | /* KVM PV hypercalls */ | |
459 | kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu)); | |
460 | r = RESUME_GUEST; | |
461 | } else { | |
462 | /* Guest syscalls */ | |
463 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL); | |
464 | } | |
7b701591 | 465 | kvmppc_account_exit(vcpu, SYSCALL_EXITS); |
bbf45ba5 HB |
466 | r = RESUME_GUEST; |
467 | break; | |
468 | ||
469 | case BOOKE_INTERRUPT_DTLB_MISS: { | |
bbf45ba5 | 470 | unsigned long eaddr = vcpu->arch.fault_dear; |
7924bd41 | 471 | int gtlb_index; |
475e7cdd | 472 | gpa_t gpaddr; |
bbf45ba5 HB |
473 | gfn_t gfn; |
474 | ||
a4cd8b23 SW |
475 | #ifdef CONFIG_KVM_E500 |
476 | if (!(vcpu->arch.shared->msr & MSR_PR) && | |
477 | (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) { | |
478 | kvmppc_map_magic(vcpu); | |
479 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); | |
480 | r = RESUME_GUEST; | |
481 | ||
482 | break; | |
483 | } | |
484 | #endif | |
485 | ||
bbf45ba5 | 486 | /* Check the guest TLB. */ |
fa86b8dd | 487 | gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr); |
7924bd41 | 488 | if (gtlb_index < 0) { |
bbf45ba5 | 489 | /* The guest didn't have a mapping for it. */ |
daf5e271 LY |
490 | kvmppc_core_queue_dtlb_miss(vcpu, |
491 | vcpu->arch.fault_dear, | |
492 | vcpu->arch.fault_esr); | |
b52a638c | 493 | kvmppc_mmu_dtlb_miss(vcpu); |
7b701591 | 494 | kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
495 | r = RESUME_GUEST; |
496 | break; | |
497 | } | |
498 | ||
be8d1cae | 499 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
475e7cdd | 500 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
501 | |
502 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
503 | /* The guest TLB had a mapping, but the shadow TLB | |
504 | * didn't, and it is RAM. This could be because: | |
505 | * a) the entry is mapping the host kernel, or | |
506 | * b) the guest used a large mapping which we're faking | |
507 | * Either way, we need to satisfy the fault without | |
508 | * invoking the guest. */ | |
58a96214 | 509 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
7b701591 | 510 | kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS); |
bbf45ba5 HB |
511 | r = RESUME_GUEST; |
512 | } else { | |
513 | /* Guest has mapped and accessed a page which is not | |
514 | * actually RAM. */ | |
475e7cdd | 515 | vcpu->arch.paddr_accessed = gpaddr; |
bbf45ba5 | 516 | r = kvmppc_emulate_mmio(run, vcpu); |
7b701591 | 517 | kvmppc_account_exit(vcpu, MMIO_EXITS); |
bbf45ba5 HB |
518 | } |
519 | ||
520 | break; | |
521 | } | |
522 | ||
523 | case BOOKE_INTERRUPT_ITLB_MISS: { | |
bbf45ba5 | 524 | unsigned long eaddr = vcpu->arch.pc; |
89168618 | 525 | gpa_t gpaddr; |
bbf45ba5 | 526 | gfn_t gfn; |
7924bd41 | 527 | int gtlb_index; |
bbf45ba5 HB |
528 | |
529 | r = RESUME_GUEST; | |
530 | ||
531 | /* Check the guest TLB. */ | |
fa86b8dd | 532 | gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr); |
7924bd41 | 533 | if (gtlb_index < 0) { |
bbf45ba5 | 534 | /* The guest didn't have a mapping for it. */ |
d4cf3892 | 535 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS); |
b52a638c | 536 | kvmppc_mmu_itlb_miss(vcpu); |
7b701591 | 537 | kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS); |
bbf45ba5 HB |
538 | break; |
539 | } | |
540 | ||
7b701591 | 541 | kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); |
bbf45ba5 | 542 | |
be8d1cae | 543 | gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); |
89168618 | 544 | gfn = gpaddr >> PAGE_SHIFT; |
bbf45ba5 HB |
545 | |
546 | if (kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
547 | /* The guest TLB had a mapping, but the shadow TLB | |
548 | * didn't. This could be because: | |
549 | * a) the entry is mapping the host kernel, or | |
550 | * b) the guest used a large mapping which we're faking | |
551 | * Either way, we need to satisfy the fault without | |
552 | * invoking the guest. */ | |
58a96214 | 553 | kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); |
bbf45ba5 HB |
554 | } else { |
555 | /* Guest mapped and leaped at non-RAM! */ | |
d4cf3892 | 556 | kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); |
bbf45ba5 HB |
557 | } |
558 | ||
559 | break; | |
560 | } | |
561 | ||
6a0ab738 HB |
562 | case BOOKE_INTERRUPT_DEBUG: { |
563 | u32 dbsr; | |
564 | ||
565 | vcpu->arch.pc = mfspr(SPRN_CSRR0); | |
566 | ||
567 | /* clear IAC events in DBSR register */ | |
568 | dbsr = mfspr(SPRN_DBSR); | |
569 | dbsr &= DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4; | |
570 | mtspr(SPRN_DBSR, dbsr); | |
571 | ||
572 | run->exit_reason = KVM_EXIT_DEBUG; | |
7b701591 | 573 | kvmppc_account_exit(vcpu, DEBUG_EXITS); |
6a0ab738 HB |
574 | r = RESUME_HOST; |
575 | break; | |
576 | } | |
577 | ||
bbf45ba5 HB |
578 | default: |
579 | printk(KERN_EMERG "exit_nr %d\n", exit_nr); | |
580 | BUG(); | |
581 | } | |
582 | ||
583 | local_irq_disable(); | |
584 | ||
9dd921cf | 585 | kvmppc_core_deliver_interrupts(vcpu); |
bbf45ba5 | 586 | |
bbf45ba5 HB |
587 | if (!(r & RESUME_HOST)) { |
588 | /* To avoid clobbering exit_reason, only check for signals if | |
589 | * we aren't already exiting to userspace for some other | |
590 | * reason. */ | |
591 | if (signal_pending(current)) { | |
592 | run->exit_reason = KVM_EXIT_INTR; | |
593 | r = (-EINTR << 2) | RESUME_HOST | (r & RESUME_FLAG_NV); | |
7b701591 | 594 | kvmppc_account_exit(vcpu, SIGNAL_EXITS); |
bbf45ba5 HB |
595 | } |
596 | } | |
597 | ||
598 | return r; | |
599 | } | |
600 | ||
601 | /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */ | |
602 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
603 | { | |
082decf2 HB |
604 | int i; |
605 | ||
bbf45ba5 | 606 | vcpu->arch.pc = 0; |
666e7252 | 607 | vcpu->arch.shared->msr = 0; |
ecee273f | 608 | vcpu->arch.shadow_msr = MSR_USER | MSR_DE | MSR_IS | MSR_DS; |
8e5b26b5 | 609 | kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */ |
bbf45ba5 | 610 | |
49dd2c49 HB |
611 | vcpu->arch.shadow_pid = 1; |
612 | ||
082decf2 HB |
613 | /* Eye-catching numbers so we know if the guest takes an interrupt |
614 | * before it's programmed its own IVPR/IVORs. */ | |
bbf45ba5 | 615 | vcpu->arch.ivpr = 0x55550000; |
082decf2 HB |
616 | for (i = 0; i < BOOKE_IRQPRIO_MAX; i++) |
617 | vcpu->arch.ivor[i] = 0x7700 | i * 4; | |
bbf45ba5 | 618 | |
73e75b41 HB |
619 | kvmppc_init_timing_stats(vcpu); |
620 | ||
5cbb5106 | 621 | return kvmppc_core_vcpu_setup(vcpu); |
bbf45ba5 HB |
622 | } |
623 | ||
624 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
625 | { | |
626 | int i; | |
627 | ||
628 | regs->pc = vcpu->arch.pc; | |
992b5b29 | 629 | regs->cr = kvmppc_get_cr(vcpu); |
bbf45ba5 HB |
630 | regs->ctr = vcpu->arch.ctr; |
631 | regs->lr = vcpu->arch.lr; | |
992b5b29 | 632 | regs->xer = kvmppc_get_xer(vcpu); |
666e7252 | 633 | regs->msr = vcpu->arch.shared->msr; |
de7906c3 AG |
634 | regs->srr0 = vcpu->arch.shared->srr0; |
635 | regs->srr1 = vcpu->arch.shared->srr1; | |
bbf45ba5 | 636 | regs->pid = vcpu->arch.pid; |
a73a9599 AG |
637 | regs->sprg0 = vcpu->arch.shared->sprg0; |
638 | regs->sprg1 = vcpu->arch.shared->sprg1; | |
639 | regs->sprg2 = vcpu->arch.shared->sprg2; | |
640 | regs->sprg3 = vcpu->arch.shared->sprg3; | |
bc9c1933 PT |
641 | regs->sprg4 = vcpu->arch.sprg4; |
642 | regs->sprg5 = vcpu->arch.sprg5; | |
643 | regs->sprg6 = vcpu->arch.sprg6; | |
644 | regs->sprg7 = vcpu->arch.sprg7; | |
bbf45ba5 HB |
645 | |
646 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) | |
8e5b26b5 | 647 | regs->gpr[i] = kvmppc_get_gpr(vcpu, i); |
bbf45ba5 HB |
648 | |
649 | return 0; | |
650 | } | |
651 | ||
652 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
653 | { | |
654 | int i; | |
655 | ||
656 | vcpu->arch.pc = regs->pc; | |
992b5b29 | 657 | kvmppc_set_cr(vcpu, regs->cr); |
bbf45ba5 HB |
658 | vcpu->arch.ctr = regs->ctr; |
659 | vcpu->arch.lr = regs->lr; | |
992b5b29 | 660 | kvmppc_set_xer(vcpu, regs->xer); |
b8fd68ac | 661 | kvmppc_set_msr(vcpu, regs->msr); |
de7906c3 AG |
662 | vcpu->arch.shared->srr0 = regs->srr0; |
663 | vcpu->arch.shared->srr1 = regs->srr1; | |
5ce941ee | 664 | kvmppc_set_pid(vcpu, regs->pid); |
a73a9599 AG |
665 | vcpu->arch.shared->sprg0 = regs->sprg0; |
666 | vcpu->arch.shared->sprg1 = regs->sprg1; | |
667 | vcpu->arch.shared->sprg2 = regs->sprg2; | |
668 | vcpu->arch.shared->sprg3 = regs->sprg3; | |
bc9c1933 PT |
669 | vcpu->arch.sprg4 = regs->sprg4; |
670 | vcpu->arch.sprg5 = regs->sprg5; | |
671 | vcpu->arch.sprg6 = regs->sprg6; | |
672 | vcpu->arch.sprg7 = regs->sprg7; | |
bbf45ba5 | 673 | |
8e5b26b5 AG |
674 | for (i = 0; i < ARRAY_SIZE(regs->gpr); i++) |
675 | kvmppc_set_gpr(vcpu, i, regs->gpr[i]); | |
bbf45ba5 HB |
676 | |
677 | return 0; | |
678 | } | |
679 | ||
5ce941ee SW |
680 | static void get_sregs_base(struct kvm_vcpu *vcpu, |
681 | struct kvm_sregs *sregs) | |
682 | { | |
683 | u64 tb = get_tb(); | |
684 | ||
685 | sregs->u.e.features |= KVM_SREGS_E_BASE; | |
686 | ||
687 | sregs->u.e.csrr0 = vcpu->arch.csrr0; | |
688 | sregs->u.e.csrr1 = vcpu->arch.csrr1; | |
689 | sregs->u.e.mcsr = vcpu->arch.mcsr; | |
690 | sregs->u.e.esr = vcpu->arch.esr; | |
691 | sregs->u.e.dear = vcpu->arch.shared->dar; | |
692 | sregs->u.e.tsr = vcpu->arch.tsr; | |
693 | sregs->u.e.tcr = vcpu->arch.tcr; | |
694 | sregs->u.e.dec = kvmppc_get_dec(vcpu, tb); | |
695 | sregs->u.e.tb = tb; | |
696 | sregs->u.e.vrsave = vcpu->arch.vrsave; | |
697 | } | |
698 | ||
699 | static int set_sregs_base(struct kvm_vcpu *vcpu, | |
700 | struct kvm_sregs *sregs) | |
701 | { | |
702 | if (!(sregs->u.e.features & KVM_SREGS_E_BASE)) | |
703 | return 0; | |
704 | ||
705 | vcpu->arch.csrr0 = sregs->u.e.csrr0; | |
706 | vcpu->arch.csrr1 = sregs->u.e.csrr1; | |
707 | vcpu->arch.mcsr = sregs->u.e.mcsr; | |
708 | vcpu->arch.esr = sregs->u.e.esr; | |
709 | vcpu->arch.shared->dar = sregs->u.e.dear; | |
710 | vcpu->arch.vrsave = sregs->u.e.vrsave; | |
711 | vcpu->arch.tcr = sregs->u.e.tcr; | |
712 | ||
713 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) | |
714 | vcpu->arch.dec = sregs->u.e.dec; | |
715 | ||
716 | kvmppc_emulate_dec(vcpu); | |
717 | ||
718 | if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) { | |
719 | /* | |
720 | * FIXME: existing KVM timer handling is incomplete. | |
721 | * TSR cannot be read by the guest, and its value in | |
722 | * vcpu->arch is always zero. For now, just handle | |
723 | * the case where the caller is trying to inject a | |
724 | * decrementer interrupt. | |
725 | */ | |
726 | ||
727 | if ((sregs->u.e.tsr & TSR_DIS) && | |
728 | (vcpu->arch.tcr & TCR_DIE)) | |
729 | kvmppc_core_queue_dec(vcpu); | |
730 | } | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
735 | static void get_sregs_arch206(struct kvm_vcpu *vcpu, | |
736 | struct kvm_sregs *sregs) | |
737 | { | |
738 | sregs->u.e.features |= KVM_SREGS_E_ARCH206; | |
739 | ||
740 | sregs->u.e.pir = 0; | |
741 | sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0; | |
742 | sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1; | |
743 | sregs->u.e.decar = vcpu->arch.decar; | |
744 | sregs->u.e.ivpr = vcpu->arch.ivpr; | |
745 | } | |
746 | ||
747 | static int set_sregs_arch206(struct kvm_vcpu *vcpu, | |
748 | struct kvm_sregs *sregs) | |
749 | { | |
750 | if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206)) | |
751 | return 0; | |
752 | ||
753 | if (sregs->u.e.pir != 0) | |
754 | return -EINVAL; | |
755 | ||
756 | vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0; | |
757 | vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1; | |
758 | vcpu->arch.decar = sregs->u.e.decar; | |
759 | vcpu->arch.ivpr = sregs->u.e.ivpr; | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
765 | { | |
766 | sregs->u.e.features |= KVM_SREGS_E_IVOR; | |
767 | ||
768 | sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL]; | |
769 | sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK]; | |
770 | sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE]; | |
771 | sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE]; | |
772 | sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL]; | |
773 | sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT]; | |
774 | sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM]; | |
775 | sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL]; | |
776 | sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL]; | |
777 | sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL]; | |
778 | sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER]; | |
779 | sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT]; | |
780 | sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG]; | |
781 | sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS]; | |
782 | sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS]; | |
783 | sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG]; | |
784 | } | |
785 | ||
786 | int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
787 | { | |
788 | if (!(sregs->u.e.features & KVM_SREGS_E_IVOR)) | |
789 | return 0; | |
790 | ||
791 | vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0]; | |
792 | vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1]; | |
793 | vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2]; | |
794 | vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3]; | |
795 | vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4]; | |
796 | vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5]; | |
797 | vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6]; | |
798 | vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7]; | |
799 | vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8]; | |
800 | vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9]; | |
801 | vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10]; | |
802 | vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11]; | |
803 | vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12]; | |
804 | vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13]; | |
805 | vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14]; | |
806 | vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15]; | |
807 | ||
808 | return 0; | |
809 | } | |
810 | ||
bbf45ba5 HB |
811 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
812 | struct kvm_sregs *sregs) | |
813 | { | |
5ce941ee SW |
814 | sregs->pvr = vcpu->arch.pvr; |
815 | ||
816 | get_sregs_base(vcpu, sregs); | |
817 | get_sregs_arch206(vcpu, sregs); | |
818 | kvmppc_core_get_sregs(vcpu, sregs); | |
819 | return 0; | |
bbf45ba5 HB |
820 | } |
821 | ||
822 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
823 | struct kvm_sregs *sregs) | |
824 | { | |
5ce941ee SW |
825 | int ret; |
826 | ||
827 | if (vcpu->arch.pvr != sregs->pvr) | |
828 | return -EINVAL; | |
829 | ||
830 | ret = set_sregs_base(vcpu, sregs); | |
831 | if (ret < 0) | |
832 | return ret; | |
833 | ||
834 | ret = set_sregs_arch206(vcpu, sregs); | |
835 | if (ret < 0) | |
836 | return ret; | |
837 | ||
838 | return kvmppc_core_set_sregs(vcpu, sregs); | |
bbf45ba5 HB |
839 | } |
840 | ||
841 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
842 | { | |
843 | return -ENOTSUPP; | |
844 | } | |
845 | ||
846 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
847 | { | |
848 | return -ENOTSUPP; | |
849 | } | |
850 | ||
bbf45ba5 HB |
851 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, |
852 | struct kvm_translation *tr) | |
853 | { | |
98001d8d AK |
854 | int r; |
855 | ||
98001d8d | 856 | r = kvmppc_core_vcpu_translate(vcpu, tr); |
98001d8d | 857 | return r; |
bbf45ba5 | 858 | } |
d9fbd03d | 859 | |
4e755758 AG |
860 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
861 | { | |
862 | return -ENOTSUPP; | |
863 | } | |
864 | ||
2986b8c7 | 865 | int __init kvmppc_booke_init(void) |
d9fbd03d HB |
866 | { |
867 | unsigned long ivor[16]; | |
868 | unsigned long max_ivor = 0; | |
869 | int i; | |
870 | ||
871 | /* We install our own exception handlers by hijacking IVPR. IVPR must | |
872 | * be 16-bit aligned, so we need a 64KB allocation. */ | |
873 | kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
874 | VCPU_SIZE_ORDER); | |
875 | if (!kvmppc_booke_handlers) | |
876 | return -ENOMEM; | |
877 | ||
878 | /* XXX make sure our handlers are smaller than Linux's */ | |
879 | ||
880 | /* Copy our interrupt handlers to match host IVORs. That way we don't | |
881 | * have to swap the IVORs on every guest/host transition. */ | |
882 | ivor[0] = mfspr(SPRN_IVOR0); | |
883 | ivor[1] = mfspr(SPRN_IVOR1); | |
884 | ivor[2] = mfspr(SPRN_IVOR2); | |
885 | ivor[3] = mfspr(SPRN_IVOR3); | |
886 | ivor[4] = mfspr(SPRN_IVOR4); | |
887 | ivor[5] = mfspr(SPRN_IVOR5); | |
888 | ivor[6] = mfspr(SPRN_IVOR6); | |
889 | ivor[7] = mfspr(SPRN_IVOR7); | |
890 | ivor[8] = mfspr(SPRN_IVOR8); | |
891 | ivor[9] = mfspr(SPRN_IVOR9); | |
892 | ivor[10] = mfspr(SPRN_IVOR10); | |
893 | ivor[11] = mfspr(SPRN_IVOR11); | |
894 | ivor[12] = mfspr(SPRN_IVOR12); | |
895 | ivor[13] = mfspr(SPRN_IVOR13); | |
896 | ivor[14] = mfspr(SPRN_IVOR14); | |
897 | ivor[15] = mfspr(SPRN_IVOR15); | |
898 | ||
899 | for (i = 0; i < 16; i++) { | |
900 | if (ivor[i] > max_ivor) | |
901 | max_ivor = ivor[i]; | |
902 | ||
903 | memcpy((void *)kvmppc_booke_handlers + ivor[i], | |
904 | kvmppc_handlers_start + i * kvmppc_handler_len, | |
905 | kvmppc_handler_len); | |
906 | } | |
907 | flush_icache_range(kvmppc_booke_handlers, | |
908 | kvmppc_booke_handlers + max_ivor + kvmppc_handler_len); | |
909 | ||
db93f574 | 910 | return 0; |
d9fbd03d HB |
911 | } |
912 | ||
db93f574 | 913 | void __exit kvmppc_booke_exit(void) |
d9fbd03d HB |
914 | { |
915 | free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER); | |
916 | kvm_exit(); | |
917 | } |